共查询到20条相似文献,搜索用时 31 毫秒
1.
随着集成电路制造工艺的发展,VLSI(Very Large Scale Integrated)电路测试面临着测试数据量大和测试功耗过高的问题.对此,本文提出一种基于多级压缩的低功耗测试数据压缩方案.该方案先利用输入精简技术对原测试集进行预处理,以减少测试集中的确定位数量,之后再进行第一级压缩,即对测试向量按多扫描划分为子向量并进行相容压缩,压缩后的测试向量可用更短的码字表示;接着再对测试数据进行低功耗填充,先进行捕获功耗填充,使其达到安全阈值以内,然后再对剩余的无关位进行移位功耗填充;最后对填充后的测试数据进行第二级压缩,即改进游程编码压缩.对ISCAS89基准电路的实验结果表明,本文方案能取得比golomb码、FDR码、EFDR码、9C码、BM码等更高的压缩率,同时还能协同优化测试时的捕获功耗和移位功耗. 相似文献
2.
LPTest: a Flexible Low-Power Test Pattern Generator 总被引:1,自引:1,他引:0
This paper presents a low power test pattern generator, LPTest, that minimizes the peak power consumption during the shift
and capture cycles for scan-based stuck-at and transition fault testing. LPTest incorporates both power-aware ATPG and low-power
X-filling techniques to achieve higher power reduction. Its enabling technique is a power estimation method which assesses
the lower-bounds of the shift-in, shift-out, and capture powers of a partially specified test pattern. The lower-bound estimation
method is utilized in LPTest’s ATPG engine, dynamic compaction, and X-filling. LPTest has been validated using ISCAS89 benchmark circuits. When considering all cycles, LPTest achieves better
than 22% peak WSA (weighted switching activity) reduction for stuck-at and transition faults compared to a commercial ATPG
with high merge ratio and random-fill options. Meanwhile, the average power reduction is better than 43%. When only capture
power is of concern, LPTest attains more than 46% WSA reduction for stuck-at and transitions. 相似文献
3.
Power consumption during scan testing operations can be significantly higher than that expected in the normal functional mode of operation in the field. This may affect the reliability of the circuit under test (CUT) and/or invalidate the testing process increasing yield loss. In this paper, a scan chain partitioning technique and a scan hold mechanism are combined for low power scan operation. Substantial power reductions can be achieved, without any impact on the test application time or the fault coverage and without the need to use scan cell reordering or clock and data gating techniques. Furthermore, the proposed design solution for scan power alleviation, permits the efficient exploitation of X-filling techniques for capture power reduction or the use of extreme (power independent) compression techniques for test data volume reduction. 相似文献
4.
Stephan Eggersglüß 《Journal of Electronic Testing》2014,30(5):557-567
Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel dynamic X-filling technique Opt-Justification-fill which uses optimization techniques to compute promising X-bits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as during a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increase is only small which leads to reduced test costs. 相似文献
5.
A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low‐power embedded systems. In scan‐based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph‐based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively. 相似文献
6.
Lung-Jen Lee 《Journal of Electronic Testing》2013,29(5):625-634
Eliminating the excessive test power for integrated circuits is a strict challenge within the nanometer era. This method combines test pattern generation with the scan chain disabling technique to achieve low capture power testing under the single stuck-at fault model. Testability analysis is exploited to assist in the test pattern generation process to generate the observation-oriented test patterns. In order to direct fault effects to the frequently-used circuit outputs, unbalanced observability costs are purposely assigned to circuit outputs to introduce unequal propagation probability. Observation-aware scan chain clustering is then performed through a weighted compatibility analysis to densely cluster the frequently-used scan cells into scan chains. Consequently, more scan chains can be disabled in the capture cycle and significant power reduction can be achieved without affecting the fault coverage. To simultaneously consider the reduction in large test data volume and capture power, the power-aware test vector compaction algorithm is also performed. Experimental results for the large ISCAS’89 benchmark circuits show that significant improvements can be simultaneously achieved including 71.7 % of capture power reduction, 43.7 % of total power reduction, 24.3 % of peak power reduction and 98.0 % of test data compaction ratios averagely. Results for three large ITC’99 benchmark circuits also demonstrate the effectiveness of the proposed method for the practical-scale circuits. 相似文献
7.
A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing. 相似文献
8.
A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements,
only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells
according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based
heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding
based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s
max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s
max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based
grouping heuristic, s
max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute
to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power
testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the
proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively
reduce the volume of the test data, with little area overhead, compared to the previous methods.
相似文献
Hong-Sik KimEmail: |
9.
Haiying Yuan Changshi Zhou Xun Sun Kai Zhang Tong Zheng Chang Liu Xiuyu Wang 《Journal of Electronic Testing》2018,34(6):685-695
Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression scheme, which produces enormous switching activities during circuit testing, thereby causing high test power consumption for scan design. To solve the above thorny problem, LFSR reseeding-oriented low-power test-compression architecture is developed, and an optimized encoding algorithm is involved in conjunction with any LFSR-reseeding scheme to effectively reduce test storage and power consumption, it includes test cube-based block processing, dividing into hold partition sets and updating hold partition sets. The main contributions is to decrease logic transitions in scan chains and reduce specified bit in test cubes generated via LFSR reseeding. Experimental results demonstrate that the proposed scheme achieves a high test compression efficiency than the existing methods while significantly reduces test power consumption with acceptable area overhead for most Benchmark circuits. 相似文献
10.
Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan‐in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't‐care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases. 相似文献
11.
Sobeeh Almukhaizim Shouq Alsubaihi Ozgur Sinanoglu 《Journal of Electronic Testing》2010,26(4):465-481
Scan-based testing of integrated circuits results in significant switching activity during the shift operations, dissipating
excessive power levels. When such levels are beyond the peak power level under which the chip can functionally operate at,
it may lead to an unexpected behavior of the design, resulting in a yield loss. One of the most effective solutions to reduce
peak shift power is to partition the scan chains into multiple groups, wherein a single group is active at any time instance
within a shift cycle. The partitioning of the chains into groups can be performed statically, i.e., per test set, or dynamically,
i.e., per test pattern. In this work, we address the application of dynamic scan chain partitioning for reducing peak shift
power. First, we address the application of dynamic partitioning to test delay faults in at-speed test techniques. Then, we
formulate the scan chain partitioning problem via Integer Linear Programming (ILP), in order to evenly distribute the transitions
produced by any pattern over multiple time instances within the shift cycle, maximally reducing the peak shift power. Finally,
we evaluate the power reduction benefit of dynamic partitioning through an extensive set of experiments using different scan
configurations and test set characteristics of benchmark circuits as well as industrial designs. The results indicate that
dynamic partitioning provides significant reduction to peak shift power over static partitioning methods, and that the benefit
is accentuated in scan architectures with fewer scan chains, test sets with more don’t care bits, and designs with larger
variances of weight differences for transitions in the scan cells. 相似文献
12.
In this paper, we show that not every scan cell contributes equally to the power consumption during scan-based test. The transitions
at some scan cells cause more toggles at the internal signal lines of a circuit than the transitions at other scan cells.
Hence the transitions at these scan cells have a larger impact on the power consumption during test application. We call these
scan cells power sensitive scan cells. A signal probability based approach is proposed to identify a set of power sensitive
scan cells. Additional hardware is added to freeze the outputs of power sensitive scan cells during scan shifting in order
to reduce the shift power consumption. Experimental results on industrial circuits show that on average more than 45% of the
scan shift power can be eliminated when freezing only 5% of power sensitive scan cells.
相似文献
Yu HuangEmail: |
13.
Sunghoon Chun YongJoon Kim Jung-Been Im Sungho Kang 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(6):649-654
To overcome the limitation of the automatic test equipment (ATE), test data compression/decompression schemes become a more important issue of testing for a system-on-chip (SoC). In order to alleviate the limitation of previous works, a new hybrid test data compression/decompression scheme for an SoC is developed. The new scheme is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed scheme, called the Modified Input reduction and CompRessing One block (MICRO), uses the modified input reduction, the one block compression, a novel mapping, and reordering algorithms. Unlike previous approaches using the cyclic scan register architecture, the proposed scheme is to compress original test data and to decompress the compressed test data without the cyclic scan register architecture. Therefore, the proposed scheme leads to high-compression ratio with low-hardware overhead. Experimental results on ISCAS '89 and ITC '99 benchmark circuits prove the efficiency of the new method. 相似文献
14.
Jia LiAuthor Vitae Xiao LiuAuthor VitaeYubin ZhangAuthor Vitae Yu HuAuthor VitaeXiaowei LiAuthor Vitae Qiang XuAuthor Vitae 《Integration, the VLSI Journal》2011,44(3):205-216
Ever-increasing test data volume and excessive test power are two of the main concerns of VLSI testing. The “don’t-care” bits (also known as X-bits) in given test cube can be exploited for test data compression and/or test power reduction, and these techniques may contradict to each other because the very same X-bits are likely to be used for different optimization objectives. This paper proposes a capture-power-aware test compression scheme that is able to keep capture-power under a safe limit with low test compression ratio loss. Experimental results on benchmark circuits validate the effectiveness of the proposed solution. 相似文献
15.
Growing test data volume and excessive testing power are both serious challenges in the testing of very large-scale integrated circuits. This article presents a scan power-aware deterministic test method based on a new linear decompressor which is composed of a traditional linear decompressor, k-input AND gates and T flip-flops. This decompression architecture can generate the low-transition deterministic test set for a circuit under test. When applying the test patterns generated by the linear decompressor, only a few transitions occur in the scan chains, and hence the switching activity during testing decreases significantly. Entire test flow compatible with the design is also presented. Experimental results on several large International Symposium on Circuits and Systems’89 and International Test Conference’99 benchmark circuits demonstrate that the proposed methodology can reduce test power significantly while providing a high compression ratio with limited hardware overhead. 相似文献
16.
Kessels J. Marston P. 《Proceedings of the IEEE. Institute of Electrical and Electronics Engineers》1999,87(2):257-267
We have designed asynchronous standby circuits for a pager decoder which dissipate four times less power and are 40% larger in size than synchronous designs. For the total pager unit this means a 37% reduction in power dissipation for nearly no additional area. The decoded chip, which apart from the standby circuits is completely synchronous, has been fabricated and was first-time-right. Two problems had to be solved to incorporate asynchronous subcircuits in a synchronous environment: synchronization and testing. A synchronization scheme is described that allows a free intermixing of asynchronous and synchronous modules and a test strategy is proposed in which the scan test facilities in the synchronous environment are used to test the asynchronous modules. One function is prevalent in the standby circuits, namely counting. In an appendix we present the asynchronous design of a so-called loadable counter whose power consumption does not depend on its size 相似文献
17.
18.
Test data compression using alternating variable run-length code 总被引:1,自引:0,他引:1
Bo YeAuthor Vitae Qian ZhaoAuthor VitaeDuo ZhouAuthor Vitae Xiaohua WangAuthor VitaeMin LuoAuthor Vitae 《Integration, the VLSI Journal》2011,44(2):103-110
This paper presents a unified test data compression approach, which simultaneously reduces test data volume, scan power consumption and test application time for a system-on-a-chip (SoC). The proposed approach is based on the use of alternating variable run-length (AVR) codes for test data compression. A formal analysis of scan power consumption and test application time is presented. The analysis showed that a careful mapping of the don’t-cares in pre-computed test sets to 1s and 0s led to significant savings in peak and average power consumption, without requiring slower scan clocks. The proposed technique also reduced testing time compared to a conventional scan-based scheme. The alternating variable run-length codes can efficiently compress the data streams that are composed of both runs 0s and 1s. The decompression architecture was also presented in this paper. Experimental results for ISCAS'89 benchmark circuits and a production circuit showed that the proposed approach greatly reduced test data volume and scan power consumption for all cases. 相似文献
19.
This paper presents a new test scheme based on scan block encoding in a linear feedback shift register (LFSR) reseeding-based compression environment.Meanwhile,our paper also introduces a novel algorithm of scan-block clustering.The main contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during scan shift and the number of specified bits that need to be generated via LFSR reseeding.Thus,it can significantly reduce the test power and test data volume.Experimental results using Mintest test set on the larger ISCAS’89 benchmarks show that the proposed method reduces the switching activity significantly by 72%-94%and provides a best possible test compression of 74%-94%with little hardware overhead. 相似文献
20.
The emergence of the nanometer scale integration technology made it possible for systems-on-a-chip, SoC, design to contain
many reusable cores from multiple resources. This resulted in higher complexity SoC testing than the conventional VLSI. To
address this increase in design complexity in terms of data-volume and test-time, several compression methods have been developed,
employed and proposed in the literature. In this paper, we present a new efficient test vector compression scheme based on
block entropy in conjunction with our improved row-column reduction routine to reduce test data significantly. Our results
show that the proposed method produces much higher compression ratio than all previously published methods. On average, our
scheme scores nearly 13% higher than the best reported results. In addition, our scheme outperformed all results for each
of the tested circuits. The proposed scheme is very fast and has considerable low complexity. 相似文献