Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead.     

基于概率表达式的MPRM电路功耗计算方法

采用基于信号概率的功耗计算模型进行MPRM（Mixed Polarity Reed-Muller）电路功耗优化,信号概率计算是功耗计算的关键.提出一种基于概率表达式的MPRM电路功耗计算方法.该方法兼顾信号概率计算的时间效率和准确性,对MPRM电路中不存在空间相关性的信号通过在电路中传播信号概率的方式计算其信号概率,存在空间相关性的信号则利用概率表达式计算其信号概率,并在电路中传播概率表达式以解决空间相关性问题,在此基础之上根据基于信号概率建立的解析动态功耗和静态功耗计算模型计算电路功耗.为进一步提高时间效率,该方法采用二元矩图表示概率表达式.使用基准电路对所提出方法进行了验证,并与其他采用不同信号概率计算方法的MPRM电路功耗计算方法进行了比较.结果表明所提出方法准确有效.     

触发器可靠度计算的F-PTM方法

传统的概率转移矩阵（PTM）方法是一种用于估计软错误对组合电路可靠度影响的有效方法,但传统PTM方法只适用于组合逻辑电路的可靠度评估.触发器是时序逻辑电路的重要组成部分,其可靠度评估对时序电路的可靠度分析研究至关重要.为此,本文提出了基于PTM的触发器可靠度计算的F-PTM方法及电路PTM的判定定理.F-PTM方法首先建立触发器电路的特征方程,再用电路PTM的判定定理生成触发器的PTM,最后,根据输入信号的概率分布函数计算出电路的可靠度.与传统PTM方法相比较,F-PTM方法既能计算组合电路的PTM,又能计算触发器电路的PTM,其通用性强.对典型的触发器电路和74X系列电路中的触发器电路的实验结果表明,F-PTM方法合理可行.与多阶段方法和Monte Carlo方法的实验结果相比较,F-PTM方法得到的结果更精确.     

Characterizing,modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits

Soft errors, due to cosmic radiations, are one of the major challenges for reliable VLSI designs. In this paper, we present a symbolic framework to model soft errors in both synchronous and asynchronous designs. The proposed methodology utilizes Multiway Decision Graphs (MDGs) and glitch-propagation sets (GP sets) to obtain soft error rate (SER) estimation at gate level. This work helps mitigate design for testability (DFT) issues in relation to identifying the controllable and the observable circuit nodes, when the circuit is subject to soft errors. Also, this methodology allows designers to apply radiation tolerance techniques on reduced sets of internal nodes. To demonstrate the effectiveness of our technique, several ISCAS89 sequential and combinational benchmark circuits, and multiple asynchronous handshake circuits have been analyzed. Results indicate that the proposed technique is on average 4.29 times faster than the best contemporary state-of-the-art techniques. The proposed technique is capable to exhaustively identify soft error glitch propagation paths, which are then used to estimate the SER. To the best of our knowledge, this is the first time that a decision diagram based soft error identification approach is proposed for asynchronous circuits.     

基于Pareto支配的MPRM电路面积与可靠性优化

针对MPRM（Mixed-Polarity Reed-Muller）电路的面积与可靠性折中优化问题,在逻辑级建立面积估算模型以及电路SER（Soft Error Rate）解析评价模型,并采用Pareto支配概念对MPRM电路进行面积与可靠性多目标优化.通过对MPRM电路的XOR部分进行树形异或门分解,并考虑多个输出之间异或门的共享,建立面积估算模型.采用信号概率和故障传播方法,并考虑电路中的逻辑屏蔽因素以及信号相关性,建立电路SER解析评价模型.根据所提出的面积和SER评价模型,采用极性向量的格雷码序穷举搜索MPRM的极性空间得到MPRM电路面积与可靠性的Pareto最优解集,并使用效率因子技术指标选取最终解.MCNC基准电路的实验结果表明,与面积最小MPRM电路相比,所选取的MPRM电路可以在较小面积开销的前提下获得较高电路可靠性.     

Soft Error Mitigation Through Selective Addition of Functionally Redundant Wires

We introduce a logic-level soft error mitigation methodology for combinational circuits. The proposed method exploits the existence of logic implications in a design, and is based on selective addition of pertinent functionally redundant wires to the circuit. We demonstrate that the addition of functionally redundant wires reduces the probability that a single-event transient (SET) error will reach a primary output, and, by extension, the soft error rate (SER) of the circuit. We discuss three methods for identifying candidate functionally redundant wires, and we outline the necessary conditions for adding them to the circuit. We then present an algorithm that assesses the SET sensitization probability reduction achieved by candidate functionally redundant wires, and selects an appropriate subset that, when added to the design, minimizes its SER. Experimental results on ISCAS'89 benchmark circuits demonstrate that the proposed soft error mitigation methodology yields a significant SER reduction at the expense of commensurate hardware, power, and delay overhead.     

Switching activity estimation of VLSI circuits using Bayesian networks

Switching activity estimation is an important aspect of power estimation at circuit level. Switching activity in a node is temporally correlated with its previous value and is spatially correlated with other nodes in the circuit. It is important to capture the effects of such correlations while estimating the switching activity of a circuit. In this paper, we propose a new switching probability model for combinational circuits that uses a logic-induced directed-acyclic graph (LIDAG) and prove that such a graph corresponds to a Bayesian network (BN), which is guaranteed to map all the dependencies inherent in the circuit. BNs can be used to effectively model complex conditional dependencies over a set of random variables. The BN inference schemes serve as a computational mechanism that transforms the LIDAG into a junction tree of cliques to allow for probability propagation by local message passing. The proposed approach is accurate and fast. Switching activity estimation of ISCAS and MCNC circuits with random and biased input streams yield high accuracy (average mean error=0.002) and low computational time (average elapsed time including CPU, memory access and I/O time for the benchmark circuits=3.93 s).     

基于概率转移矩阵的时序电路可靠度估计方法

传统的概率转移矩阵(Probabilistic Transfer Matrix,PTM)方法是一种能够比较精确地估计软差错对门级电路可靠度影响的方法,但现有的方法只适用于组合逻辑电路的可靠度估计.本文提出基于PTM的时序电路可靠度估计方法(reliability estimation of Sequential circuits based on PTM,S-PTM),先把待评估时序电路划分为输出逻辑模块和次态逻辑模块,然后用本文提出的时序电路PIM计算模型得到电路的PIM,最后根据输入信号的概率分布计算出时序电路的可靠度.用ISCAS 89基准电路为对象进行实验和验证,实验表明所提方法是准确和合理的.     

Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis

The application of current generation computing machines in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for reviewing the worst-case error behavior of computing devices for fault-tolerant computation. In this work, we propose an exact probabilistic error model that can compute the maximum error over all possible input space in a circuit-specific manner and can handle various types of structural dependencies in the circuit. We also provide the worst-case input vector, which has the highest probability to generate an erroneous output, for any given logic circuit. We also present a study of circuit-specific error bounds for fault-tolerant computation in heterogeneous circuits using the maximum error computed for each circuit. We model the error estimation problem as a maximum a posteriori (MAP) estimate [28] and [29], over the joint error probability function of the entire circuit, calculated efficiently through an intelligent search of the entire input space using probabilistic traversal of a binary Join tree using Shenoy-Shafer algorithm [20] and [21]. We demonstrate this model using MCNC and ISCAS benchmark circuits and validate it using an equivalent HSpice model. Both results yield the same worst-case input vectors and the highest percentage difference of our error model over HSpice is just 1.23%. We observe that the maximum error probabilities are significantly larger than the average error probabilities, and provides a much tighter error bounds for fault-tolerant computation. We also find that the error estimates depend on the specific circuit structure and the maximum error probabilities are sensitive to the individual gate failure probabilities.     

Power estimation methods for sequential logic circuits

Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2^N where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies     

基才Smoke仿真分析在器件降额设计中的应用

器件降额设计是电路可靠性设计中的一种常用方法。通过降额设计可以达到降低器件基本失效率、提高产品使用可靠性的目的。传统的降额设计存在计算量大、耗时长、是一种静态分析方法、无法估计器件瞬态应力的缺点,基于Smoke仿真分析的降额设计可以准确分析电路中各个器件的瞬态电应力和器件结温。并直接输出所有器件的应力分析和降额情况,从而大大提高了降额设计的准确性和效率。本文采用OrCAD公司PSpice软件中的Smoke高级分析模块,对飞机刹车控制电路的V/I转换模块进行了降额设计仿真,验证了该方案的可行性,从而为电路的降额设计提供了一种新的手段,说明在Smoke分析基础上进行降额设计的研究具有重要的实用意义。     

Reliability evaluation of logic circuits using probabilistic gate models

Logic circuits built using nanoscale technologies have significant reliability limitations due to fundamental physical and manufacturing constraints of their constituent devices. This paper presents a probabilistic gate model (PGM), which relates the output probability to the error and input probabilities of an unreliable logic gate. The PGM is used to obtain computational algorithms, one being approximate and the other accurate, for the evaluation of circuit reliability. The complexity of the approximate algorithm, which does not consider dependencies among signals, increases linearly with the number of gates in a circuit. The accurate algorithm, which accounts for signal dependencies due to reconvergent fanouts and/or correlated inputs, has a worst-case complexity that is exponential in the numbers of dependent reconvergent fanouts and correlated inputs. By leveraging the fact that many large circuits consist of common logic modules, a modular approach that hierarchically decomposes a circuit into smaller modules and subsequently applies the accurate PGM algorithm to each module, is further proposed. Simulation results are presented for applications on the LGSynth91 and ISCAS85 benchmark circuits. It is shown that the modular PGM approach provides highly accurate results with a moderate computational complexity. It can further be embedded into an early design flow and is scalable for use in the reliability evaluation of large circuits.     

NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach

Supply voltage assignment (SVA) can alleviate the performance aging induced by the negative bias temperature instability (NBTI) effect. However, due to the random characteristic of an actual system workload, it is difficult to estimate the aging rate and control the supply voltage reasonably. To solve this problem, we present a workload-aware SVA method (WSVA) that encapsulates the workload change into the aging estimation using an LUT-based approach. Moreover, an NBTI and leakage co-optimization strategy based on an integer linear programming (ILP) approach is proposed to obtain the optimal input vector in standby mode. Simulation experiments on multiple benchmark circuits demonstrate that the LUT-based approach can track the dynamic change of the workload online and provide an accurate aging estimate for SVA with little computation cost. Compared with the SVA method without considering the workload, the proposed aging estimation approach and the optimal input vector selection strategy in the WSVA framework can enable the CMOS circuit conserve additional power dissipation while guaranteeing the performance requirements.     

Least-square estimation of average power in digital CMOS circuits

The estimation of average-power dissipation of a circuit through exhaustive simulation is impractical due to the large number of primary inputs and their combinations. In this work, two algorithms based on least square estimation are proposed for determining the average power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits. Least square estimation converges faster by attempting to minimize the mean square error value during each iteration. Two statistical approaches namely, the sequential least square (SLS) estimation and the recursive least square estimation are investigated. The proposed methods are distribution independent in terms of the input samples, unbiased and point estimation based. Experimental results presented for the MCNC'91 and the ISCAS'89 benchmark circuits show that the least square estimation algorithms converge faster than other statistical techniques such as the Monte Carlo method and the DIPE     

Accurate Estimation of SRAM Dynamic Stability

In this paper, an accurate approach for estimating SRAM dynamic stability is proposed. The conventional methods of SRAM stability estimation suffer from two major drawbacks: 1) using static failure criteria, such as static noise margin (SNM), which does not capture the transient and dynamic behavior of SRAM operation and 2) using quasi-Monte Carlo simulation, which approximates the failure distribution, resulting in large errors at the tails where the desired failure probabilities exist. These drawbacks are eliminated by employing a new distribution-independent, most-probable-failure-point search technique for accurate probability calculation along with accurate simulation-based dynamic failure criteria. Compared to previously published techniques, the proposed technique offers orders of magnitude improvement in accuracy. Furthermore, the proposed technique enables the correct evaluation of stability in real operation conditions and for different dynamic circuit techniques, such as dynamic write-back, where the conventional methods are not applicable.      

Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models

Using the behavioral model of a circuit to perform behavioral Monte Carlo simulation (BMCS) is a fast approach to estimate performance shift under process variation with detailed circuit responses. However, accurate Monte Carlo analysis results are difficult to obtain if the behavioral model is not accurate enough. Therefore, this paper proposes to use an efficient bottom-up approach to generate accurate process-variation-aware behavioral models of CPPLL circuits. Without blind regressions, only one input pattern in the extraction mode sufficiently obtains all required parameters in the behavioral model. A quasi-SA approach is also proposed to accurately reflect process variation effects. Considering generic circuit behaviors, the quasi-SA approach saves considerable simulation time for complicated curve fitting but still keeps estimation accuracy. The experimental results demonstrate that the proposed bottom-up modeling flow and quasi-SA equations provide similar accuracy as in the RSM approach, using less extraction cost as in the traditional sensitivity analysis approach.      

Cosmic-ray soft error rate characterization of a standard 0.6-μmCMOS process

Cosmic-ray soft errors from ground level to aircraft flight altitudes are caused mainly by neutrons. We derived an empirical model for estimation of soft error rate (SER). Test circuits were fabricated in a standard 0.6-μm CMOS process. The neutron SER dependence on the critical charge and supply voltage was measured. Time constants of the noise current were extracted from the measurements and compared with device simulations in three dimensions. The empirical model was calibrated and verified by independent SER measurements. The model is capable of predicting cosmic-ray neutron SER of any circuit manufactured in the same process as the test circuits. We predicted SER of a static memory cell     

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients

As technology scales down, more single-event transients (SETs) are expected to occur in combinational circuits and thus contribute to the increase of soft error rate (SER). We propose a systematic analysis method to precisely model the SET latching probability. Due to the decreased critical charge and shortened pipeline stage, the SET duration time is likely to exceed one clock cycle. In previous work, the SET latching probability is modeled as a function of SET pulse width, setup and hold times, and clock period for single-cycle SETs. Our analytical model does not only include new dependent parameters such as SET injection location and starting time, but also precisely categorizes the SET latching probabilities for different parameter ranges. The probability of latching multiple-cycle SETs is specifically analyzed in this work to address the increasing ratio of SET pulse width over clock period. We further propose a method that exploits the boundaries of those dependent parameters to accelerate the SER estimation. Simulation results show that the proposed analysis method achieves up to 97% average accuracy, which is applicable for both single- and multiple-cycle SETs. Our case studies on ISCAS’85 benchmark circuits confirm our analysis on the impact of SET injection location and starting time on the SET latching probability. By exploiting our analytical model, we achieve up to 78% simulation time reduction on the process of SET latching probability and SER estimation, compared with Monte-Carlo simulation.     

A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits

Nano-scale digital integrated circuits are getting increasingly vulnerable to soft errors due to aggressive technology scaling. On the other hand, the impacts of process variations on characteristics of the circuits in nano era make statistical approaches as an unavoidable option for soft error rate estimation procedure. In this paper, we present a novel statistical Soft Error Rate estimation framework. The vulnerability of the circuits to soft errors is analyzed using a newly defined concept called Statistical Vulnerability Window (SVW). SVW is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the given circuit. The SER is calculated using a probabilistic formulation based on the parameters of SVWs. Experimental results show that the proposed method provides considerable speedup (about 5 orders of magnitude) with less than 5 % accuracy loss when compared to Monte-Carlo SPICE simulations. In addition, the proposed framework, keeps its efficiency when considering a full spectrum charge collections (more than 36X speedups compared to the most recently published similar work).