Power cycling test and failure analysis of molded Intelligent Power IGBT Module under different temperature swing durations

Molded IGBT modules are widely used in low power motor drive applications due to their advantage like compactness, low cost, and high reliability. Thermo-mechanical stress is generally the main cause of degradation of IGBT modules and thus much research has been performed to investigate the effect of temperature stresses on IGBT modules such as temperature swing and steady-state temperature. The temperature swing duration is also an important factor from a real application point of view, but there is a still lack of quantitative study. In this paper, the impact of temperature swing duration on the lifetime of 600 V, 30 A, 3-phase molded Intelligent Power Modules (IPM) and their failure mechanisms are investigated. The study is based on the accelerated power cycling test results of 36 samples under 6 different conditions and tests are performed under realistic electrical conditions by an advanced power cycling test setup. The results show that the temperature swing duration has a significant effect on the lifetime of IGBT modules. Longer temperature swing duration leads to the smaller number of cycles to failure. Further, it also shows that the bond-wire crack is the main failure mechanism of the tested IGBT modules.     

A novel multiple-stress-based predictive model of LEDs for rapid lifetime estimation

This paper proposes a novel multiple-stress-based predictive model (MSBPM) to rapidly assess the lifetime of light-emitting diodes (LEDs). The MSBPM addresses the lifetime estimation of LEDs with respect to temperature, humidity, and current; these three stresses are rarely considered simultaneously in the assessment of reliability. Using several degradation data sets from accelerated life tests (ALTs) without using extrapolation method, a designed adaptive genetic algorithm is employed to identify five unknown parameters of the MSBPM. A simulation of the proposed MSBPM is presented as validation. By applying the degradation data from the ALTs under high stresses, an MSBPM for the LEDs is established. Under the nominal conditions of 25 °C/22.5% RH and a current of 0.35 A, the lifetime of the LED is estimated using the established MSBPM. The effectiveness of the proposed MSBPM is further verified through the estimated results.     

Stressing organic light-emitting diode under constant-brightness driving mode

The degradation of the organic light-emitting diodes (OLEDs) was studied under the constant-brightness driving mode. The time-dependent current exhibits a long period of linear increase followed by an exponential increase before the eventually catastrophic failure featured by a vertical increase. A new lifetime T_th is defined as the time for the device to reach the end of the linear increase stage. Similar to the well-known relation between the lifetime and the brightness in the constant-current driving mode, the lifetime and the brightness in the constant-brightness driving mode also fit the formula Lⁿ × T_th = Const., where L is the brightness and n is the acceleration exponent. By examining the current density–voltage–luminance characteristics and the photoluminescence intensity of the devices before and after the stress, it is found that both the reduction of the charge injection efficiency, and the loss of the emissive centers, contribute to the OLEDs’ degradation. The extra power supplied to the device to keep the brightness constant, raises the junction temperature, and eventually leads to the catastrophic failure of the devices.     

Lifetime tests of 600-V GaN-on-Si power switches and HEMTs

We present the first systematic lifetime tests which show excellent long-term reliability for 600 V GaN-on-Si power switches.High voltage accelerated life testing in the OFF-state yields a field related mean-time-to-failure (MTTF) greater than 3 × 10⁸ h for a 600 V operating condition. High temperature accelerated testing in the ON-state gives an MTTF of about 6 × 10⁸h at a 150 °C use condition. High temperature operating life testing using hard switched boost converters at 175 °C shows no measurable device degradation after 3000 h of operation. These results show that the intrinsic reliability of the new device technology is more than adequate for commercial and industrial power electronics applications.     

Degradation behaviors of GaN light-emitting diodes under high-temperature and high-current stressing

A number of commercially available multiple-quantum well (MQW) InGaN/GaN blue LEDs with wavelengths of about 460 nm and a power of 1 mW were stressed at temperatures ranging from 25 to 120 °C at several accelerated DC currents. Both the forward and reverse current voltage characteristics as well as the electroluminescent spectra of the LEDs were monitored. These effects also resulted in the pronounced degradation of light efficiency and device operation lifetime. We found that the degradation of photonic characteristics, correlated very well with the generation-recombination current which is governed by the defect density. The device degradation is much faster at high temperatures. At nominal operation current and at room temperature, the light intensity degradation reaches a saturation level before the light dyes out. These results shed new lights upon the design and lifetime specifications for the emerging commercial solid-state lighting devices.     

Analysis and resolution of a thermally accelerated early life failure mechanism in a 40 V GaN FET

An early life failure mechanism was discovered on a 0.25-µm 40 V GaN FET technology. Through accelerated life testing (ALT), it was determined that the early life failure mechanism was thermally accelerated with a high activation energy, which means that it is not a concern a normal operating conditions up to the maximum rated junction temperature. Subsequent improvements to the process resulted in elimination of the early life failure mechanism. With the improved process, single-mode ALT lifetime distributions and excellent reliability performance down to low failure fractions were demonstrated.     

Useful lifetime analysis for high-power white LEDs

An accelerated degradation test is used to analyze the useful lifetime of high-power white light-emitting diodes (HPWLEDs) as the point at which the light output declines to 70% of the initial flux in lumens, called L₇₀ In this study, the degradation-data-driven method (DDDM), including the approximation method, the analytical method, and the two-staged method, is used to analyze the useful lifetime of HPWLEDs. A response model based on an inverse power (exponential) law under different stresses is used to predict the useful lifetime under operating conditions. However, the degradation model for each HPWLED is usually fitted to an exponential function. In order to improve the fit accuracy, we present a bi-exponential model for the degradation curve of HPWLEDs. The estimation of the model parameters are easily obtained by using the nonlinear least square method. Through numerical examples, the results show that the bi-exponential model performs better than the exponential model based on the two-staged method. The extrapolation algorithm for L₇₀ should be fitted to a bi-exponential extrapolation model and two-staged method.     

Reliability of submicron InGaAs/InP DHBT under thermal and electrical stresses

We report on the reliability of InGaAs/InP DHBT technology which has applications in very high-speed ICs (over 100 Gbits/s). This work presents the results of accelerated aging tests under thermal and electrical stresses performed on HBT up to 2000 h. Stress conditions consist in applying collector–emitter bias V_CE from 1.3 to 2.7 V and collector current densities J_C of 400 and 610 kA/cm². The corresponding junction temperatures T_J extends from 83 to 137 °C. The base current ideality factor η_B increase and the current gain β decrease have revealed a degradation of the base–emitter junction. The normalized current gain β_norm drop has occurred earlier for higher V_CE and/or higher T_J. A 20% decrease of β_norm chosen as the failure criterion leads to an activation energy of 1.1 eV.     

Performance drifts of N-MOSFETs under pulsed RF life test

This paper presents a reliability life test bench specifically dedicated to high RF power devices for lifetime tests under pulse conditions. The monitoring of RF power, drain, gate voltages and currents under various pulses and temperatures conditions are investigated. A 3000 h pulsed RF life test has been conducted on a dedicated RF S-band test bench in operating modes. The investigation findings of degradations of critical electrical parameters derived from the data treatment after this accelerated ageing tests are presented. Numerous duty cycles are applied in order to stress Lateral-Diffused Metal-Oxide-Semiconductor (LDMOS). It shows with tracking of a set of RF parameters (P_out, Gain and Drain Efficiency: DE) that the dominant degradation phenomenon is linked to hot carriers generated interface states (traps) and trapped electrons. Which results in a build up of negative charge at Si/SiO₂ interface and the main cause appear with incidence on RF power device. Physical simulation software (Silvaco-Atlas) has been used to locate and confirm these phenomena.     

The reliability of component boards studied with different shock impact repetition frequencies

As a result of the ever-shortening time to market of new electronic products there is a clear need to make the currently employed reliability assessment procedures more efficient. However, while trying to achieve these cost savings it is important to pay attention to how much reliability tests can be accelerated without producing misleading lifetime statistics or irrelevant failure modes and mechanisms. Therefore, the primary objective of this work was to clarify the effects of impact repetition frequency on the lifetime and failure mechanisms of electronic component boards. The reliability assessments were conducted with four package types (BGA288, BGA144, QFN72, and μSMD36) with the intention of including different package dimensions and interconnection shapes and sizes in the scope of evaluation. Three shock impact repetition frequencies (0.01 Hz, 0.1 Hz, and 1.6 Hz) were used to study the sensitivity of their lifetime to the time between the shock impacts. The results showed that the impact repetition frequency has a significant effect on the average lifetime of the studied packages: the average number of impacts-to-failure increased with increased impact repetition frequency. A change in the impact repetition frequency did not, however, change the primary failure mode and the failure mechanism. In order to explain this observation, the formation of residual stresses in the solder interconnections from shock impacts and their relaxation during the time between the shock impacts were evaluated by employing FEM, which showed that at room temperature the stress relaxation by creep of solder is significant even at less than 10 s time frame. The effect of the stress relaxation on the lifetime of the component boards was studied experimentally by repeating the impact tests at elevated temperature with the intention of influencing rate of stress relaxation. The results showed that the relaxation of the residual stresses has a significant effect on the component boards shock reliability (at less than 1% risk level). The results presented in this paper indicate that the impact repetition frequency should be taken into account, especially when reliability assessments are being carried out with different testers, since the interval between the shock impacts varies from one test system to another.     

Accelerated life test of high power white light emitting diodes based on package failure mechanisms

Accelerated life tests of high-power white light emitting diodes (LEDs) were conducted under an unbiased highly accelerated temperature and humidity test (HAST) and a normal aging test. The conditions in the unbiased HAST were 110 °C-85% RH, 130 °C-85% RH without bias. During the aging, the degradation mechanisms of optical power reduction and degradation of 455 mm blue wavelengths that were better than phosphors related yellow emission bands were observed. The microscopy analysis showed that this effect could be ascribed to the bubbling and discoloration of the silicone encapsulating material of the package. It is thought that these features are also responsible for the optical power reduction and thermal resistance increase.     

Creep lifetime prediction of solder joint for heat sink assembly

The heat sink assembly in a server station is anticipated to creep to fail at the solder joint under a constant load and temperature condition. To predict the lifetime of solder joint in the system, accelerated creep-rupture tests are conducted. Three loads of 4, 6, and 8 kg and temperatures of 35, 55, and 65 °C are selected for the tests. Larson–Miller model is adopted for the lifetime prediction, which requires tested lifetime data and stress analyses for the solder joint. An FE model for the stress analyses is developed and validated experimentally. Analyzed Larson–Miller constants show different tendency in the 8 kg load cases. Extensive failure analyses on the failed solder joints reveal the transition of failure mechanism at 8 kg load cases from the intergranular to the transgranular creep. Using only the validated test data of 4 and 6 kg load cases, creep lifetime prediction model for the solder joint in the heat sink assembly is developed and applied for a field condition.     

Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits

In this work, we investigate the co-dependency of die temperature and bias temperature instability (BTI) and their combined effect on the lifetime of VLSI circuits. The investigation considers the impact of die temperature in increasing the effect of the BTI as well as changes in the die temperature due to the BTI-induced threshold voltage alterations. In addition, the impact of workloads on the degree of the BTI-induced degradation in VLSI circuits is studied. This impact accounts for the direct influence of the signal probability of the internal nodes under the given workload as well as its indirect influence due to power consumption and temperature changes of the circuits. The study is performed by using a simulation framework that captures dynamic changes in the operating temperature and application workload. Simultaneous consideration of the dynamic workload and operating temperature enables one to accurately predict the circuit lifetime. To assess the accuracy of the proposed approach, the estimated delay degradations caused by the Negative BTI (NBTI) for some large circuits from ISCAS'89 and ITC'99 benchmark suites when circuits are simulated under dynamic (both temperature and workload are updated periodically), semi-static (either temperature or workload is updated periodically), and static (no updating is performed) scenarios are compared. Simulation results obtained in a 45 nm CMOS technology, reveal that the predicted timing degradation in the case of the dynamic scenario is significantly different than those of the other scenarios. The differences ranged from − 135% to + 98% for the considered circuits in this work. The large differences demonstrate that for accurate estimation of the circuit lifetime under the BTI effect, the dynamic scenario should be adopted as part of the standard design flows.     

Interface reliability and lifetime prediction of heavy aluminum wire bonds

In this study a high frequency mechanical fatigue testing procedure for evaluation of interfacial reliability of heavy wire bonds in power semiconductors is presented. A displacement controlled mechanical shear testing set-up working at a variable frequency of a few Hertz up to 10 kHz is used to assess the interfacial fatigue resistance of heavy Al wire bond in IGBT devices. In addition, power cyclic tests were conducted on IGBT modules for in-situ measurement of the temperature distribution in the devices and determination of the thermally induced displacements in the wire bond loops. Finite Element Analysis was conducted to calculate the correlation between the thermally and mechanically induced interfacial stresses in the wire bonds. These stress values were converted into equivalent junction temperature swings (ΔT_j) in the devices based on which lifetime curves at different testing frequencies were obtained. Comparison of the fatigue life curves obtained at mechanical testing frequencies of up to 200 Hz with the power cycling data related to the wire bond lift-off failure revealed a very good conformity in the ranges of 50 to 160 K. A lifetime prediction model for Al wire bonds in IGBT modules is suggested by which the loading cycles to failure can be obtained as a function of ΔT_j and the mechanical testing frequency. The proposed accelerated shear fatigue testing procedure can be applied for rapid assessment of a variety of interconnects with different geometries and material combinations. Decoupling of the concurrent failure mechanisms and separation of the thermal, mechanical and environmental stress factors allows a more focused and efficient investigation of the interfaces in the devices.     

Lifetime and manufacturability of integrated power electronics

In case of battery electric cars, market data show a traditional exponential gradient of sales figures, known from other technology transitions. The worldwide installed wind and photovoltaic capacity show also an exponential gradient. Even the power density of power electronics is growing exponentially.Power electronics is a prerequisite to enable the exponential growth of power density.Requirements on power electronic packaging technologies are electric performance, thermal performance and robust design. Due to the lack of bond wires, SMD capacitors can be mounted close to semiconductors, resulting in a minimization of parasitic inductance. Thermally, the packaging technology benefits from heat spreading inside the copper leadframe and thin dielectric layers. It obtains a thermal resistance of 0.5 K/W, and there is potential to further reduce the thermal resistance by alternative dielectric material. The thermal resistance can be further reduced to at least 0.42 K/W by the construction of a double side chip cooling.A robust design can be offered by the combination of a chip copper metallization connecting to copper microvias connecting to the top copper layer, which means no difference in coefficients of thermal expansion. On the bottom side, a silver sinter layer offers a reliable connection between chip and leadframe.This paper describes production process optimizations, thermal optimization possibilities, power cycling lifetime measurements and first conductive anodic filament lifetime measurements at 1000 V DC. The outlook onto an integrated 120 A 700 V SiC MOSFET demonstrator is given.     

End of life and acceleration modelling for power diodes under high temperature reverse bias stress

This work is motivated by the growing importance of lifetime modelling in power electronics. Strongly accelerated High Temperature Reverse Bias (HTRB) testing of power diodes at different stress conditions is performed until alterations and fatigue mechanisms become evident. Two categories of effects can be separated: Drifting breakdown voltage and hard failures with complete loss of blocking capability. Nevertheless the overall stress duration needed to provoke destructive failures is very high with test durations > 2500 h even at almost 230 °C and 100% rated voltage. For both mechanisms the temperature and voltage acceleration is evaluated. Especially temperature acceleration is significant in the regime of testing between 200 °C and 230 °C and an activation energy E_a in the regime > 1 eV can be deduced which is higher compared to values commonly reported in the literature. Failure analysis shows that both package and also chip related effects could contribute to the observed hard failures in HTRB stress under extreme conditions.     

Fluid–solid coupling thermo-mechanical analysis of high power LED package during thermal shock testing

The virtual design by numerical simulation to model various accelerated reliability testing conditions is adopted to validate and improve the reliability of the high power LED package. In this study, the reliability of the high power LED package during thermal shock testing is investigated by fluid–solid coupling thermo-mechanical modeling by considering nonlinear time and temperature dependent material properties. Through fluid–solid coupling transient thermal transfer analysis, it is found that the maximum thermal gradient exceeds 75 K during the rapid cooling process and 91 K during the rapid heating process of the thermal shock testing which is ignored in the traditional isothermal assumption. The calculation results indicate that the equivalent plastic strain range of the bonding wire within the LED package with consideration of the temperature gradient is much higher than that with the isothermal assumption. The assumption of the isothermal condition is not appropriate which will lead to overestimation of the predicted lifetime. The viscoelastic behaviors of the silicone have significant influences on the lifetime prediction of the bonding wire and silicone with low elastic modulus and coefficient of thermal expansion (CTE) can significantly enhance the reliability of the bonding wire under the thermal shock loading. The results in this study could provide a guideline on design for reliability in the high power LED packaging.     

Long-term NBTI degradation under real-use conditions in IBM microprocessors

Long-term measurement of bias temperature instability (BTI) degradation obtained from an on-chip sensor is presented. The sensor reports measurements periodically with a digital output. Implemented on IBM’s z196 enterprise systems using IBM 45 nm technology, it can be used to monitor long-term degradation under real-use conditions. Over 700 days worth of ring oscillator degradation data from customer systems is presented. The data obtained by this sensor are consistent with models based on accelerated testing.     

An exploration for the degradation behavior of 2-D electrostatic microscanners by accelerated lifetime test

Failure analysis for the MEMS device is a crucial step in understanding the root causes of failure and improving the performance of the device. In order to explore the degradation failure mechanisms of 2-D electrostatic microscanners, three steps were addressed in this paper. Firstly, the stress distribution of the microscanner under its operation state was simulated using the finite element method (FEM), and the results showed that the middle part on the frame torsion beam was the most critical place. In the second step, accelerated lifetime test (ALT) was performed to shorten the time-to-failure period. Thirty well-conditioned devices participated in the experiment with continuous operation modes. Finally, five failures were observed by scanning electron microscope (SEM), and pull-in was found to be the main failure mode. In particular, a new appearance (wrinkling) was found at the most critical place obtained by previous simulation, and the natural frequencies of failed microscanners declined in accordance with the characteristic degradation trend before they failed. In this paper, it was proved that for electrostatic microscanners, the degradation of the mechanical properties after a long period of cyclic torsion work was the cause that induced pull-in failure, and the degradation was embodied by the wrinkling appearance. Besides, based on the experimental data, a working life of 15.8 years at 298 K for microscanners was obtained by further calculation.     

Voltage dependent degradation of HfSiON/SiO2 nMOSFETs under positive bias temperature instability

This paper investigates voltage-dependent degradation of HfSiON/SiO₂ nMOSFETs under conditions of positive bias temperature instability (PBTI), and proposes a PBTI degradation model that can use data from acceleration tests to predict device lifetime accurately. Experimental results show that the PBTI stress generated shallow traps in HfSiON and the exponent of power-law for threshold-voltage shift increased exponentially with an increase of PBTI stress voltage. An enhancement factor that represents creation of shallow charge traps in gate dielectric by PBTI stress was included in the proposed model. The proposed model predicted operational lifetime t_L = 1.64 × 10¹⁰ s, which agreed well with the t_L = 1.92 × 10¹⁰ s measured at low gate stress voltage, whereas the conventional model overestimates t_L by an order of magnitude, demonstrating that the proposed model is very useful on shortening the measurement time for estimating t_L of high-k nMOSFETs.