Efficient optimization of integrated spiral inductor with bounding of layout design parameters

In this paper we present an efficient method of determining the optimized layout of on chip spiral inductor. The method initially identifies the feasible region of optimization by developing layout design parameter bound curves for a large range of physical inductance values that satisfies the same area specification. For any desired inductance value the upper and lower bounds of the optimization variables are determined graphically. An enumeration algorithm implemented finds the global optimum layout that gives the highest quality factor in less than 1 s of CPU time with less function evaluations. The optimization method also gives the performance of all possible combinations that results the same inductance value. Subsequently important fundamental tradeoff of the design like quality factor and area, quality factor and inductance, quality factor and operating frequency, maximum quality factor and the peak frequency is explored in few seconds. The method also gives other valuable information such as sensitivity of the inductance and quality factor to the layout design parameters. The accuracy of the proposed method is verified using a 3D electromagnetic simulator.     

Characterization of novel varistor+inductor integrated passive devices

This letter describes the design, modeling, simulation, and fabrication of novel integrated passive devices (IPDs). These IPDs, comprising of a cofired multilayered varistor and inductor, have been developed in the ceramic coprocessing technology. The equivalent model of the new structures is presented, suitable for design and circuit simulations. The fabrication method, new design of structures and patented materials of these devices lead to improved characteristics suitable for application in high-frequency suppressors. The IPDs were tested in the frequency range of 1 MHz-3 GHz using an Agilent 4287A RF LCR meter. The measurements confirm the validity of the proposed model.     

系统集成中的高阻硅IPD技术

集成无源器件(IPD)技术可以将分立的无源器件集成在衬底内部,提高器件Q值及系统集成度。由于高阻硅衬底具有良好的射频特性,高阻硅IPD技术可以制备出Q值高达70以上的电感。高阻硅IPD基于薄膜技术具有高精度、高集成度等特点,可将无源器件特征尺寸缩小一个数量级。同时可利用成熟的硅工艺平台,便于批量生产降低成本。此外,高阻硅IPD技术可与硅通孔(TSV)技术兼容,可实现三维叠层封装。分析表明,高阻硅IPD技术在系统集成中具有广泛应用前景。     

光无源器件技术发展综述（续）

5　光开关当今世界各国都在研究和开发以 DWDM为基础的全光网络。全光网络的迅速发展将带来通信网的一场新的革命 ,人们将有望通过全光器件实现信息无瓶颈的高速传输。光开关是光交换机的核心元件 ,在全光网络中 ,高密度光开关矩阵能够完成开关、路由以及主要网络中枢的交叉连接的任务 ,许多光纤干线、各个载波多路光信道都可以端接 ;光开关已向智能型光开关发展 ,进入密集波分复用光网 ,简化复杂的全光网络系统。随着人们对光开关的材料、器件原理与加工工艺认识的不断深入 ,研究光开关阵列的类型也呈多元化发展趋势。已报道的光开关如按…     

光无源器件技术发展综述

全光通信是光通信发展的必然方向 ,光无源器件是构建全光通信网络的重要基础。介绍了光无源器件——连接器、耦合器、光开关、衰减器、波分复用器、隔离器等器件的发展情况及现状。重点介绍了作为新一代光交换系统所需的核心器件光开关的发展和现状。对光无源器件未来发展的情况进行了概略的分析和预测。     

Analytical wide-band modeling of high frequency resistance in integrated spiral inductors

For integrated spiral inductor synthesis, designers and design automation tools require efficient modeling techniques during the initial design space exploration process. In this paper, we introduce an analytical frequency-dependent resistance model for integrated spiral inductors. Based on our resistance formulation, we have developed a systematic technique for creating wide-band circuit models for accurate time domain simulation. The analytical resistance model provides a fast alternative to field solver-based approaches with typical errors of less than 2.6 percent while surpassing the accuracy of several other analytical modeling techniques by an order of magnitude. Furthermore, the wide-band circuit generation technique captures the frequency-dependent resistance of the inductor with typical errors of less than 3.2 percent.     

Process modeling of integrated circuit device technology

This paper reviews the field of computer-aided design as applied to process modeling of integrated circuit technology and devices. Device design applications for process modeling are considered for both bipolar and NMOS technologies. The kinetics of oxidation and impurity diffusion in silicon are discussed. The numerical solution of impurity diffusion is considered, including grid and time step constraints. New efforts in two-dimensional process modeling are briefly discussed along with test structure work needed for parameter estimation.     

Micromachined planar spiral inductor in standard GaAs HEMT MMICtechnology

A novel free-standing planar spiral inductor with reduced parasitic capacitances is proposed by suspending individually the strips, through a maskless front-side bulk micromachining compatible with a commercial GaAs HEMT monolithic microwave integrated circuit (MMIC) technology. Suspended structures have been fabricated and characterized at frequencies up to 15 GHz, showing quality factors of up to 16 and self-resonant frequency superior to 16 GHz for a 4.8 nH inductor. Moreover, since the standard IC process as well as the unconcerned electronic circuits are not influenced by micromachining, such devices are directly useful to enhance RF circuits, like matching networks, filters, and low-noise amplifiers     

Isoplanar integrated injection logic: a high-performance bipolar technology

A newly developed technology is discussed. The emphasis of this approach is on achieving high packing density and high performance by use of various process innovations combined with topological design variations. Factors affecting packing density, DC as well as power delay product in I/SUP 2/L are analyzed and design considerations for the new structure are given. The results of computer simulations and measured device parameters and power delay are given. The following gate performance has been obtained at 100-/spl mu/A injector current, /spl beta/u/spl sime/2-4 for all four collectors, speed <10 ns for fan-out of four, speed <5 ns for a fan-out of one. At low currents a speed power product is 0.15 pJ. A packing density of more than 300 gates/mm/SUP 2/ including interconnect and power bussing has been achieved.     

The design and optimization of high-performance, double-polyself-aligned p-n-p technology

The device design and performance of double-poly self-aligned p-n-p technology, featuring a low-resistivity p⁺ subcollector, thin p-epi, and boron-doped poly-emitter are described. Device isolation is provided by deep and shallow trenches which reduce the collector-to-substrate capacitance while maintaining a high breakdown voltage (⩾40 V). By utilizing a shallow emitter process in conjunction with an optimized arsenic-base implant, devices with emitter-base junction depths as shallow as 20 nm and base widths of less than 100 nm were obtained. Cutoff frequencies of up to 27 GHz were obtained, and the AC performance was demonstrated by an NTL-gate delay of 36 ps and an active-pull-down (APD) ECL-gate delay of 20 ps. This high-performance p-n-p technology was developed to be compatible with existing double-poly n-p-n technologies. The matching speed of p-n-p devices opens up new opportunities for high-performance complementary bipolar circuits     

Fabrication and performance of a novel suspended RF spiral inductor

A novel suspended radio frequency (RF) spiral inductor was fabricated on glass substrate by using the microelectromechanical systems (MEMS) technology. The suspended spiral inductor is sustained with the T-shaped pillars. Great improvements in Q-factor have been achieved because of the separation between the substrate and the inductor. In the fabrication process, fine polishing of the photoresist is used to simplify the processes and ensure the seed layer and the pillars contact perfectly, and dry etching technique is used to remove the seed layer. The inductance and Q-factor are measured using the HP 8722D network analyzer in the frequency range of 0.05-10 GHz. The maximum quality factor of this inductor is 37 for the inductance of 4.2 nH with a suspended height of 60 /spl mu/m. Also, the relationship between the maximum quality factor and the suspended height were studied; the maximum quality factor grows gradually with the increase of the suspended height.     

CMOS planar spiral inductor modeling and low noise amplifier design

During this study, various narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for GSM and S-band low earth orbit (LEO) space applications have been designed, simulated and compared using Mietec CMOS 0.7 μm process and the Cadence/BSIM3v3. To get more realistic results, parasitic effects due to layout have been calculated and added to the simulations. Also, considering the inductive source degenerative topology, most of the attention is given on the modeling of planar spiral inductor by lumped element circuits. Moreover to decrease the substrate effects, the inductors have been surrounded by grounded guard rings and have patterned ground shield (PGS) under them. The simulation results of LNA including the parasitic effects indicate a forward gain of 9 dB with noise figure of 4.5 dB while drawing 18 mW from+3 V supply at 2210 MHz. The area occupied is 1.8 mm×1.6 mm with pads, 1.3 mm×1.2 mm without pads.     

System-level design consideration and optimization of through-silicon-via inductor

Due to the slow scaling of board and package technology, on-chip inductor has shown promising potential to enable more compact design and smaller parasitics for inductor-based designs, such as voltage regulator, resonant clocking, filter, etc. On the other hand, conventional on-chip 2D spiral inductor must be placed on the top metal layers, thereby consuming significant routing resources for global interconnects. Moreover, it may need more dedicated shielding to prevent unnecessary coupling, which further increases its occupied area. With the popularity of 2.5D and 3D chip architecture, Through-Silicon-Via (TSV) has been widely used, a significant portion of which are placed for thermal/manufacturability/reliability purposes. Thus, those redundant TSVs can be utilized to form the on-chip inductor for 2.5D/3D chips, with lower footprint and higher inductance density compared from the conventional spiral inductor. Unlike prior works focusing on the inductor itself, this paper discusses the optimization and application of such TSV-inductor from system perspective, including the optimization options and its design considerations. The possible design options including physical parameters, architecture and materials, to optimize the TSV-inductor are thoroughly investigated. Based on that, we further study a few key design scenarios to evaluate the design impact with use of such TSV-inductor and provide the design guidelines for its application in actual system designs.     

短距离通信中的塑料光纤无源器件技术

阐述了塑料光纤的真正优势在于其器件和连接的低价与便捷.着重介绍应用在短距离通信中的塑料光纤无源器件的研究进展,包括塑料光纤连接器、耦合器、塑料光纤放大器、塑料光纤光栅等.分析比较各种器件的技术特点,并指出今后面临的问题与挑战.     

Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-/spl mu/m RFCMOS technology, experimental results in this paper reveal that inductors' core diameters must be adequately large, more than 100 /spl mu/m, to ensure high quality factor characteristics and their conductor spacing should be minimal to obtain larger per unit area inductance value. A novel design methodology which optimizes the conductor width of inductors allows alignment of their peak quality factor to the circuit's operating frequency, enhancing the gain, input/output matching characteristics and noise figure of a giga-hertz amplifier.     

A toroidal inductor integrated in a standard CMOS process

This paper presents a toroidal inductor integrated in a standard 0.13 μm CMOS process. Finite-elements preliminary simulations are provided to prove the validity of the concept. In order to extract fundamental parameters by means of direct calculations, two different and well-known approaches are followed and the results are compared; this comparison provides useful guidelines for the design of the device. A very simple Π model for low frequencies is derived from 1-port and 2-port measurements, and a good matching with general theory is observed. The coil exhibits an inductance between 0.9 nH and 1.1 nH up to 20 GHz (physical limit for the measurement equipment) and a quality factor approaching 10 at 15 GHz. No self-resonance is observed within the measurement range.     

Equivalent circuit of microstrip spiral inductor circuit generation by computer

A method of equivalent circuit generation by computer is illustrated using a microstrip spiral inductor as an example. The computer program modifies the circuit topology, adding nodes and components as necessary. Results are compared with a model derived from physical considerations and show a great improvement in performance for a small increase in complexity.     

RF integrated inductor modeling and its application to optimization-based design

In this paper an optimization-based approach for the design of RF integrated inductors is addressed. For the characterisation of the inductor behaviour the double ??-model is used. The use of this model is twofold. On one hand it enables the generation of the inductor characterisation in a few seconds. On the other hand its integration into the optimization procedure is straightforward. For the evaluation of the model element values analytical expressions based on technology parameters as well as on the device geometric characteristics are used. The use of a technology-based methodology for the evaluation of the model parameters grants the adaptability of the model to any technology. The inductor analytical characterization is integrated into an optimization-based tool for the automatic design of RF integrated inductors. This tool uses a modified genetic algorithm (MGA) optimization procedure, which has proved its validation in previous work. Due to the design parameter constraints nature as well as the topology constraints, discrete variables optimization techniques are used. The accuracy of the results is checked against a non-commercial software.     

A new integrated SOI power device based on self-isolation technology

A new SOI LDMOS structure with buried n-islands(BNIs) on the top interface of the buried oxide(BOX) is presented in a p-SOI high voltage integrated circuits(p-SOI HVICs),which exhibits good self-isolation performance between the power device and low-voltage control circuits.Furthermore,both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μm,but also modulate the lateral electric field distribution,resulting in an improvemen...     

基于自隔离技术的可集成SOI高压功率器件新结构

SOI功率器件的高耐压和高、低压间良好的隔离效果是SOI高压功率集成电路（SOI HVIC）的两项关键技术。本文提出在埋氧层（buried oxide layer,BOX）上表面处埋N岛 (buried n-islands,BNI) 的SOI LDMOS高压功率器件新结构,该结构采用自隔离技术使SOI HPIC中高压功率器件与低压控制电路单元之间达到理想的隔离效果。此外,N岛中的施主离子和位于耗尽N岛间的空穴使BOX层的电场强度从32V/μm增加到113V/μm,同时对漂移区表面电场分布进行调制,最终使器件击穿电压（BV）显著提高。实验测得一个BNI SOI LDMOS样品的耐压为673V,并在SOI HVPIC中表现出良好的隔离特性。