Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects

Inductive coupling is becoming a design concern for global interconnects in nanometer technologies. We present measurement results of the effect of inductive coupling on timing, and demonstrate that inductive coupling noise is a practical design issue in 90 nm technology. The measured delay change curve is consistent with circuit simulation results for an RLC interconnect model, and clearly different from those for a conventional RC model. The long-range coupling effect of inductive coupling, and noise reduction caused by ground insertion or decreased driver size were clearly observed on silicon. Examination of noise cancellation and superposition effects shown in measurement results confirm that the summation of delay variations due to each individual aggressor is a reasonable approximation of the total delay variation.     

Characterisations of absolute phase noise in fibre-laser modelocked by sapphire-loaded cavity resonator oscillator at 10 GHz

Results from characterisations of the absolute phase noise in a fibre laser modelocked, at 10.24 GHz, by a sapphire-loaded cavity resonator oscillator, are reported. From the phase noise measured, an absolute timing jitter of /spl sim/2.48 and /spl sim/14.3 fs, respectively, for frequency-offset (/spl Delta/f) ranges that spanned /spl Delta/f=100 Hz to 1 MHz, and /spl Delta/f=100 Hz to 40 MHz, were estimated.     

On the impact of on-chip inductance on signal nets under the influence of power grid noise

It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and cannot be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultradeep submicron technologies under the influence of power grid noise. The analysis is based on an Al-based 0.18-/spl mu/m CMOS process and a Cu-based 0.13-/spl mu/m CMOS process. The impact of on-chip inductance is shown to be insignificant if we assume a perfect power supply network around the interconnect routes. Otherwise, the impact of on-chip inductance can be significant. Furthermore, the results presented in this paper illustrate the impact of on-chip inductance one would expect from transitioning from an Al-based interconnect technology to a Cu-based interconnect technology. A heuristic method is proposed in the paper to account for the inductive coupling due to power grid noise in signal delay modeling and simulations.     

High responsivity InP-InGaAs quantum-well infrared photodetectors: characteristics and focal plane array performance

We report the detailed characteristics of long-wavelength infrared InP-In/sub 0.53/Ga/sub 0.47/As quantum-well infrared photodetectors (QWIPs) and 640/spl times/512 focal plane array (FPA) grown by molecular beam epitaxy. For reliable assessment of the detector performance, characterization was performed on test detectors of the same size and structure with the FPA pixels. Al/sub 0.27/Ga/sub 0.73/As-GaAs QWIPs with similar spectral response (/spl lambda//sub p/=/spl sim/7.8 /spl mu/m) were also fabricated and characterized for comparison. InP-InGaAs QWIPs (20-period) yielded quantum efficiency-gain product as high as 0.46 under -3-V bias with a 77-K peak detectivity above 1/spl times/10/sup 10/ cm/spl middot/Hz/sup 1/2//W. At 70 K, the detector performance is background limited with f/2 aperture up to /spl sim/ 3-V bias where the peak responsivity (2.9 A/W) is an order of magnitude higher than that of the AlGaAs-GaAs QWIP. The results show that impact ionization in similar InP-InGaAs QWIPs does not start until the average electric-field reaches /spl sim/25 kV/cm, and the detectivity remains high under moderately large bias, which yields high responsivity due to large photoconductive gain. The InP-InGaAs QWIP FPA offers reasonably low noise equivalent temperature difference (NETD) even with very short integration times (/spl tau/).70 K NETD values of the FPA with f/1.5 optics are 36 and 64 mK under bias voltages of -0.5 V (/spl tau/=11 ms) and -2 V (/spl tau/=650 /spl mu/s), respectively. The results clearly show the potential of InP-InGaAs QWIPs for thermal imaging applications requiring high responsivity and short integration times.     

Current-source a-Si:H thin-film transistor circuit for active-matrix organic light-emitting displays

In this letter, we describe a four thin-film-transistor (TFT) circuit based on hydrogenated amorphous silicon (a-Si:H) technology. This circuit can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The experimental results indicated that, for TFT threshold voltage shift as large as /spl sim/3 V, the output current variations can be less than 1 and 5% for high (/spl ges/0.5 /spl mu/A) and low (/spl les/0.1 /spl mu/A) current levels, respectively. This circuit can potentially be used for the active-matrix organic light-emitting displays (AM-OLEDs).     

DSM interconnects: importance of inductance effects and corresponding range of length

To analyze at which rise/fall times the inductance effect appears in DSM interconnects, the author develops a methodology versus the input line transition time to be technology-independent. These lines are modeled as RC and RLC distributed lines, and the two models are compared to define the effects caused by neglecting inductance. The goal of this study is, based upon the discrepancy between RC and RLC models, to define when inductance must be included in the modeling of interconnects. A simple rule permits the choice of the simplest model (RC or RLC) for a given accuracy. The length range concerned by the inductive effect is calculated from the complex propagation factor value. The theoretical limits are illustrated on several interconnection configurations, on a 0.18-/spl mu/m technology.     

Evidence of crossover phenomena in wind-speed data

In this paper, a systematic analysis of hourly wind-speed data obtained from three potential wind-generation sites (in North Dakota) is analyzed. The power spectra of the data exhibited a power-law decay characteristic of 1/f/sup /spl alpha// processes with possible long-range correlations. Conventional analysis using Hurst exponent estimators proved to be inconclusive. Subsequent analysis using detrended fluctuation analysis revealed a crossover in the scaling exponent (/spl alpha/). At short time scales, a scaling exponent of /spl alpha//spl sim/1.4 indicated that the data resembled Brownian noise, whereas for larger time scales the data exhibited long-range correlations (/spl alpha//spl sim/0.7). The scaling exponents obtained were similar across the three locations. Our findings suggest the possibility of multiple scaling exponents characteristic of multifractal signals.     

Circuit for monitoring BJT RF performance using DC measurements

A test circuit is described for on-wafer monitoring of high-frequency performance of bipolar junction transistors using only dc measurements. The test circuit includes an oscillation-amplitude detector and a high-frequency (/spl sim/3 GHz) oscillator whose minimum bias current for oscillation I/sub osc/ correlates strongly with the transistors' maximum oscillation frequency f/sub max/. Variations in the circuit's I/sub osc/ can be routinely monitored to track changes in f/sub max/ caused by process variations. Monte Carlo simulations showed a correlation coefficient of -0.79 between I/sub osc/ and f/sub max/. Variations in measured f/sub max/ intentionally introduced through layout variations were verified to be strongly correlated with I/sub osc/.     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

The impact of uniform strain applied via bonding onto plastic substrate on MOSFET performance

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (/spl sim/0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average /spl Delta/I/sub d//I/sub d//spl sim/10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (L/sub g//spl sim/55 nm -0.530 /spl mu/m/W /spl sim/2-20 /spl mu/m). The p-MOSFETs also exhibited I/sub d/-improvement by /spl sim/7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects.     

Characterization of the jitter in a mode-locked Er-fiber laser and its application in photonic sampling for analog-to-digital conversion at 10 gsample/s

This paper compares two approaches for evaluating the amplitude and timing jitters of an Er-fiber laser mode-locked at 10 GHz. Using a low-noise oscillator as the clock drive for the mode-locking, relative amplitude jitter was measured as low as 0.0384% and timing jitter as low as 0.0153% (/spl Delta/f=100 Hz-40 MHz). Applying the mode-locked pulse train in a photonic sampling experiment at 10 Gsample/s, a spurious free dynamic range (SFDR) of /spl sim/48.5 dB (over the Nyquist bandwidth of 5 GHz) for multiple analog inputs at L band (1-2.6 GHz). These results correspond to an analog-to-digital conversion resolution of /spl sim/8 SFDR bits at 10 Gsample/s. Finally, the use of "instantaneous companding" is demonstrated to correct for third-order distortions generated by a Mach-Zehnder modulator used in the photonic sampling link.     

Optical and electrical properties of nanostructured metal-silicon-metal photodetectors

We report an experimental evaluation of the performance of silicon (Si) photodetectors incorporating one-dimensional (1-D) arrays of rectangular and triangular-shaped nanoscale structures within their active regions. A significant (/spl sim/2/spl times/) enhancement in photoresponse is achieved in these devices across the 400- to 900-nm spectral region due to the modification of optical absorption properties that results from structuring the Si surface on physical optics scales smaller than the wavelength, which both reduces the reflectivity and concentrates the optical field closer to the surface. Both patterned (triangular and rectangular lineshape) and planar Ni-Si back-to-back Schottky barrier metal-semiconductor-metal photodetectors on n-type (/spl sim/5/spl times/10/sup 14/ cm/sup -3/) bulk Si were studied. 1-D /spl sim/50-250-nm linewidth, /spl sim/1000-nm depth, grating structures were fabricated by a combination of interferometric lithography and dry etching. The nanoscale grating structures significantly modify the absorption, reflectance, and transmission characteristics of the semiconductor: air interface. These changes result in improved electrical response leading to increased external quantum efficiency (from /spl sim/44% for planar to /spl sim/81% for structured devices at /spl lambda/=700 nm). In addition, a faster time constant (/spl sim/1700 ps for planar to /spl sim/600 ps for structured at /spl lambda/=900 nm) is achieved by increasing the absorption near the surface where the carriers can be rapidly collected. Experimental quantum efficiency and photocurrents results are compared with a theoretical photocurrent model based on rigorous coupled-wave analysis of nanostructured gratings.     

Diamond FET using high-quality polycrystalline diamond with f/sub T/ of 45 GHz and f/sub max/ of 120 GHz

Using high-quality polycrystalline chemical-vapor-deposited diamond films with large grains (/spl sim/100 /spl mu/m), field effect transistors (FETs) with gate lengths of 0.1 /spl mu/m were fabricated. From the RF characteristics, the maximum transition frequency f/sub T/ and the maximum frequency of oscillation f/sub max/ were /spl sim/ 45 and /spl sim/ 120 GHz, respectively. The f/sub T/ and f/sub max/ values are much higher than the highest values for single-crystalline diamond FETs. The dc characteristics of the FET showed a drain-current density I/sub DS/ of 550 mA/mm at gate-source voltage V/sub GS/ of -3.5 V and a maximum transconductance g/sub m/ of 143 mS/mm at drain voltage V/sub DS/ of -8 V. These results indicate that the high-quality polycrystalline diamond film, whose maximum size is 4 in at present, is a most promising substrate for diamond electronic devices.     

Spatial distribution of the gain and temperature across the flow in a slit-nozzle supersonic chemical oxygen-iodine laser with transonic and supersonic schemes of iodine injection

Spatial distributions of the gain and temperature across the flow were studied for transonic and supersonic schemes of the iodine injection in a slit-nozzle supersonic chemical oxygen-iodine laser as a function of the iodine and secondary nitrogen flow rate, jet penetration parameter, and gas pumping rate. The mixing efficiency for supersonic injection of iodine (/spl sim/0.85) is much larger than for transonic injection (/spl sim/0.5), the maximum values of the gain being /spl sim/0.65%/cm for both injection schemes. Measurements of the gain distribution as a function of the iodine molar flow rate nI/sub 2/ were carried out. For transonic injection, the optimal value of nI/sub 2/ at the now centerline is smaller than that at off axis locations. The temperature is distributed homogeneously across the flow, increasing only in the narrow boundary layers near the walls. Opening a leak downstream of the cavity in order to decrease the Mach number results in a much larger mixing efficiency (/spl sim/0.8) than for a closed leak.     

A 250-MHz BiCMOS receiver channel with leading edge timing discriminator for a pulsed time-of-flight laser rangefinder

An integrated receiver channel of a pulsed time-of-flight (TOF) laser rangefinder for fast industrial measurement applications with the measurement accuracy of a few centimeters in the measurement range from /spl sim/1 m to /spl sim/30 m to noncooperative targets was developed. The receiver channel consists of a fully differential transimpedance amplifier channel, a peak detector, an rms meter and a timing discriminator. In this particular application there is no time to measure the received signal strength beforehand and it is not predictable from previous measurements, so a leading edge timing discriminator with a constant threshold voltage was used. The amplitude of the received pulse is measured with a peak detector and the amplitude information is used to compensate for the resulting walk error. The measured bandwidth of the receiver channel is 250 MHz, the maximum transimpedance 40k/spl Omega/ and the input-referred noise /spl sim/7pA//spl radic/Hz (C/sub photodiode/=2 pF). The timing detection accuracy of the receiver is better than /spl plusmn/35 mm in a single-shot measurement in a dynamic range of 1:4000 and a temperature range of 0/spl deg/C to +50/spl deg/C.     

Millimeter-wave voltage-controlled oscillators in 0.13-/spl mu/m CMOS technology

This paper describes the design of CMOS millimeter-wave voltage controlled oscillators. Varactor, transistor, and inductor designs are optimized to reduce the parasitic capacitances. An investigation of tradeoff between quality factor and tuning range for MOS varactors at 24 GHz has shown that the polysilicon gate lengths between 0.18 and 0.24 /spl mu/m result both good quality factor (>12) and C/sub max//C/sub min/ ratio (/spl sim/3) in the 0.13-/spl mu/m CMOS process used for the study. The components were utilized to realize a VCO operating around 60 GHz with a tuning range of 5.8 GHz. A 99-GHz VCO with a tuning range of 2.5 GHz, phase noise of -102.7 dBc/Hz at 10-MHz offset and power consumption of 7-15mW from a 1.5-V supply and a 105-GHz VCO are also demonstrated. This is the CMOS circuit with the highest fundamental operating frequency. The lumped element approach can be used even for VCOs operating near 100-GHz and it results a smaller circuit area.     

640 /spl times/ 512 pixel long-wavelength infrared narrowband, multiband, and broadband QWIP focal plane arrays

A 640 /spl times/ 512 pixel, long-wavelength cutoff, narrowband (/spl Delta//spl lambda///spl lambda//spl sim/10%) quantum-well infrared photodetector (QWIP) focal plane array (FPA), a four-band QWIP FPA in the 4-15 /spl mu/m spectral region, and a broadband (/spl Delta//spl lambda///spl lambda/ /spl sim/ 42%) QWIP FPA having a 15.4 /spl mu/m cutoff have been demonstrated. In this paper, we discuss the electrical and optical characterization of these FPAs, and their performance. In addition, we discuss the development of a very sensitive (NEDT /spl sim/ 10.6 mK) 640 /spl times/ 512 pixel thermal imaging camera having a 9 /spl mu/m cutoff.     

Variable numerical-aperture temporal-coherence measurement of resonant-cavity LEDs

The first interferometric measurements of temporal-coherence length variation with numerical aperture (NA) are described for 650 nm, resonant-cavity light-emitting diodes (LEDs) agreeing with spectrally derived results. The interferometrically measured coherence length (22 /spl mu/m to 32 /spl mu/m) reduced by 37% for a 0.42 increase in NA. For a larger range of NA (0-1), this would give coherence lengths (10 /spl mu/m-40 /spl mu/m) lying in the gap between that of conventional LEDs (/spl sim/5 /spl mu/m) and superluminescent diodes (/spl sim/60 /spl mu/m).     

Integrated high-/spl kappa/ (/spl kappa/ /spl sim/19) MIM capacitor with Cu/low-/spl kappa/ interconnects for RF application

We demonstrate a high-performance metal-high /spl kappa/ insulator-metal (MIM) capacitor integrated with a Cu/low-/spl kappa/ backend interconnection. The high-/spl kappa/ used was laminated HfO/sub 2/-Al/sub 2/O/sub 3/ with effective /spl kappa/ /spl sim/19 and the low-/spl kappa/ dielectric used was Black Diamond with /spl kappa/ /spl sim/2.9. The MIM capacitor (/spl sim/13.4 fF//spl mu/m/sup 2/) achieved a Q-factor /spl sim/53 at 2.5 GHz and 11.7 pF. The resonant frequency f/sub r/ was 21% higher in comparison to an equivalently integrated Si/sub 3/N/sub 4/-MIM capacitor (/spl sim/0.93 fF//spl mu/m/sup 2/) having similar capacitance 11.2 pF. The impacts of high-/spl kappa/ insulator and low-/spl kappa/ interconnect dielectric on the mechanism for resonant frequency improvement are distinguished using equivalent circuit analysis. This letter suggests that integrated high-/spl kappa/ MIM could be a promising alternative capacitor structure for future high-performance RF applications.     

Sensitivity of double-gate and FinFETDevices to process variations

We investigate the manufacturability of 20-nm double-gate and FinFET devices in integrated circuits by projecting process tolerances. Two important factors affecting the sensitivity of device electrical parameters to physical variations were quantitatively considered. The quantum effect was computed using the density gradient method and the sensitivity of threshold voltage to random dopant fluctuation was studied by Monte Carlo simulation. Our results show the 3/spl sigma/ value of V/sub T/ variation caused by discrete impurity fluctuation can be greater than 100%. Thus, engineering the work function of gate materials and maintaining a nearly intrinsic channel is more desirable. Based on a design with an intrinsic channel and ideal gate work function, we analyzed the sensitivity of device electrical parameters to several important physical fluctuations such as the variations in gate length, body thickness, and gate dielectric thickness. We found that quantum effects have great impact on the performance of devices. As a result, the device electrical behavior is sensitive to small variations of body thickness. The effect dominates over the effects produced by other physical fluctuations. To achieve a relative variation of electrical parameters comparable to present practice in industry, we face a challenge of fin width control (less than /spl sim/1 nm 3/spl sigma/ value of variation) for the 20-nm FinFET devices. The constraint of the gate length variation is about 10/spl sim/15%. We estimate a tolerance of 1/spl sim/2 /spl Aring/ 3/spl sigma/ value of oxide thickness variation and up to 30% front-back oxide thickness mismatch.