Fast statistical delay evaluation of RC interconnect in the presence of process variations

Fast statistical methods of interconnect delay and slew in the presence of process fluctuations are proposed. Using an optimized quadratic model to describe the effects of process variations, the proposed method enables closed-form expressions of interconnect delay and slew for the given variations in relevant process parameters. Simulation results show that the method, which has a statistical characteristic similar to traditional methodology, is more efficient compared to HSPICE-based Monte Carlo simulations and traditional methodology.     

考虑工艺波动的快速RC互连延时统计计算

本文提出了一种考虑工艺波动影响的计算延时和过渡时间的快速统计模型。模型中使用优化的二阶模型描述工艺波动的影响,使用了闭合表达式来表示相关工艺参数和工艺波动影响下的延时和过渡时间之间的关系。仿真实验表明：提出的模型和传统算法有相似的精度和相似的统计特性,而计算效率大大高于基于HSPICE的模特卡罗分析和传统方法。     

工艺变化下互连线分布参数随机建模与延迟分析

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证.     

考虑工艺波动的RLC互连延时统计模型

基于概率解释算法的原理,提出了一种考虑工艺波动的RLC互连延时统计模型,该模型使用了对数正态分布函数。在给定互连参数波动范围条件下,利用该算法计算延时仅需要采用前两个瞬态。和HSPICE相比,Monte Carlo分析中的均值和平均偏差误差分别低于0.7％和0.51％。模型计算简单且精度高,可以满足互连线仿真要求。     

Materials' impact on interconnect process technology and reliability

We explain how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper, as the metal of choice at the 130-nm technology node, mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of the interconnect system. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing pose serious challenges to the implementation of such materials in high-volume manufacturing. We consider the cases of two ILD materials, carbon-doped silicon dioxide and low-k spin-on-polymer, to illustrate the impact of the ILD choice on the process technology and reliability of copper interconnects.     

考虑工艺波动的互连串扰的峰值统计模型

随着集成电路特征尺寸的不断减小,互连线的串扰噪声对工艺波动的灵敏度也在相应增加。通过分析互连几何参数波动对互连寄生参数的影响,得到其近似的函数关系表达式,在此基础上建立了考虑工艺波动的串扰噪声的统计模型。利用该模型可以得到互连串扰噪声均值和标准差的解析表达式。计算结果表明：和HSPICE相比,该方法在确保计算精度的前提下大大缩短了计算时间,在超大规模集成电路互连信号完整性的分析和优化中具有一定的应用前景。     

90nm工艺及其相关技术

ITRS2001规划2004年实现90nm工艺,英特尔、AMD等世界顶级半导体公司将于2003年采用90nm工艺量产微处理器和逻辑器件。这样使ITRS2001整整提前了一年。90nm工艺包括193nm光刻技术、高k绝缘材料、高速多层铜互连技术、低k绝缘材料、应变硅技术和电压隔离技术等新技术。193nm光刻技术是实现90nm工艺达量产的最关键技术,为此,必须采用193nmArFstepper(准分子激光扫描分步投影光刻机)。讨论了90nm工艺达量产的难点,如掩模版成本较高、成品率较低和应用面暂时不宽等。     

VLSI中互连线工艺变化的若干问题研究进展

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,互连线的工艺变化已成为影响集成电路性能的重要因素.针对该问题,结合作者的研究工作,综述了目前国内外互连线工艺变化若干关键问题的研究进展情况,重点介绍工艺变化条件下互连线寄生电参数及其传输性能的研究方法,并分析不同技术的特点和局限性.最后展望了互连线工艺变化问题今后的研究发展方向.     

一种基于概率解释的新型互连线时延Slew模型

基于概率解释的互连线时延模型具有效率高,实现简单,估计准确等特点,在亚100纳米工艺IC设计及验证中具有较好的应用前景.基于概率解释的互连线时延模型往往需要大量的查表计算,对效率及计算精度都存在一定的影响,而且有些模型不能进行Slew的估计.本文提出了一种基于BS统计分布的互连线时延模型,完全避免了查表运算而且可直接用于Slew估计.90纳米工艺TCAD仿真实验结果表明,该模型在效率、精度、实现难易程度等方面具有一定的优势,对亚100纳米VLSI静态时序分析及相关EDA工具开发也有一定的参考价值.     

Small-delay defect detection in the presence of process variations

Interconnect-based defects such as partial opens are becoming more prevalent in nanoscale designs. These are latent defects that affect circuit reliability and can be modeled as small-delay defects. Detecting such defects therefore requires faster than at-speed test clocks. In the paper we analyze the uncertainty introduced by process variations in detecting these defects. We propose new path selection algorithms that increase the probability of defect detection by taking into account the variability in path delays. Our results show that the new technique detects much smaller defects than the traditional approach of selecting the longest paths for test.     

Material and process challenges in 100 nm interconnects module technology and beyond

In order for ultra-large-integrated (ULSI) circuits manufacturing to minimize the Cost of Ownership (CoO) aspect in the wiring process and realize fabricating semiconductor devices over 100 nm node, several Cu/low-k wiring technologies have been proposed. The evidential criteria in choosing the most probable one are physical or material limitation and requirements from manufacturing. A development of module processes (e.g., processing from low-k dielectrics to metal CMP) with proven equipment and material is an appropriate approach and has a high potential in overcoming those difficulties. In this paper, an advantage of dual Damascene Cu wiring accompanied with low-k (dielectric constant ∼2.7) and prediction of 100 nm Cu wiring module will be discussed.     

基于TCAD的90nm STI应力仿真与研究

研究了90 nm CMOS工艺下浅槽隔离技术产生的x轴应力对NMOSFET电学性能的影响.用新一代集成工艺仿真软件Sentaurus TCAD对不同有源区宽度(Sa=0.4 μm～3.2 μm,间隔0.4 μm)的90 nm沟长NMOSFET进行了仿真并和测量数据进行了对比.随着有源区宽度从3.2 μm减小到0.4 μm,NMOSFET的饱和电流减小了7%,但其阈值电压增大了8%.这说明有源区宽度的减小使得STI应力增大,进一步减小了NMOSFET中电子迁移率和沟道中halo注入浓度的扩散,使得饱和电流退化,阈值电压增加.     

Characterization and impact of reduced copper plating overburden on 45 nm interconnect performances

During first metal level interconnects fabrication, a controlled modification of the electro-deposited copper over-deposition (overburden) is performed using a partial chemical-mechanical polishing (CMP) step. Next, copper microstructure is stabilized with a short duration hot-plate anneal. Overburden is then removed during CMP end-of-step. Ionic microscopy and EBSD observations of overburden thickness reduction reveal that copper grain growth occurs differently, according to patterned geometries and with a strong 〈1 1 1〉 texture, as observed in modified films. Reduction of overburden thickness also reveals the capacity of anneal temperature to impact electrical performances. Reliability is impacted for thinnest wires.     

Analysis of the impact of process variations on clock skew

In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as V_T and I_DSS, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network     

VLSI随机工艺变化下互连线建模与延迟分析

目前互连线的工艺变化问题已成为影响超大规模集成电路性能的重要因素.考虑了互连线工艺变化的空间相关性,将工艺参数变化建模为具有自相关性的随机过程,采用数值仿真及拟合方法得到寄生参数的近似表达式,最后基于Elmore延迟度量分析了随机工艺变化对互连延迟的影响,提出了工艺变化下互连延迟统计特性的估算方法,并通过仿真实验对方法的有效性进行了验证.     

基于90 nm InP HEMT工艺的220 GHz功率放大器设计

基于90 nm InP HEMT工艺,设计了一款220 GHz功率放大器太赫兹单片集成电路,该放大器采用片上威尔金森功分器结构实现了两路五级共源放大器的功率合成。在片测试结果表明,200~230 GHz频率范围内,功率放大器小信号增益平均值18 dB。频率为210~230 GHz范围内该MMIC放大器饱和输出功率优于15.8 mW,在223 GHz时最高输出功率达到20.9 mW,放大器芯片尺寸为2.18 mm×2.40 mm。     

A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.     

Low VDD and body bias conditions for testing bridge defects in the presence of process variations

Bridge defects are an important manufacturing defect that may escape test causing reliability issues. It has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods lowering test quality. Therefore, advances in test methodologies to enhance bridge detection are required. In this work a Statistical Timing Analysis Framework (STAF) is used to compute the probability of detection of bridge defects for different V_DD and RBB values. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage (SFC). The STAF allows to capture properly the behavior of the mean and a standard circuit delay when V_DD and RBB change. Furthermore, the STAF uses a realistic bridge defect model suitable to consider appropriately the impact of V_DD and RBB on delay increase. This methodology is applied to some ISCAS benchmark circuits implemented in a commercial 65 nm CMOS technology. The obtained results of several ISCAS benchmark circuits show clearly that the Statistical Fault Coverage (SFC) increases significantly when V_DD is lowered, and increases even more when RBB is applied at Low V_DD. The test conditions to improve resistive bridge detection combining Low V_DD and Reverse Body Bias (RBB) under a delay based test are determined. It is shown that the impact of RBB on bridge detection improves significantly for a sufficient low value of V_DD. The values of Low V_DD and RBB can be selected considering the tradeoff between fault coverage and test time penalization.     

Pipelined H-trees for high-speed clocking of large integratedsystems in presence of process variations

This paper addresses the problem of clocking large high-speed digital systems, as well as deterministic skew modeling, a related problem. In order to provide a reliable skew model, and to avoid the frequency limitation, we propose a novel approach that distributes the clock with an H-tree, whose branches are composed of minimum-sized inverters rather than metal. With such a structure, we obtain the highest clocking rate achievable with a given technology. Indeed, clock rates around 1 GHz are possible with a 1.2 μm CMOS technology. From the skew modeling standpoint, we derive an analytic expression of the skew between two leaves of the H-tree, which we consider to be the difference in root-to-leaf delay pairs. The skew upper bound obtained has an order of complexity which, with respect to the H-tree size D, is the same as the one that may be derived from the Fisher and Kung model for both side-to-side and neighbor-to-neighbor communications, i.e., a Ω(D²), whereas, the Steiglitz and Kugelmass probabilistic model predicts Θ(D×√LogD). In an H-tree implemented with metallic lines, the leaf-to-leaf skew is obviously bounded by the delay between the root and the leaves. However, with the logic based H-tree proposed here, we arrive at a nonobvious result, which states that the leaf-to-leaf skew grows faster than the root-to-leaf delay in presence of a uniform transistor time constant gradient. This paper also proposes generalizations of the skew model to (1) the case of chips in a wafer subject to a smooth, but nonuniform gradient and (2) the case of H-tree configurations mixing logic and interconnections; in this respect, this paper covers the H-tree configurations based on the combination of logic and interconnections