High-field-induced leakage in ultrathin N2O oxides

Stress-induced leakage current (SILC) is studied in ultrathin (~50 Å) gate oxides grown in N₂O or O₂ ambient, using rapid thermal processing (N₂O oxide or control oxide, respectively). MOS capacitors with N₂O oxides exhibit much suppressed SILC compared to the control oxide for successive ramp-up, constant voltage DC, and AC (bipolar and unipolar) stresses. The mechanism for SILC is discussed, and the suppressed SILC in N₂O oxide is attributed to suppressed interface state generation due to nitrogen incorporation at the Si/SUO₂ interface during N₂O oxidation     

Explanation of SILC Probability Density Distributions With Nonuniform Generation of Traps in the Tunnel Oxide of Flash Memory Arrays

In this paper, we develop a detailed physical model to interpret the dependence of the stress induced leakage current (SILC) distributions on the nature and position of the generated defects, and we exploit it to reconsider in detail previously published experimental data on the statistical distribution of the SILC in Flash arrays. We found that a unique symmetrical spatial distribution of traps, which is rapidly decreasing from the Si-SiO₂ interfaces toward the center of the oxide, can explain the oxide-thickness and stress-level dependence of the measured SILC distributions. The generation of cooperating defects with increasing stress time is also analyzed and discussed.     

超薄栅MOS器件热载流子应力下SILC的产生机制

通过测量界面陷阱的产生,研究了超薄栅nMOS和pMOS器件在热载流子应力下的应力感应漏电流(SILC).在实验结果的基础上,发现对于不同器件类型(n沟和p沟)、不同沟道长度(1、0.5、0.275和0.135μm)、不同栅氧化层厚度(4和2.5nm),热载流子应力后的SILC产生和界面陷阱产生之间均存在线性关系.这些实验证据表明MOS器件减薄后,SILC的产生与界面陷阱关系非常密切.     

Body effect induced wear-out acceleration in ultra-thin oxides

In this study, body effect influence on oxide degradation is analyzed. It is found that the negative bias polarization on the n-well of a p-channel MOS transistor may induce a significant reduction of the oxide lifetime as well as an increase of stress-induced leakage current (SILC). Such a result is demonstrated to confirm the key role of hot holes on SILC and breakdown phenomena. Moreover, even if the hot hole generated at the anode are probably at the origin of SILC and can be interpreted as a catalyst of breakdown, it is undoubtedly shown that both phenomena are not directly correlated: SILC at breakdown can not be ascribed to a critical density of defect at failure.     

Modeling of SILC based on electron and hole tunneling. I. Transienteffects

A detailed investigation of the steady-state and transient leakage currents in thin oxides is proposed. The experimental data are compared with numerical results obtained from a model based on an inelastic trap-assisted tunneling process, which includes both electron and hole contributions. In order to accurately reproduce the transient discharge currents, a continuous distribution of oxide traps was adopted. The energies of these levels can be either in correspondence of the conduction or valence band edges of the adjacent silicon/polysilicon layers. Both electrons and holes contribute to the transient stress-induced leakage current (SILC), but the extracted trap densities cannot account for the steady-state SILC. A different mechanism, involving trap levels with energy aligned to the energy gap of the silicon layers is proposed and is developed in the following paper. The model can be applied to any type of device and bias conditions and may be used to correctly recognize the role of electron and hole SILC and the spatial and energy distribution of defect states     

Electrically and radiation induced leakage currents in thin oxides

Stress Induced Leakage Current (SILC) has been recognized as a topic of concern in flash memory reliability. It is a veritable failure mechanism, occurring long before oxide breakdown and, hence, limiting oxide lifetime. The physical origin and mechanisms of SILC have not yet been clearly understood and several open points to discussion remain. In this work the electrical characteristics of SILC have been studied and an empirical reliability model for ultra-thin gate oxide has been proposed. Moreover, ionizing radiation effects in leakage current generation have been analyzed and compared to electrical SILC.     

A statistical model for SILC in flash memories

The reliability of flash memories is strongly. limited by the stress-induced leakage current (SILC), which leads to accelerated charge-loss phenomena in a few anomalous cells. Estimating the reliability of large flash arrays requires that physically-based models for the statistical distribution of SILC are developed. In this paper, we show a physical model for the leakage mechanism in thin oxides, which is able us to explain the anomalous leakage-conduction in tail cells. The physical model is then used for a quantitative evaluation of the SILC distribution in large flash arrays. The new model can reproduce the statistics of SILC for a wide range of tunnel-oxide thickness, and can provide a straightforward estimation of the reliability for large flash arrays.     

SILC as a measure of trap generation and predictor ofTBD in ultrathin oxides

The theoretical basis of stress-induced leakage current (SILC) as a measure of bulk trap density within thin oxide films is explored. Contrary to popular belief, this measure is neither absolute, nor do most papers in the literature sufficiently specify the measurement conditions to make their comparison meaningful. We also explore the relationship between SILC generation rate and the time-to-breakdown, and show that only a very specific definition of SILC generation can capture the voltage dependence of the time-to-breakdown     

Role of positive trapped charge in stress-induced leakage current for flash EEPROM devices

The transient behavior of hot hole (HH) stress-induced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge-assisted tunneling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. A correlation between SILC and stress-induced substrate current is observed. Our study shows that both SILC and stress-induced substrate current have power law time-dependence t/sup -n/ with the power factor n about 0.7 and 1, respectively. Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time- and field-dependence of SILC and the substrate current. Based on our model, the evolution of threshold voltage shift with read-disturb time in a flash EEPROM cell is derived. Finally, the dependence of SILC on oxide thickness is explored. As oxide thickness reduces from 100 /spl Aring/ to 53 /spl Aring/, the dominant SILC mechanism is found to change from PCAT to neutral trap-assisted tunneling (TAT).     

HfO_2高k栅介质漏电流机制和SILC效应

利用室温下反应磁控溅射的方法在 p- Si(1 0 0 )衬底上制备了 Hf O2 栅介质层 ,研究了 Hf O2 高 k栅介质的电流传输机制和应力引起泄漏电流 (SIL C)效应 .对 Hf O2 栅介质泄漏电流输运机制的分析表明 ,在电子由衬底注入的情况下 ,泄漏电流主要由 Schottky发射机制引起 ,而在电子由栅注入的情况下 ,泄漏电流由 Schottky发射和 Frenkel-Poole发射两种机制共同引起 .通过对 SIL C的分析 ,在没有加应力前 Hf O2 / Si界面层存在较少的界面陷阱 ,而加上负的栅压应力后在界面处会产生新的界面陷阱 ,随着新产生界面陷阱的增多 ,这时在衬底注入的情况下 ,电流传     

Measurement and modeling of the annealing kinetics of stress induced leakage current in ultra-thin oxides

The annealing properties of the stress induced leakage current (SILC) for 55 and 65 Åthick oxides are investigated. It is demonstrated that the SILC is a fully reversible degradation process and that its generation kinetics are nearly unchanged after successive stressing/annealing cycles. The activation energy and diffusion coefficient of the annealing process has been extracted and shown to be independent of oxide thickness. Moreover the annealing kinetics are quantitatively simulated using a drift-diffusion model with the experimentally extracted parameters.     

On interface and oxide degradation in VLSI MOSFETs. I. Deuteriumeffect in CHE stress regime

This paper analyzes in detail the generation of interface states (N_it) and stress-induced leakage current (SILC) during channel hot electron (CHE) stress experiments in the context of a possible hydrogen/deuterium (H/D) isotope effect. Our results show that N_it generation is related to the hydrogen release (HR) at the Si-SiO₂ interface at relatively high V_G where a large isotope effect is found. Instead, for gate voltages (V_G) favorable for hot hole injection (HHI) the N_it creation becomes a unique function of hole fluence and the isotope effect disappears. In the studied stress conditions, we found no experimental evidence supporting a causal relation between SILC generation and HR because no isotope effect is observed even when the corresponding N_it measurements reveal a very different D/H release rate. Similar to N_it generation, we found that SILC becomes a unique function of hole fluence at low stress V_G. Relevant implications and extensions of these results to the Fowler-Nordheim (FN) tunneling stress conditions are discussed in Pt. II     

Degradation behavior of Ta2O5 stacks and its dependence on the gate electrode

Response of 8 nm Ta₂O₅ stacks with Al and Au gate electrodes to voltage stress at room temperature and at 100 °C is investigated. Stress-induced leakage current (SILC) reveals significant gate dependence and distinct difference to SILC in SiO₂. The mechanisms for SILC generation and stress degradation are discussed. Unlike SiO₂, pre-existing traps and positive charge build-up are recognized as a key factor for generation of SILC in Ta₂O₅ stacks.     

The impacts of SILC and hot carrier induced drain leakage current on the refresh time in DRAM

This paper reports the temperature dependence of SILC and hot carrier induced drain leakage current, and their impact on the refresh time in Giga-bit level DRAM with practical considerations. SILC has been found to increase as the monitoring and stress temperature increases. Due to the generation of interface states, hot carrier induced pn junction leakage current and band-to-band tunneling current have been found to increase as the monitoring temperature increases.From the simulation results of a refresh circuit for Giga-bit level DRAM, it has been found that the increase of SILC with stress time is a dominant factor in refresh failure below 373K, and the pn junction leakage current will be a dominant factor at the high elevated temperature. It has been also observed that the increase of hot carrier induced drain leakage current can be a cause for the refresh failure.     

Relation between defect generation, stress induced leakage current and soft breakdown in thin (<5 nm) oxides

The normalized stress induced leakage current (SILC) measured when the oxide is subjected to low level constant-current stresses shows a tendency towards saturation at large charge fluences. To investigate the origin of this saturation, the degradation of the oxide has been analyzed using two independent methods: SILC data analysis and a two-step stress test. The results show that, although under low stress currents the SILC saturation is observed, the degradation (i.e., the generation of defects) proceeds until the soft breakdown (SBD) event takes place. The implications for the use of SILC data as degradation monitor are analyzed.     

Impact of time dependent dielectric breakdown and stress-inducedleakage current on the reliability of high dielectric constant(Ba,Sr)TiO3 thin-film capacitors for Gbit-scale DRAMs

Time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) are investigated for the reliability of (Ba,Sr)TiO₃ (BST) thin films. Both time to breakdown (T_BD) versus electric field (E) and T_BD versus 1/E plots show universal straight lines, independent of the film thickness, and predict lifetimes longer than 10 y at +1 V for 50 nm BST films with an SiO₂ equivalent thickness of 0.70 nm. SILC is observed at +1 V after electrical stress of BST films; nevertheless, 10 y reliable operation for Gbit-scale DRAMs is predicted in spite of charge loss by SILC. Lower (Ba+Sr)/Ti ratio is found to be strongly beneficial for low leakage, low SILC, long TBD, and therefore greater long-term reliability. This suggests a worthwhile tradeoff against the dielectric constant, which peaks at a (Ba+Sr)/Ti ratio of 1.05     

Monitoring the degradation that causes the breakdown of ultrathin(<5 nm) SiO2 gate oxides

The degradation of ultrathin oxides subjected to constant-current stresses is analyzed using two independent procedures. First, the injected charge to breakdown is estimated from the stress-induced leakage current (SILC) evolution during the stress. Second, the degradation that leads to the breakdown is directly measured using a two-step stress test. The evolution of the SILC during constant-current stresses proceeds at a rate that decreases with time. Moreover, under low current density stress conditions the normalized SILC at breakdown is no longer constant. However, our two-step test methodology shows that the degradation of the oxide evolves roughly linearly until the breakdown. These apparently contradictory results can be reconciled assuming that the degradation at breakdown is independent of the stress conditions and using the initial SILC generation rate to calculate the charge-to-breakdown by linear extrapolation. The implications for the use of SILC data as a degradation monitor are discussed     

Stress induced leakage current analysis via quantum yieldexperiments

This paper investigates the physical characteristics of stress induced leakage current (SILC) by means of quantum yield (QY) measurements and simulations. QY experiments allow us to infer the energy of tunneling electrons, which is an important factor for the damage generation process. The energy of SILC electrons is analyzed in three different types of p-MOSFET devices: n⁺ gate surface channel and buried channel, and p⁺ gate surface channel. We show that an extra tunneling current component due to native traps can be present even in virgin devices and it is elastic. Then it is shown that SILC electrons have less energy than direct tunneling electrons. This energy loss is then extracted from experimental data and the limitations of this extraction technique are addressed. Finally, experiments on p⁺ gate p-MOSFET clearly demonstrate that electrons tunneling through traps created by electrical stress lose energy irrespective of their initial band. It is then concluded that native and stress induced traps have different physical characteristics     

Trap generation and breakdown processes in very thin gate oxides

Neutral electron traps are generated in gate oxide during electrical stress, leading to degradation in the form of stress-induced leakage current (SILC) and eventually resulting in breakdown. SILC is the result of inelastic, trap-assisted tunneling of electrons that originate in the conduction band of the cathode. Deuterium annealing experiments call into question the interfacial hydrogen release model of the trap generation mechanism. A framework for modeling time-to-breakdown is presented.     

Hot hole stress induced leakage current (SILC) transient in tunneloxides

The mechanisms and transient characteristics of hot hole stress induced leakage current (SILC) in tunnel oxides are investigated. Positive oxide charge assisted tunneling is found to be a dominant SILC mechanism in a hot hole stressed device. The SILC transient is attributed to oxide hole detrapping and thus annihilation of positive charge assisted tunneling centers. Our characterization shows that the leakage current transient in a 100-Å oxide obeys a power law time dependence f^-n with the power factor n significantly less than one. An analytical model accounting for the observed time dependence is proposed