50-nm gate Schottky source/drain p-MOSFETs with a SiGe channel

We propose new SiGe channel p-MOSFETs with germano-silicide Schottky source/drains (S/Ds). The Schottky barrier-height (SBH) for SiGe is expected to be low enough to improve the injection of carriers into the SiGe channel and, as a result, current drivability is also expected to improve. In this work, we demonstrate the proposed Schottky S/D p-MOSFETs down to a 50-nm gate-length. The drain current and transconductance are -339 /spl mu/A//spl mu/m and 285 /spl mu/S//spl mu/m at V/sub GS/=V/sub DS/=-1.5 V, respectively. By increasing the Ge content in the SiGe channel from 30% to 35%, the drive current. and transconductance can be improved up to 23% and 18%, respectively. This is partly due to the lower barrier-height for strained Si/sub 0.65/Ge/sub 0.35/ channel than those for strained Si/sub 0.7/Ge/sub 0.3/ channel device and partly due to the lower effective mass of the holes.     

Thickness dependent gate oxide quality of thin thermal oxide grownon high temperature formed SiGe

For thin oxides grown on high temperature formed Si_0.3Ge_0.7, the gate oxide quality is strongly dependent on oxide thickness and improves as thickness reduces from 50 to 30 Å. The thinner 30 Å oxide has excellent quality as evidenced by the comparable leakage current, breakdown voltage, interface-trap density and charge-to-breakdown with conventional thermal oxide grown on Si. The achieved good oxide quality is due to the high temperature formed Si_0.3Ge_0.7 that is strain relaxed and stable during oxidation. The possible reason for strong thickness dependence may be due to the lower GeO₂ content formed in thinner 30 Å oxide rather than strain relaxation related rough surface or defects     

Modelling negative bias temperature instabilities in advanced p-MOSFETs

The decrease of the threshold voltage V_th of p-channel metal-oxide semiconductor field effect transistors (p-MOSFET) with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed, that accounts for the generation of Si₃Si^√ (P_b0) centers and bulk oxide defects, induced by the tunnelling of electrons or holes through the gate dielectric layer during the electrical stress. The model predicts that V_th shifts are mainly due to the tunnelling of holes at low gate bias |V_G|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |V_G|. Consequently, device lifetime at operating voltage, based on V_th shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on V_th shifts is next investigated. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of Si---N---Si strained bonds, that act as trapping centers of hydrogen species released during the electrical stress. Finally, V_th shifts in p-MOSFET with Hf_ySiO_x gate layers and SiO₂/Hf_ySiO_x gate stacks are simulated, taking into account the generation of P_b0 centers induced by the injection of electrons through the structure. It is found that the transistor lifetime, based on threshold voltage shifts, is improved in SiO₂/Hf_ySiO_x gate stacks as compared to single Hf_ySiO_x layers. This finding is attributed to the beneficial presence of the SiO₂ interfacial layer, which allows the relaxation of strain at the Si/dielectric interface.     

一种高电流增益的SiGe HBT的研制

研制了一种平面集成多晶发射极SiGe HBT。经测量,在室温下电流增益β大于1500,最大达到2800,其Vceo为5V,厄利（Early）电压VA大于10V,βVh乘积达到15000以上。这种器件对多晶硅发射极砷杂质浓度分布十分敏感。     

Recovery of negative bias temperature instability induced degradation of p-MOSFETs with SiON gate dielectric

This paper investigates the recovery property of p-MOSFETs with an ultra-thin SiON gate dielectric which are degraded by negative bias temperature instability (NBTI). The experimental results indicate that the recovery of the NBTI degradation occurs through an electrical neutralization of the NBTI-induced positive charges at the SiON/Si interface and in the gate dielectric. The neutralization of interface charges was a fast process occurring just after the device returned to the recovery state. The neutralization of positive charges in the gate dielectric was a slow process associated with the electron injection into the gate dielectric. Below the gate voltage for strong accumulation, the amount of recovery increased with an increase of the gate voltage. A further increase of gate voltage did not affect the amount of recovery. These experimental results indicate that the major cause of the recovery is a neutralization of the NBTI-induced positive charges by electrons instead of a hydrogen passivation of the NBTI-induced defect sites.     

激光诱导生成锗纳米晶体量子点

采用氧化和析出的方法在氧化硅中凝聚生成锗纳米晶体量子点结构.其形成的锗晶体团簇没有突出的棱角和支晶结构,锗晶体团簇的轮廓较圆混,故可以用球形量子点模型来模拟实际的锗晶体团簇.对比了在高温(800℃～1000℃)条件下和在低温(200℃～500℃)用激光照射条件下所生成的锗纳米晶体结构的PL光谱和对应的锗纳米晶体团簇的尺寸分布.低温用激光照射条件下所生成的锗纳米晶体较小,其PL光谱出现蓝移.用量子点受限模型计算了锗纳米晶体团簇的能隙结构,用Monte Carlo方法模拟了PL光谱和对应的锗纳米晶体团簇的尺寸分布,分别与实验结果吻合较好.     

Properties of self-organized SiGe nanostructures formed by ion implantation

Properties of self-organized SiGe quantum dots formed for the first time by ion implantation of Ge ions into Si are studied using Auger electron spectroscopy, atomic-force microscopy, and scanning electron microscopy. It is found that a spatially correlated distribution of Ge atoms is observed in Si layers implanted with Ge ions after subsequent annealing of these layers. As a result, nanometer-sized regions enriched with germanium are formed; germanium concentration in these regions is 10–12% higher than that in the surrounding matrix of the SiGe solid solution. Optical properties of the layers with SiGe quantum dots were studied using Raman scattering and photoluminescence. An intense photoluminescence peak is observed in the wavelength region of 1.54–1.58 μm at room temperature. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 38, No. 5, 2004, pp. 593–597. Original Russian Text Copyright ? 2004 by Parkhomenko, Belogorokhov, Gerasimenko, Irzhak, Lisachenko.     

一种具有高电流增益的平面集成SiGe HBT

研制了一种平面集成多晶发射极SiGe HBT。经测量,在室温下电流增益β大于1 500,最大达到2 800,其Vceo为5 V,厄利(Early)电压VA大于10 V,βVA乘积达到15 000以上。这种器件对多晶硅发射极砷杂质浓度分布十分敏感。     

Fully depleted strained-SOI n- and p-MOSFETs on bonded SGOI substrates and study of the SiGe/BOX interface

Fully depleted strained-Si n- and p-MOSFETs have been demonstrated on bonded-SiGe-on-insulator (SGOI) substrates. The fully depleted devices show significant electron and hole mobility enhancements of 60 and 35%, respectively, demonstrating that high material quality, thin SGOI substrates can be fabricated by a wafer bonding approach. The bottom SiGe/buried-oxide interface in the SGOI structure and its impact on fully depleted device performance are also investigated.     

High performance,uniaxially-strained,silicon and germanium,double-gate p-MOSFETs

The effect of uniaxial-strain, band-structure, mobility, effective masses, density of states, channel orientation and high-field transport on the drive current, off-state leakage and switching delay in nano-scale, Silicon (Si) and Germanium (Ge), p-MOS DGFETs is thoroughly and systematically investigated. To accurately model and capture all these complex effects, different simulation techniques, such as the Non-local Empirical Pseudopotential method (bandstructure), Full-Band Monte-Carlo Simulations (transport), 1-D Poisson-Schrodinger (electrostatics) and detailed Band-To-Band-Tunneling (BTBT) (including bandstructure and quantum effects) simulations, were used in this study.     

MOSFETs with ultrashallow junction and minimum drain area formed byusing solid-phase diffusion from SiGe

An advanced CMOS structure, in which a raised source/drain and contact windows formed over the field oxide, was fabricated. Ultrashallow junction formation using solid-phase diffusion from doped SiGe layers was used to fabricate MOSFETs. These MOSFETs demonstrated excellent short-channel characteristics and 70%-80%-reduced parasitic drain-junction capacitance. They have ultrashallow junctions with a depth of 25 nm and a low source/drain extension (SDE) resistance: 350 Ω/sq (NMOSFETs) and 390 Ω/sq (PMOSFETs). The isotropic diffused SDE structure was formed by using solid-phase diffusion, which could effectively form a shallow junction and a suitable overlap between gate and SDE. This structure results in good short-channel characteristics and high current drivability     

SiGe HBT高频噪声特性研究

对SiGe HBT的高频噪声进行了模拟.频率f、载流子正向延迟时间τF、集电极电流等因素都对高频噪声有影响.当频率高于高频转角频率时,最小噪声系数NFmin随着频率的增大而线性增大,而不是与f2成正比关系,且NFmin随着集电极电流的增大先减小后增大.结果表明,噪声最小时的最佳偏置电流所对应的特征频率fT并不是最大特征频率,约为最大特征频率的50%.     

High speed p-type SiGe modulation-doped field-effect transistors

We report on the fabrication and characterization of high-speed p-type modulation-doped field-effect transistors (MODFETs) with 0.7-μm and 1-μm gate-lengths having unity current-gain cut-off frequencies (f_T) of 9.5 GHz and 5.3 GHz, respectively. The devices were fabricated on a high hole mobility SiGe heterostructure grown by ultra-high-vacuum chemical vapor deposition (UHV-CVD). The dc maximum extrinsic transconductance (g_m) is 105 mS/mm (205 mS/mm) at room temperature (77 K) for the 0.7-μm gate length devices. The fabricated devices show good pinch-off characteristics and have a very low gate leakage current of a few μA/mm at room temperature and a few nA/mm at 77 K     

高频大功率SiGe/Si HBT的设计

详细地阐述了高频大功率SiGe/Si异质结双极晶体管(HBT)设计中的一些主要问题,主要包括器件的纵向设计中发射区、基区以及收集区中掺杂浓度、形貌分布、层厚的选择以及横向布局设计中的条宽、间隔的选择等.并对这些主要参数的选择给出了一些实用的建议.     

一种基于SiGe工艺的高速宽带D/A转换器

介绍了一款基于0.13 μm SiGe BiCMOS工艺设计的12位4.5 GSPS D/A转换器。首先给出了低延迟高速率DAC设计对制造工艺器件参数的约束评估,设计采用了低延迟架构和CML逻辑。一种创新的输出模式架构突破了大多数DAC输出频谱sin(x)/x包络的极限,有效扩展了DAC的线性度。同时,该架构减小了关节节点的寄生电容和电感,扩展DAC可用模拟输出带宽至5.9 GHz,该DAC芯片流片测试结果显示其转换速率达到了4.5 GHz,延迟时间少于3.5个时钟周期,转换器在时钟频率4.5 GHz,输出模拟信号频率4.455 GHz时,SFDR达到57 dBc。     

High-Temperature Stable IrxSi Gates With High Work Function on HfSiON p-MOSFETs

A novel 1000 degC-stable Ir_xSi gate on HfSiON is shown for the first time with full process compatibility to current very-large-scale-integration fabrication lines and proper effective work function of 4.95 eV at 1.6-nm equivalent-oxide thickness. In addition, small threshold voltages and good hole mobilities are measured in Ir_xSi/HfSiON transistors. The 1000 degC thermal stability above pure metal (900 degC only) is due to the inserted 5-nm amorphous Si, which also gives less Fermi-level pinning by the accumulated metallic full silicidation at the interface     

一种偏置电流可调节的高效率2.4GHz锗硅功率放大器

基于IBM0.35μm SiGe BiCMOS工艺BiCMOS5PAe实现了一种偏置电流可调节的高效率2.4GHz锗硅功率放大器。该功率放大器采用两级单端结构和一种新型偏置电路,除射频扼流电感外,其它元件均片内集成。采用的新型偏置电路用于调节功率放大器的静态偏置电流,使功率放大器工作在高功率模式状态或低功率模式状态。在3.5V电源条件下,功率放大器在低功率模式下工作时,与工作在高功率模式下相比,其功率附加效率在输出0dBm时提高了56.7%,在输出20dBm时提高了19.2%。芯片的尺寸为1.32mm×1.37mm。     

High work function Ir/sub x/Si gates on HfAlON p-MOSFETs

We have fabricated the fully silicided Ir/sub x/Si-gated p-MOSFETs on HfAlON gate dielectric with 1.7-nm equivalent oxide thickness. After 950/spl deg/C rapid thermal annealing, the fully Ir/sub x/Si/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm/sup 2//V/spl middot/s, and the advantage of being process compatible to the current VLSI fabrication line.