Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a $J$-shaped spring design produces a combination of high 3-D compliances and acceptable electrical parasitics. Further, numerical analyses on the $J$ -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 $mu{rm m}$ ). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to $sim$35 GHz without significant power loss.      

Performance Modeling of Low-$k$/Cu Interconnects for 32-nm-Node and Beyond

Challenges and issues with the scaling of low-$k$/Cu interconnects in ultra-large-scale integration (ULSI) devices are reviewed, and the performance of interconnects is featured by considering the effect of the resistance and capacitance per unit interconnect length or the minimum grid length. The grid-scaled resistance–capacitance (GSRC) model is proposed to compare the interconnect performance at various technology nodes. Introduction of low-$k$ films to reduce the line capacitance improves the per-grid value of the resistance–capacitance product, however, the abrupt increment of the line resistivity due to the small-size effect consumes the benefit of the capacitance beyond 32-nm-node. We also discuss power consumption in interconnects with different low- $k$ structures based on experimental works. Continuous reduction of effective $k$-value $(K_{ rm eff})$ is needed to reduce the active power consumption. The way to reduce the interconnect resistance while keeping the interconnect reliability high is a key challenge, particularly for deeply scaled-down ULSIs.      

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm $times$ 6.5 mm with 48 spring contacts on a 0.8 mm $times$ 0.65 mm grid array, each spring measuring 400 $, mu$m $times$ 100 $mu$m. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone ${>}20thinspace 000$ hot plate thermal cycles and ${>}1000$ oven thermal cycles without failure.      

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant $(k _{rm eff})$ of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film $(k=2.5)$ is stacked directly on an oxygen (O)-rich porous SiOCH $(k=2.7)$ film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an ${hbox{Ar}}/ {hbox{N}} _{2} / {hbox{CF}} _{4} / {hbox{O}} _{2}$ gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS–SiOCH prevent the Si–CHx bonds from oxidation during ${hbox{O}} _{2}$-plasma ashing, suppressing the C-depleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication.      

Wiring Effect Optimization in 65-nm Low-Power NMOS

This letter investigates the wiring effect on RF performance in advanced 65-nm low-power CMOS technology. New designs are proposed to minimize the parasitic resistances and capacitances associated with the interconnects in the transistor. Compared with the standard multifinger devices provided by the foundry, the device with the optimized wiring parasitic capacitances and resistances presents improvement up to $sim$ 21% for $f_{T}$ (increased from 89 to 108 GHz) and $sim$22% for $f_{max}$ (increased from 130 to 159 GHz), respectively. The extracted equivalent circuit model parameters indicate that the proposed approach can effectively minimize the parasitic effects leading to improved RF performance of the advanced MOSFETs.      

Extraction of the Effective Mobility of $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs

The extraction of the effective mobility on $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied and shown to be greater than 3600 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. The removal of $C_{rm it}$ response in the split $C$–$V$ measurement of these devices is crucial to the accurate analysis of these devices. Low-temperature split $C$–$V$ can be used to freeze out the $D_{rm it}$ response to the ac signal but maintain its effect on the free carrier density through the substrate potential. Simulations that match this low-temperature data can then be “warmed up” to room temperature and an accurate measure of $Q_{rm inv}$ is achieved. These results confirm the fundamental performance advantages of $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs.      

Using Ink-Jet Printing and Coffee Ring Effect to Fabricate Refractive Microlens Arrays

We developed an ink-jet printing process to fabricate microlens arrays (MLAs) by creating microwell structures based on the “coffee ring effect” to confine the lenses' materials on the substrates. After O $_{2}$ and CF $_{4}$ plasma treatment, the MLAs exhibited well-confined patterns with distinct ridge boundaries possessing repellent surfaces. Further, through appropriate control over the printing of the multidrops and the printhead temperature, we obtained optical microlens with different $f$-numbers. This fabrication method is a simple, shape-controllable, and material-saving approach compared to the traditional fabrication process.      

Test Structures for the Characterization of MEMS and CMOS Integration Technology

Test structures have been used to study the feasibility of bonding MEMS to CMOS wafers to create an integrated system. This involves bonding of prefabricated wafers and creating interconnects between the bonded wafers. Bonding of prefabricated wafers has been demonstrated using a chemical–mechanical polishing enabled surface planarization process and an oxygen plasma assisted low temperature wafer bonding process. Two interwafer connection approaches have been evaluated. For an oxide bonding approach, interconnects between wafers are established through contact vias, using a standard multilevel metallization process after the wafer bonding process. Resistances of 3.8–5.2 $Omega $ have been obtained from via chain test structures and an average specific contact resistivity of 1.7$,times ,$10$^{-8} Omega {hbox{cm}}^{2}$ , measured from the single via Kelvin structures. For a direct metal contact approach, electrical connections have been achieved during the bonding anneal stage due to stress relief of the aluminium film.      

Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults

The effect of crosstalk-induced errors becomes more significant in high-performance circuits and systems. In this paper, compact crosstalk test patterns are introduced for a system-on-a-chip and board level interconnects considering physically effective aggressors. By being able to target multiple victim lines, $6n$, where $n$ is the number of nets patterns are drastically reduced to a constant number $6D$, where $D$ indicates the effective distance among interconnect nets. The test quality for static and crosstalk faults are completely preserved with $6D$ patterns.      

A 10:1 Unequal Wilkinson Power Divider Using Coupled Lines With Two Shorts

A novel unequal Wilkinson power divider is presented. A coupled-line section with two shorts is proposed to realize the high characteristic impedance line, which cannot be implemented by conventional microstrip fabrication technique due to fabrication limitation. The proposed coupled-line structure is compatible with single layer integration and can be easily designed based on an even-odd mode analysis. As a design example, a 10:1 Wilkinson power divider at 2 GHz is fabricated and measured. The measured $-10~{rm dB}$ bandwidth of $S_{11}$ is about 16%, and the isolation $S_{32}$ is better than $-20~{rm dB}$ . The measured amplitude balance between output port 2 and port 3 is between $-10.20~{rm dB}$ and $-9.52~{rm dB}$, and the corresponding phase difference is between 0$^{circ}$ and 4.6$^{circ}$.      

Measurement of Subnanosecond Delay Through Multiwall Carbon-Nanotube Local Interconnects in a CMOS Integrated Circuit

Due to their excellent electrical properties and small size, metallic carbon nanotubes (CNTs) are promising materials for interconnect wires in future integrated circuits. Indeed, simulations have firmly established CNTs as strong contenders for replacing or complementing copper interconnects. In this paper, we analyze the performances of a prototype 0.25-$muhbox{m}$ CMOS digital integrated circuit with select horizontal multiwall CNT (MWCNT) interconnects. Some local interconnect wires of the prototype chip were implemented, during a post-CMOS assembly process, by single 14-$muhbox{m}$ -long metallic MWCNT with 30-nm diameter, representative of future requirements for local interconnects. We evaluate the merits and challenges of MWCNT interconnects in a realistic silicon integrated-circuit environment. We experimentally extract the subnanosecond delays of these wires to quantitatively benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, as well as with the expected performances of scaled copper wires. Finally, we discuss the origin of the discrepancies between our experimental results and the modeling projections.      

Virus Spread in Networks

The influence of the network characteristics on the virus spread is analyzed in a new—the $N$ -intertwined Markov chain—model, whose only approximation lies in the application of mean field theory. The mean field approximation is quantified in detail. The $N$ -intertwined model has been compared with the exact $2^{N}$-state Markov model and with previously proposed “homogeneous” or “local” models. The sharp epidemic threshold $tau_{c}$ , which is a consequence of mean field theory, is rigorously shown to be equal to $tau_{c}=1/(lambda_{max}(A))$ , where $lambda_{max}(A)$ is the largest eigenvalue—the spectral radius—of the adjacency matrix $A$ . A continued fraction expansion of the steady-state infection probability at node $j$ is presented as well as several upper bounds.      

1580-V–40-$hbox{m}Omegacdot hbox{cm}^{2}$ Double-RESURF MOSFETs on 4H-SiC $(hbox{000}bar{hbox{1}})$

Double-reduced-surface-field (RESURF) MOSFETs with $hbox{N}_{2}hbox{O}$ -grown oxides have been fabricated on the 4H-SiC $(hbox{000} bar{hbox{1}})$ face. The double-RESURF structure is effective in reducing the drift resistance, as well as in increasing the breakdown voltage. In addition, by utilizing the 4H-SiC $(hbox{000}bar{hbox{1}})$ face, the channel mobility can be increased to over 30 $hbox{cm}^{2}/hbox{V}cdothbox{s}$, and hence, the channel resistance is decreased. As a result, the fabricated MOSFETs on 4H-SiC $( hbox{000}bar{hbox{1}})$ have demonstrated a high breakdown voltage $(V_{B})$ of 1580 V and a low on-resistance $(R_{rm ON})$ of 40 $hbox{m}Omega cdothbox{cm}^{2}$. The figure-of-merit $(V_{B}^{2}/R_{rm ON})$ of the fabricated device has reached 62 $hbox{MW/cm}^{2}$, which is the highest value among any lateral MOSFETs and is more than ten times higher than the “Si limit.”      

Full-Wave Analysis of Large-Scale Interconnects Using the Multilevel UV Method With the Sparse Matrix Iterative Approach (SMIA)

Moving towards the goal of analyzing whole printed circuit boards (PCBs) and packages using full-wave electromagnetic (EM) methods, the multilevel UV method is applied to the method-of-moments (MoM) solution of the current on large-scale interconnects. The MoM solution uses the layered media Green's functions computed using the numerical modified steepest-descent path (NMSP) method, and is applied to the exterior layers of the interconnect structure. The sparse matrix iterative approach (SMIA) is used to speed up the solution of the iterative matrix solver. The iterative solver is also accelerated by using larger blocks in the block diagonal inverse preconditioner. With the multilevel UV method, a fast solution is presented for solving the current on large-scale interconnects on thin layered structures at high frequencies. We show an example of an interconnect structure that has horizontal dimensions of 12.675 $lambda$ $times$ 12.876 $lambda$ with 24$thinspace$ 848 current unknowns and an interconnect fractional area of approximately 31%. This problem takes a total of 21 min 20 s to solve for the current on the traces on a Pentium 3.2-GHz CPU with 4 GB of RAM.      

Multi-Channel Field-Effect Transistor (MCFET)—Part I: Electrical Performance and Current Gain Analysis

Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow $I_{ rm OFF}$ (16 $hbox{pA}/muhbox{m}$) and high $I_{rm ON}$ (N: 2.27 $ hbox{mA}/muhbox{m}$ and P: 1.32 $hbox{mA}/muhbox{m}$ ) currents are obtained on silicon on insulator (SOI) with a high-$ kappa$/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-$kappa$/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher $V_{rm Dsat}$ for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity.      

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation

We propose an analytical closed-form gate-interconnect interdependent delay model that accounts for the dynamic behavior of signal slope across different regions of operation. In the presence of interconnects, the gate driver influences the input slope of the driven wire affecting the interconnect delay, and the driven wire acts as a parasitic load to the driver affecting the gate delay. Hence, it is essential to consider their interdependence for an accurate estimation of the circuit delay. The proposed model converts a signal slope into its effective fan-out for a simple yet accurate delay estimation. Simulations show that, for ISCAS benchmark circuits, our framework exhibits an error of $≪$ 5.3% at each stage and $≪$ 4.3% for the path delay with a speedup of three orders of magnitude over HSPICE at the 130-nm technology node. Two test chips have been fabricated in 90- and 65-nm CMOS technologies to verify the effectiveness of the proposed model. Measured results show that, for a wide range of interconnect lengths (2000 and 1400 ${rm mu}hbox{m}$ ) and geometries, the proposed model predicts the circuit delay with an error of 5.7% at a supply voltage of $V_{{rm dd}}=1.2 hbox{V}$ and 4.8% at $V_{{rm dd}}=0.3 hbox{V}$ .      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

An Analytical Method to Extract the Physical Parameters of a Solar Cell From Four Points on the Illuminated $J{-}V$ Curve

For a variety of solar cells, it is shown that the single exponential $J{-}V$ model parameters, namely—ideality factor $eta$ , parasitic series resistance $R_{s}$, parasitic shunt resistance $R_{rm sh}$, dark current $J_{0}$, and photogenerated current $J_{rm ph}$ can be extracted simultaneously from just four simple measurements of the bias points corresponding to $V_{rm oc}$, $sim!hbox{0.6}V_{rm oc}$, $J_{rm sc}$, and $sim! hbox{0.6}J_{rm sc}$ on the illuminated $J{-}V$ curve, using closed-form expressions. The extraction method avoids the measurements of the peak power point and any $dJ/dV$ (i.e., slope). The method is based on the power law $J{-}V$ model proposed recently by us.      

Comparative Study of High-Power Continuous-Wave Laser Performance of Yb-Doped Vanadate Crystals

A comprehensive experimental investigation has been conducted into the high-power continuous-wave (CW) laser performance of isostructural Yb-doped vanadates, including three ordered crystals of Yb:YVO $_{4}$, Yb:GdVO $_{4}$, and Yb:LuVO $_{4}$, and two mixed ones with compositional disorder: Yb$_{0.007}$ :Y$_{0.407}$ Gd$_{0.586}$ VO$_{4}$ and Yb$_{0.015}$ :Lu$_{0.52}$ Gd$_{0.465}$ VO$_{4}$ . The CW laser operation of the different vanadates is compared under nearly identical experimental conditions by using a high-power diode laser as the pump source. In addition to the output characteristics of the individual vanadate lasers, the polarization properties and optical bistability exhibited in the laser oscillation are also discussed. The spectroscopic properties closely related to the laser performance are compared and summarized for these Yb-doped vanadates.      

A Programmable Lens-Array Antenna With Monolithically Integrated MEMS Switches

This paper describes a reconfigurable millimeter-wave lens-array antenna based on monolithically integrated microelectromechanical systems (MEMS) switches. This device is constructed as a planar array of 2-bit programmable MEMS antenna–filter–antenna (AFA) unit cells that are used to provide a 1-D programmable “aperture transfer function” between the input and output wavefronts. The fully integrated device consists of 484 (22 $times$ 22) AFA elements and 2420 switches. Switches, bias lines, antennas, and the rest of the RF structure are fabricated on two quartz wafers ($varepsilon_{ r}=3.8$, $tandelta=0.002$) that are subsequently stacked using adhesive bonding to form the tri-layer metal structure of the AFA array. The bonded structure also forms a package for the MEMS switches. This paper investigates the design and fabrication issues and presents the measured data related to yield and frequency response of this lens-array. It also characterizes the performance of this device as a steerable antenna. Measured results show that this lens-array can be used to steer the beam of a low gain horn antenna to $pm {hbox{40}}^{circ}$ in either the $E$- or the $H$-plane. For the fabricated prototype, the yield is estimated to be 50% for the best region of the array, resulting in a relatively high insertion loss and sidelobe level.