一种高增益低纹波的电荷泵电路

针对现有电荷泵存在的体效应、电荷回流等问题,提出一种高增益低纹波的电荷泵电路。该电荷泵采用两路互补的结构,减小了输出电压纹波;使用电位选择电路消除体效应,并使用两相低电平不交叠时钟避免电荷回流,提高了电压增益和转换效率。Hspice仿真结果表明,在级数同为5级和电流负载相同的情况下,文中提出的电荷泵相比现有电荷泵具有更高的输出电压和更小的电压纹波。     

一种高增益交叉耦合电荷泵的设计

针对传统电荷泵的阈值损耗与体效应问题,提出了一种采用两相非交叠时钟的高增益交叉耦合电荷泵。该电荷泵不受阈值压降、体效应等因素影响,开关管导通电阻较小,因而具有较高的电压增益与效率。电路采用SMIC 0.18 μm CMOS工艺设计与仿真,结果表明,该电路的最低工作电压为0.9 V,可驱动120 μA的负载电流,电压增益高达4.8,最大电源效率达到70.18%。     

适用于低压EEPROM编程的双电荷泵电路系统设计

设计了一款应用于低电源电压EEPROM的双电荷泵电路结构,提供存储单元编程所需的高压。基于传统Dickson结构,设计主次两级电荷泵结构：次级电荷泵为两级升压结构,输出电压可增强时钟的驱动能力、抬高其高电平;主级电荷泵采用传输管栅压提升的结构及驱动能力增强的时钟对内部电容进行充放电,提高主级电荷泵每级的传输能力及整体电路的工作效率,最终实现低电源电压下产生高压的目的。同时,通过使能时序控制稳压系统电路,保证了输出电压的稳定性。仿真结果显示,电荷泵升降压速度快、纹波小、效率高。该双电荷泵电路已实际应用于芯片设计中,采用0.18μm EEPROM工艺流片,输出高压稳定,达到设计要求,并且性能良好。     

一种高效率的适合于低功耗应用的电荷泵电路

设计实现了一种高效率的电荷泵电路。利用电容和晶体管对电荷传输开关进行偏置来消除开关管阈值电压的影响。同时,通过对开关管的的衬底进行动态的偏置使得在电荷传输期间当开关管打开时其阈值电压较低,在开关管关断时其阈值电压较高。该电荷泵电路的效率得到了提高。基于0.18μm,3.3V标准CMOS工艺实现了该电路。在每级电容为0.5pF,时钟频率为780KHz,电源电压为2V的情况下,测得的8级电荷泵的输出电压为9.8V。电荷泵电路和时钟驱动电路从电源处总共消耗了2.9μA的电流。该电荷泵电路适合于低功耗的应用。     

一种采用饱和区MOS管作调节开关的电荷泵

为了得到稳定的输出电压,电荷泵电路需要通过负反馈系统进行控制.在传统的"Skip"模式电荷泵中,采用工作在线性区的MOS管做开关,通过控制振荡器来调节输出电压,但这种方式会产生较大的输出电压纹波.设计了一种采用饱和区MOS管作调节开关的电荷泵,通过控制饱和区MOS管的导通电阻来调节电荷泵的输出电压.它工作在占空比为50%的方波信号下,具有很低的输出电压纹波(37mV).     

应用于Flash存储器的一种高效低纹波电荷泵设计

针对交叉耦合型电荷泵电荷回流的问题,本文提出了一种新型六相位电荷泵结构,电荷泵的主体由3个NMOS管和3个泵电容组成。考虑到时钟驱动能力对电荷泵性能的影响,设计通过增加额外的时钟驱动模块实现四相位到六相位的时钟转换,从而减小电荷泵的上升时间并改善输出电压。此外,电路采用并联双支路结构减小输出电容的充放电时间间隔,以减小输出纹波。基于0.13μm工艺的仿真结果表明,在时钟频率为20MHz,负载电容为50pF,负载电流为300μA的条件下,该电路可以实现3.3V到15V的电压转换,效率可达到67.7%,输出纹波仅为38.5mV。     

一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器

设计了一款基于电荷泵高压内电源的恒定跨导轨到轨运算放大器.输入级采用PMOS差分对结构,通过电荷泵产生高于电源电压的输入级内电源,使运放在轨到轨输入范围能正常工作并保持输入跨导恒定.电荷泵电路所需的时钟信号通过内部振荡器电路产生,再通过电压自举电路和时序电路产生所需电平的非交叠开关控制信号,最后利用时间交织结构输出连续稳定的高压内电源.在电荷泵实现中还采用了辅助开关结合跟随运放的结构降低了主开关在切换时的毛刺.该运放在折叠式共源共栅结构中使用增益自举结构提高了总体增益,输出级采用class AB类输出结构实现轨到轨输出.该运算放大器基于0.5μm CMOS工艺完成电路与版图设计,仿真结果表明,在5 V电源电压下,直流增益为150.76 dB,单位增益带宽为53.407 MHz,相位裕度为96.1°,输入级跨导在轨到轨输入共模范围内的变化率为0.001 25%.     

一种采用齐纳管作为开关器件的Dickson电荷泵电路

文章提出了一种基于Dickson原理的电荷泵电路,采用齐纳管作为开关器件。该电路克服了采用MOS管作为开关器件的Dickson电路在多级级联时的转换效率急剧下降问题,并且可以利用齐纳管来稳定输出电压。Spice仿真结果显示,五级齐纳电荷泵可以轻松在3V电源电压下实现10V左右的稳定电压输出。该电路结构简单,与标准CMOS工艺兼容,具有较高的应用价值和经济价值。     

应用于升压电荷泵的自适应衬偏电路

本文设计了一种应用于升压电荷泵的自适应衬偏电路,主要解决电荷泵开关管的电气性能的可靠性问题。该电路主要采用迟滞比较器和触发器相结合的结构,保证PMOS开关管的衬底电位始终和源极、漏极中较高电压保持一致。仿真结果表明,在二倍压电荷泵上应用此衬偏电路,衬底电压始终保持在对应开关管的最佳电位,漏电流可以降低90%,电荷泵的工作效率可以提高4%。     

一种用于LCD驱动的高效电荷泵的设计

电荷泵是一种流行的获取高于供电电源的直流电压转换技术.传统的电荷泵电路采用二极管连接的NMOS管级联来获取较高的电压,由于阈值电压的作用,这种电荷泵的提升效率会随着级数的增加而下降.为了提高效率,文中提出了一种提升5倍电压的采用液晶显示器(LCD)驱动的新型电荷泵结构.特别设计了开关管的栅控电路,消除了阈值电压对电压提升效率的影响,并且通过对开关管尺寸和控制时钟的进一步优化,提高了电压转换效率,降低了功耗,特别适合于小尺寸LCD驱动的需要.     

一种PMOS管传输型高效电荷泵电路设计

设计了一种基于传统Dickson结构的PMOS管传输型电荷泵电路。电路通过衬底电位跟随器实现PMOS管传输,避免了传输过程中阈值电压损失;通过电阻分压反馈网络、控制振荡器输出达到稳压的目的;在电荷泵不工作时,各个子电路关断,实现低功耗设计。仿真结果表明,电路效率高,上电时间短,纹波小;采用SMIC 0.18μm工艺流片,电路达到设计要求,输出高压稳定,驱动能力强,在1M EEPROM电路芯片中得到实际应用。     

High-Voltage Analog System for a Mobile NAND Flash

High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memory in a mobile handset. Regulated high voltage generation at low supply voltage is achieved with optimized oscillator, high-voltage charge pump, and voltage regulator circuits. We developed a design methodology for a high-voltage charge pump to minimize silicon area, noise, and power consumption of the circuit without degrading the high-voltage output drive capability. Novel circuit techniques are proposed for low supply voltage operation. Both the oscillator and the regulator circuits achieve 1.5 V operation, while the regulator includes a ripple suppression circuit that is simple and robust. Through the paper, theoretical analysis of the proposed circuits is provided along with Spice simulations. A mobile NAND Flash device is realized with an advanced 63 nm technology to verify the operation of the proposed circuits. Extensive measurements show agreement with the results predicted by both analysis and simulation.     

一种适用于MEMS麦克风的新型恒压电荷泵设计

实现了一种新型恒压输出电荷泵电路,通过选择合理的电荷泵结构能有效抑制反向电流及衬底电流,并通过一种负反馈稳压电路得到低纹波且不随电源电压变化的稳压输出,非常适用于MEMS麦克风。该电路采用MIXIC0.35μm标准CMOS工艺实现,测试结果表明该电路能自适应2.8～3.6V的电源电压变化,输出稳定的9V直流电压。     

Circuit techniques for a 1.8-V-only NAND flash memory

Focusing on internal high-voltage (V_pp) switching and generation for low-voltage NAND flash memories, this paper describes a V _(pp) switch, row decoder, and charge-pump circuit. The proposed nMOS V_pp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V _pp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V_pp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V_pp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 μA. The proposed pump scheme reduced the area required for charge-pump circuits by 40%     

一种用于AMOLED驱动的多模式高效电荷泵

设计了一种用于AMOLED驱动芯片的多模式高效低纹波电荷泵。该电荷泵通过模式选择,使输出电压可配置,实现多模式功能。针对电压建立和模式切换过程中电荷损耗的问题,利用初始化电路和电压检测电路来保证电荷泵中电荷单向传输,同时利用衬底选择开关来解决电荷泵的体效应问题,提高了电压转换效率。采用双边对称的泵电路结构,减小了输出电压纹波。采用UMC 80 nm CMOS工艺进行仿真。结果表明,负载电流为4 mA时,输出电压为8.4~17 V,四种工作模式下电压转换效率均在90%以上,电压纹波均小于1 mV。     

变频和脉冲跳变双模式控制电荷泵的建模和实现

提出了一种高性能电荷泵的建模和设计实现方法.为了实现在大的负载电流变化范围内具有高转换效率和低输出电压纹波,提出了变频模式(VFM)和脉冲跳变模式(PSM)双模式控制的电荷泵,并建立了相应的数学模型以方便设计参数的分析和选取.芯片采用TSMC0.35 μm标准CMOS数模混合工艺进行设计制造,总面积约为1.4 mm×1.5 mm.测试结果表明,所设计的电荷泵在全负载电流范围内(5 ～ 100 mA)能够实现双模式的自动切换,取得较低电压纹波和较高效率,达到了设计预期,从而验证了变频和脉冲跳变双模式控制电荷泵的可行性.     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

高效电池电源设计研究

传统的电池电源设计存在诸多弊端:低电压供电难,供电时间短,输出电压纹波较高,消耗电流大以及开关频率高时,效率低下。笔者以TI公司的充电泵TPS60210为基础,采用推挽拓扑结构,根据负载电流的大小,自动选择三种不同的工作模式(待机,连续频率及脉冲–跳跃),实现了低EMI、高转换效率的电池电源设计,减少了常规充电泵固有的高输出电压纹波,延长了电池寿命。     

一种低压改进型MOS电荷泵电路的设计

针对使用标准CMOS技术实现的传统电荷泵输出电压较低的不足,文中提出将基本的电荷转移开关进行改进的MOS电荷泵,在泵送增益增加电路的基础上,通过在泵的输出级增加第3个控制信号来提高电荷泵的电压增益,以得到更高的输出电压,将其作为无线传感器的能量收集电路。仿真结果表明,该改进型电荷泵电路适合于低电压设备,并具有较高的泵送增益。其输出电压在同类电荷泵中最高,在1.5 V电源条件下,可高达8.5 V。     

Self-start-up fully integrated DC-DC step-up converter using body biasing technique for energy harvesting applications

An ultra-low power, self-start-up switched-capacitor Two Branch Charge Pump (TBCP) circuit for low power, low voltage, and battery-less implantable applications is proposed. In order to make feasible the low voltage operation, the proposed charge pump along with Non-Overlapped Clock generator (NOC) are designed working in sub-threshold region by using body biasing technique. A four-stage TBCP circuit is implemented with both NMOS and PMOS transistors to provide a direct load flow. This leads to a significant drop in reverse charge sharing and switching loss and accordingly improves pumping efficiency. A post-layout simulation of designed four-stage TBCP has been performed by using an auxiliary body biasing technique. Consequently, a low start-up voltage of 300 mV with a pumping efficiency of 95% for 1 pF load capacitance is achieved. The output voltage can rise up-to 1.88 V within 40 μs with 0.2% output voltage ripple in case of using 400 mV power supply. The designed circuit is implemented by 180-nm standard CMOS technology with an effective chip area of 130.5 μm × 141.8 μm while the whole circuit consumes just 3.2 μW.