Modular, device-scale, direct-chip-attach packaging formicrosystems

A pressing challenge to the commercial implementation of prototype microsystems is the reduction of package size and cost. To decrease package size, a process was developed for the fabrication of high-aspect-ratio, through-wafer interconnect structures. These interconnects permit device-scale packaging of microsystems and are compatible with modern surface mount technology such as flip chip assembly. To minimize package cost, a modular wafer-level silicon packaging architecture was devised. Low temperature bonding methods were used to join package components, permitting integration of driving circuitry on the microsystem die. The reconfigurable architecture allows standard package components to serve a wide variety of applications     

LTCC package for high temperature applications

There is a growing demand for sensors and electronics that can work in harsh environments and at high temperature. Applications include sensors and actuators for control in petroleum and geothermal industry, process monitoring and distributed control systems in the automotive and aerospace fields. Process development and packaging materials for electronic devices are closely connected to such packaging issues. In many cases the package is as important as the device itself in meeting the applications needs.Low temperature co-fired ceramics (LTCC) and thick-film technologies have the potential to incorporate multilayer structures, enabling fabrication of specialized packaging systems. LTCC technology enables easy electrical or optical connections within and between layers in addition to enabling use of integrated passive components, heaters, sensors, converters etc.This paper presents attempts to develop a reliable packaging technology for silicon carbide (SiC) based hydrogen sensors operating at temperatures up to 300 °C. Some simulations of thermal properties were carried out and package structures were made and investigated. The package protects the sensor against mechanical damage and makes possible easy electrical connections. Moreover, the heater and temperature sensors allow for proper temperature regulation of the element. The manufacturing process, basic electrical parameters of the integrated heater as well as real temperature distribution are presented.     

Fabrication of Application Specific Integrated Passive Devices Using Wafer Level Packaging Technologies

Integrated passives have become increasingly popular in recent years. Especially wafer level packaging technologies offer an interesting variety of different possibilities for the implementation of integrated passive components. In this context, particularly the fabrication of integrated passive devices (IPDs) represents a promising solution regarding the reduction of size and assembly costs of electronic systems in package (SiP). IPDs combine different passive components (R,L ,C ) in one subcomponent to be assembled in one step by standard technologies like surface mount device (SMD) or flip chip. In this paper, the wafer level thin film fabrication of integrated passive devices (WL-IPDs) will be discussed. After a brief overview of the different possibilities for the realization of IPDs using wafer level packaging technologies two fabricated WL-IPDs will be presented. Design, technological realization, as well as results from the electrical characterization will be discussed.     

MCM封装技术中的基板设计与分析

通过采用多芯片组件封装技术,将6种由不同集成电路工艺实现的不同类型的芯片集成在单个封装内,简化了系统设计,实现了产品小型化的目标。同时,还详细给出了Zeni EDA工具下的MCM基板设计流程以及MentorPCB环境下的多芯片组件热分析方法。     

Fabrication and accelerated hermeticity testing of an on-wafer package for RF MEMS

A hermetic silicon micromachined on-wafer dc-to-40-GHz packaging scheme for RF microelectromechanical systems (MEMS) switches is presented. The designed on-wafer package has a deembedded insertion loss of 0.03 dB per transition up to 40 GHz (a total measured loss of 0.3 dB including a 2.7-mm-long through line) and a return loss below -18dB up to 40 GHz. The hermeticity of the packaged is tested using an autoclave chamber with accelerated conditions of 130/spl deg/C, 2.7 atm of pressure, and 100% relative humidity. The fabrication process is designed so as to be completely compatible with the MEMS switch process, hence, allowing the parallel fabrication of all the components on a single wafer. The on-wafer proposed packaging approach requires no external wiring to achieve signal propagation and, thus, it has the potential for lower loss and better performance at higher frequencies.     

化学镀镍镀钯浸金表面处理工艺概述及发展前景分析

随着电子封装系统集成度逐渐升高及组装工艺多样化的发展趋势,适应无铅焊料的化学镀镍镀钯浸金（ENEPIG）表面处理工艺恰好能够满足封装基板上不同类型的元件和不同组装工艺的要求,因此ENEPIG正成为一种适用于IC封装基板和精细线路PCB的表面处理工艺。ENEPIG工艺具有增加布线密度、减小元件尺寸、装配及封装的可靠性高、成本较低等优点,近年来受到广泛关注。文章基于对化学镍钯金反应机理的简介,结合对镀层基本性能及可靠性方面的分析,综述了ENEPIG表面处理工艺的优势并探讨了其发展前景。     

Three-dimensional high-frequency distribution networks. I.Optimization of CPW discontinuities

This paper describes a systematic study of coplanar waveguide discontinuities that are requisite components of high-frequency distribution networks. The specific geometries addressed are air bridges, right-angle bends, tee junctions, and Wilkinson dividers. Relative to typical monolithic-microwave integrated-circuit designs, the components studied herein are electrically large in order to minimize signal attenuation. The large size leads to pronounced parasitic effects, and the emphasis of this study was to optimize the electrical performance using simple compensation techniques. The optimization methods are developed using full-wave simulation and equivalent-circuit modeling, and are verified experimentally up to 60 GHz. Part II of this paper describes the implementation and packaging of the components to realize a three-dimensional W-band distribution network     

Ultra CSPTM-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP^TM. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed     

Self-assembly for microscale and nanoscale packaging: steps toward self-packaging

The packaging of microelectromechanical systems (MEMS) and nanoscale devices constitutes an important area of research and development that is vital to the commercialization of such devices. Packaging needs of these devices include interfaces to nonelectronic domains; integration of structures, devices, and subsystems made with incompatible fabrication processes into a single platform; and the ability to handle a very large numbers of parts. Although serial, robotic assembly methods such as pick-and-place have allowed significant manufacturing feats, self-assembly is an attractive option to tackle packaging issues as the size of individual parts decreases below 300 /spl mu/m. In this paper, we review advances made in the usage of self-assembly for packaging and potential directions that growth in this area can assume. In the micrometer scale, we review the use of capillary forces, gravity, shape recognition, and electric fields to guide two- and three-dimensional self-assembly processes. In the nanoscale, we survey the usage of self-assembled molecular monolayers to solve current packaging issues, DNA hybridization for guiding self-assembly processes of nanoscale devices, and methods used to package nanowires or nanotubes into electronic circuits. We conclude with an example of a nanoscale biosensor which directly incorporates the concept of its package into its fabrication process. Even though the idea of a fully self-packaging system has not been demonstrated to date, the body of work reviewed and discussed here presents a solid foundation for the pursuit of this goal.     

Multimode Fiber Devices for Optical Fiber Links, Printing, and Display

It is generally agreed that multimode graded index fiber has become the main fiber technology for optical communication applications. Multimode graded index fibers provide sufficient bandwidth for most applications without the critical tolerances of single mode fibers. In this paper, multimode fiber devices and components based on packaging miniaturized optical components for a GaAs laser array source package, and multichannel waveguides will be discussed. Experimental results, fabrication process and technology limitation for some of the multimode devices will be included. One major drawback of using multimode fibers is the difficulty to obtain simple and efficient switches and taps which are essential for data bus or other optical links. Some possible solutions for multimode fiber switches with miniaturized bulk wave devices will be presented.     

Evolution of a unique flip-chip MCM-L package

Flip-chip (FC) packaging is gaining acceptance in the electronics packaging arena. More sources of bumped die and high density printed wiring boards (PWBs) laminates become available every day. Also, known good die (KGD) issues are being resolved by several companies, and design tools to perform FC packaging designs are becoming more available. This is the infrastructure FC packaging requires to become the packaging method of choice, particularly for >200 I/O applications. FC packages come in a variety of styles: FC plastic ball grid arrays (FC/PBGAs), FC plastic quad flat packs (PC/PQFPs), etc. Presently, the industry's drive is toward single chip packages on low cost laminates; i.e., organic substrates. Work is starting to occur in the area of multichip FC packages, due to the need to increase memory to microprocessor speed communication. In this article, a unique FC/MCM-L package is discussed. Part I will concentrate on the development and reliability testing of a one to four chip leadless FC/MCM-L package. Unlike traditional surface mount (SM) components that are attached to printed wiring boards (PWBs) with leads, the SM pads within the body of the package are used for attachment to a PWB. Collapsible eutectic solder domes are deposited on the SM pads by traditional screen printing. After reflow, these domes are used to connect the FC/MCM-L to the PWB. Challenges encountered during package design, PWB fabrication and first and second level assembly will be discussed. Part II of this article will focus on the extension of this FC/MCM-L package to a BGA second level interconnect. Change of FC attachment method, design enhancements, assembly, and reliability testing results will be presented     

New dimensions in memory

A new 16Mb 3DM module has been developed that satisfies the requirements of high packaging density, high memory capacity, and low fabrication cost. The package density is four times that of TSOP. The module is fabricated by using four 4Mb-DRAM chips at low cost, and it is almost the same size as the single 4Mb-DRAM package (TSOP) currently in use. We also developed a new fabrication process for the module. A 3DM module has advantages in its size, high package density, and electrical performance. Applications that can utilize these advantages include supercomputers, workstations, memory cards, and space equipment     

芯片尺寸封装工艺技术

芯片尺寸封装(CSP)技术是近年来发展最为迅速的微电子封装技术之一。文章介绍了目前出现的四类CSP结构形式，分析了每种结构的工艺技术特点及其制作方法。     

表面贴装声表器件封装失效及其分析

随着声表面波器件日益广泛的应用,声表面波器件的封装尺寸越来越小,封装的难度越来越大,封装过程可能带来的失效问题也越来越多。文章简单介绍了声表面波器件封装形式的变化,论述了表面贴装声表面波器件的封装工艺过程和失效分析的基本概念,并对表面贴装声表面波器件的封装工艺过程中几种主要的失效模式展开分析,促使我们在表面贴装声表面波器件的封装工艺过程加强工序过程的控制,从而提高表面贴装声表面波器件的可靠性,更好地满足顾客的需要。     

A monolithic decode-drive circuit for magnetic memories

The highly replicated decode-drive circuitry of magnetic memories is being produced at a very low cost with batch-fabricated integrated-circuit technology. This has resulted from judiciously reconfiguring traditional circuit forms in order to optimize their fabrication. A new monolithic circuit function and its application are described. The circuit is used for low-cost high-speed 400-mA switching in magnetic memories. The functions of address decoding and timing control are also incorporated into the circuit. The address scheme employs no transformers and possesses the advantages of miniaturization. Details of the circuit configuration, topology, and packaging are described and illustrated.     

A chip-on-board packaged bandpass filter using cross-coupled topological optimised hairpin resonators for X-band radar application

Devices that are compact in design and fabrication continue to draw attention for specific applications that require high performance. A compact elliptic bandpass filter using a cross-coupled topological structure with a hairpin resonator optimised for radar applications is presented in this paper. This work presents the design theory and corresponding semiconductor fabrication processes and describes the chip-on-board packaging method in detail. The proposed design of the bandpass filter can not only reduce the size of the device and result in good RF performance, but the accurate semiconductor fabrication process can also ensure high performance further. In addition, the presented chip-on-board packaging method can greatly enhance the reliability and long-term stability of a microwave device, which rarely introduces RF characteristic interference. The simulated, bare-chip measured and final chip-on-board measured results agreed well, which validated the correctness of the proposed approach.     

System on Wafer: A New Silicon Concept in SiP

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.      

Integrated packaging of over 100 GHz bandwidthuni-traveling-carrier photodiodes

Hybrid packaging techniques, in which the device substrate is different from the package substrate, and wire bonding or solder interconnections are used, are inadequate for ultrahigh-speed (>100 GHz) wideband applications. By employing wafer-bonding techniques, an integrated packaging (IP) technology was developed, in which devices are fabricated directly on the package substrate, and the interconnections are made as a part of the device fabrication process. This IP process was used to fabricate uni-traveling-carrier photodiodes (UTC-PD's) integrated with millimeter-wave coplanar waveguides (CPW) on package compatible sapphire with high yield. The performance of wafer-bonded UTC-PD's with 3-dB bandwidth of 102 GHz was similar to that of conventional devices, and the CPW's exhibited low dispersion     

An Integrated-Circuit Approach to Extracellular Microelectrodes

This paper describes a new multielectrode microprobe which utilizes integrated-circuit fabrication techniques to overcome many of the problems associated with conventional microelectrodes. The probe structure consists of an array of gold electrodes which are supported on a silicon carrier and which project beyond the carrier for a distance of about 50 ? to allow a close approach to active neurons. These electrodes are covered with a thin (0.4-?) layer of silicon dioxide which is selectively removed at the electrode tips using high-resolution photoengraving techniques to define the recording areas precisely. The processing sequence described permits any two-dimensional electrode array to be realized. Interelectrode spacings can be accurately controlled in the range from 10 to 20 ? or larger, and electrode-tip diameters can be as small as 2 ?.