16×16位高速低功耗并行乘法器的实现

基于0.6μm双阱CMOS工艺模型,实现了一种高速低功耗16×16位并行乘法器。采用传输管逻辑设计电路结构,获得了低功耗的电路性能。采用改进的低功耗、快速Booth编码电路结构和4-2压缩器电路结构,它在2.5V工作电压下,运算时间达到7.18ns,平均功耗(100MHz)为9.45mW。     

一种采用改进Domiono加法器的高速流水线乘法器

乘法器是数字信号处理系统中的关键。流水线乘法顺可以较小的代价获得较高的平均速度。本文给出了流水线乘法器的结构;提出了两种改进型Domino加法器电路;对改进型电路作了分析和模拟。模拟结果表明,采用新的改进剂Domino电路后,流水线乘法器的速度可以显著提高。     

适用于VLSI的一种并行乘法器结构

本文给出了二进制补码和无符号乘法器的通用表达式。对VLSI乘法器的结构进行了讨论。     

基于部分积概率分析的高精度低功耗近似浮点乘法器设计

浮点乘法器是高动态范围(HDR)图像处理、无线通信等系统中的关键运算单元,其相比于定点乘法器动态范围更广,但复杂度更高。近似计算作为一种新兴范式,在受限的精度损失范围内,可大幅降低硬件资源和功耗开销。该文提出一种16 bit半精度近似浮点乘法器(App-Fp-Mul),针对浮点乘法器中的尾数乘法模块,根据其部分积阵列中出现1的概率,提出一种对输入顺序不敏感的近似4-2压缩器及低位或门压缩方法,在精度损失较小的条件下有效降低了浮点乘法器资源及功耗。相较于精确设计,所提近似浮点乘法器在归一化平均错误距离(NMED)为0.0014时,面积及功耗延时积方面分别降低20%及58%;相较于现有近似设计,在近似位宽相同时具有更高的精度及更小的功耗延时积。最后将该文所提近似浮点乘法器应用于高动态范围图像处理,相比现有主流方案,峰值信噪比和结构相似性分别达到83.16 dB 和 99.9989%,取得了显著的提升。     

基于新型部分积生成器和提前压缩器的乘法器设计

为了提高乘法器性能,采用基4 Booth编码算法设计Booth编码器,使用华莱士树压缩结构设计16 bit有符号数乘法器;针对部分积生成的复杂过程提出一种新的部分积生成器,同时进行部分积的产生与选择,提高了部分积生成效率;针对压缩过程中的资源浪费,提出一种部分积提前压缩器,将某几位部分积在进入压缩树之前进行合并,减少了压缩单元的使用。基于28 nm工艺对乘法器进行逻辑综合,关键路径延时为0.77 ns,总面积为937.3μm²,功耗为935.71μW,能够较好地提升乘法器的面积利用率和运算性能。     

常系数乘法器的分布式并行进化设计

为了进一步改善进化图生成EGG(Evolutionary Graph Generation)系统的性能，我们在EGG中引入了基于PCs簇Linux计算平台并使用消息传递接口MPI（Message-Passing Interface)技术成功地实现分布式的EGG并行系统DPEGG（Distributed and Parallel EGG)。实验结果充分表明DPEGG系统在生成的解质量方面略好于EGG系统。特别值得指出的是，DPEGG系统的运行时间开销还大大地减少了。     

采用FPGA实现的8位高速并行乘法器

利用Altera公司的MAX PLUSⅡ软件及FPGA器件中的FEX10K10芯片来实现8位并行乘法器。对设计的器件进行了仿真。结果表明本设计是正确的。要用FPGA设计电路大在缩短了设计周期，降低了开发成本。     

基于绝热逻辑的低功耗乘法器电路设计

基于绝热开关理论的能量回收逻辑与传统的静态CMOS逻辑相比,能够大大减少电路的功率消耗。这里介绍了一种使用单相正弦电源时钟的能量回收逻辑,分别用静态CMOS逻辑和这种能量回收逻辑设计,并仿真了一个两位乘法器电路,比较了这两种电路的性能。研究表明,采用能量回收逻辑设计的乘法器显著降低了电路的功率消耗。     

定宽截断式并行乘法器的实现研究

文章主要阐述了并行补码运算的定宽截断式乘法器是如何实现的。两个N位的输入,定宽的乘法器将产生N位的输出,而不是2N位的输出,但因截断会带来误差。与标准的2N位输出乘法器相比,文章中所设计的乘法器具有面积更小,延迟时间更短的优点。在设计中,为了能让定宽截断式乘法器的输出更精确,所用的计算时间更短,生成进位电路部分的设计最为关键。实验表明,文章中所设计的固定位宽截断式乘法器与其他的固定位宽的乘法器相比,误差更小,成本更低。基于以上特性,这种乘法器特别适合应用于多媒体处理和数字信号处理芯片的设计中,例如数字滤波、译码电路等。     

32×32高速乘法器的设计与实现

设计并实现了一种32×32高速乘法器.本设计通过改进的基4 Booth编码产生部分积,用一种改进的Wallace树结构压缩部分积,同时采用一种防止符号扩展的技术有效地减小了压缩结构的面积.整个设计采用Vetilog HDL进行了结构级描述,用SIMC 0.18μm标准单元库进行逻辑综合.时间延迟为4.34 ns,系统时钟频率可达230 MHz.     

A fast final adder for a 54-bit parallel multiplier for DSP application

A novel redundant binary-to-natural binary converter circuit is proposed which is used in the final addition stage of parallel multipliers. Use of this circuit in the final adder stage proves to be 17% faster than carry-look-ahead implementation. We used this algorithm in such a way that no redundant binary adder is required in compressing partial product rows. Only the natural 4:2 compressor circuits are used.     

A New Static Differential CMOS Logic with Superior Low Power Performance

A new differential static CMOS logic (DSCL) family is devised. The new circuit is fully static, making it simple to design. The circuit topology of the DSCL and its operation is explained. Delay optimization of the new circuits was performed. It showed the fully static behavior of these circuits. Their performance in terms of delay, power, and area is compared to that of conventional static differential logic and dynamic differential logic. Spice simulations using a 0.18 m technology with a power supply of 1.8 V was utilized to evaluate the performance of the three circuits. Two different sets of simulations were carried out; one with equal input capacitances of all circuits and another with equal circuit delays. For each design, all circuits were optimized for minimum delay. It is shown that at equal input capacitance, the DSCL achieved 40% less delay than the DCVSL at one third the power. Also, at equal delay, the DSCL achieved 20% of the power dissipation of the DCVSL and 78% of the DDCVSL making it the most energy-efficient among the three circuits.Muhammad E.S. Elrabaa received his B.Sc. degree in computer Engineering from Kuwait University, Kuwait in 1989, and his M.A.Sc. and PhD degrees in Electrical Engineering from the University of Waterloo, Waterloo, Canada, in 1991 and 1995, respectively. His graduate research dealt with Digital BiCMOS ICs and Low-Power circuit techniques. From 1995 till 1998, he worked as a senior circuit designer with Intel Corp., in Portland, Oregon, USA. He designed and developed low power digital circuits for Microprocessors. From 1998 till 2001 he was with the EE department, UAE University as an assistant professor. In 2001, he joined the computer Engineering department, KFUPM University. His current research interests include reconfigurable computing, low-power circuits, and communication circuits. He authored and co-authored several papers, a book and holds two US patents.     

10 μA Quiescent Current Opamp Design for LCD Driver ICs

This paper examines the design considerations for an opamp to be used in a low-power consumption LCD driver IC: (1) slew rate enhancement suitable for a rail-to-rail input stage; (2) improved phase compensation with reduced compensation capacitance; and (3) limitation of instantaneous current consumption. The experimental results support our opamp design approach and indicate the feasibility of 10 A quiescent current opamp.     

基于ADSP-BF561车载多媒体系统

给出一套新的车载多媒体系统设计方案,该系统是基于美国模拟器件公司(AnalogDeviceInc.,ADI)最新发布的ADSP-BF561嵌入式多媒体处理器设计出的支持嵌入式音视频应用,GPS,GPRS,HFCK,网口,USB,CAN总线,I2C控制和海量存储等功能,是功能强大的多媒体系统,尤其适用于车载环境,亦可作为个人数字助理应用。     

Enhancement of the ill-conditioned original recordings using novel ICA technique

The independent component analysis (ICA) method proposed in this study uses FastICA algorithm to improve the quality of the original recordings, which can be used as valuable pre-processing technique in signal processing methods. Initially, the ill-conditioned original audio recordings are separated using ICA methods and later, they are reconstructed using modified un-mixing matrix. The simulation results showed huge improvement of the original signal after reconstruction. The new method is found to be good because the accuracy is more compared to others in terms of the variance of the Gain matrix. The proposed method has potential applications in audio and biosignal processing techniques.     

A sensor monitoring system for telemedicine,safety and security applications

A sensor system capable of medical, safety and security monitoring in avionic and other environments (e.g. homes) is examined. For application inside an aircraft cabin, the system relies on an optical cellular network that connects each seat to a server and uses a set of database applications to process data related to passengers’ health, safety and security status. Health monitoring typically encompasses electrocardiogram, pulse oximetry and blood pressure, body temperature and respiration rate while safety and security monitoring is related to the standard flight attendance duties, such as cabin preparation for take-off, landing, flight in regions of turbulence, etc. In contrast to previous related works, this article focuses on the system’s modules (medical and safety sensors and associated hardware), the database applications used for the overall control of the monitoring function and the potential use of the system for security applications. Further tests involving medical, safety and security sensing performed in an real A340 mock-up set-up are also described and reference is made to the possible use of the sensing system in alternative environments and applications, such as health monitoring within other means of transport (e.g. trains or small passenger sea vessels) as well as for remotely located home users, over a wired Ethernet network or the Internet.