超低功耗逐次逼近寄存器型模数转换器的设计

采用逐次逼近方式设计了一个12 bit的超低功耗模数转换器(ADC).为减小整个ADC的芯片面积、功耗和误差,提高有效位数(ENOB),在整个ADC的设计过程中采用了一种改进的分段电容数模转换器(DAC)阵列结构.重点考虑了同步时序产生电路结构,对以上两个模块的版图设计进行了精细的布局.采用0.18 μm CMOS工艺,该ADC的信噪比(SNR)为72 dB,有效位数(ENOB)为11.7 bit,该ADC的芯片面积只有0.36 mm2,典型的功耗仅为40 μW,微分非线性误差小到0.6 LSB、积分非线性误差只有0.63 LSB.整个ADC性能达到设计要求.     

一种基于电压窗口技术的超低功耗SAR ADC

本文提出了一种应用于生物医学的超低功耗逐次逼近型模数转换器(SAR ADC).针对SAR ADC主要模块进行超低功耗设计.数模转换(DAC)电路采用vcm-based以及分段电容阵列结构来减小其总电容,从而降低了DAC功耗.同时提出了电压窗口的方法在不降低比较器精度的情况下减小其功耗.此外,采用堆栈以及多阈值晶体管结构来减小低频下的漏电流.在55nm工艺下进行设计和仿真,在0.6V电源电压以及l0kS/s的采样频率下,ADC的信噪失真比(SNDR)为73.3dB,总功耗为432nW,品质因数(FOM)为11.4fJ/Conv.     

基于分段电容阵列的改进型逐次逼近型ADC

为缩短高速模数转换器(ADC)中高位(MSB)电容建立时间以及减小功耗,提出了一种基于分段式电容阵列的改进型逐次逼近型(SAR)ADC结构,通过翻转小电容阵列代替翻转大电容阵列以产生高位数字码,并利用180 nm CMOS工艺实现和验证了此ADC结构。该结构一方面可以缩短产生高位数码字过程中的转换时间,提高量化速度;另一方面其可以延长大电容的稳定时间,减小参考电压的负载。通过缩小比较器输入对管的面积以减小寄生电容带来的误差,提升高位数字码的准确度。同时,利用一次性校准技术减小比较器的失配电压。最终,采用180 nm CMOS工艺实现该10 bit SAR ADC,以验证该改进型结构。结果表明,在1.8 V电源电压、780μW功耗、有电路噪声和电容失配情况下,该改进型SAR ADC得到了58.0 dB的信噪失真比(SNDR)。     

高精度SAR ADC电容阵列设计及校准算法

在高精度逐次逼近寄存器模数转换器(SAR ADC)中,电容阵列是SAR ADC的核心之一。电容阵列中的电容失配问题是导致转换精度降低的一个重要原因。为了尽可能改善这一问题,设计了一种6+6+6分段电容阵列,并且基于这种阵列设计了权重迭代算法的前台数字校准。该方法不需要额外的电容阵列,利用自身的电容阵列与比较器量化出电容失配,计算出每一位输出码的权重校准系数,用来对正常量化出的输出码进行编码,实现校准功能。仿真结果表明,引入电容失配的18 bit SAR ADC经过该算法校准后,信噪比(SNR)从77.6 dB提升到107.6 dB,无杂散动态范围(SFDR)从89.8 dB提升到125.6 dB,有效位数(ENOB)从12.54 bit提升到17.54 bit。在SMIC 0.18μm工艺下,该校准算法对高精度SAR ADC的动态性能具有较大提升。     

面向WSN结点SoC的逐次逼近模数转换器

设计了一种适合于无线传感网(WSN)结点SoC芯片传感器接口电路应用的12 bit精度逐次逼近型(SAR)模数转换器(ADC)。为了实现高精度、低成本,并兼容射频CMOS工艺的要求,利用全差分结构和带有Auto-zero失调消除功能的比较器提高转换精度。采用分段式电容阵列DAC减小芯片占用面积,通过构造符合精度要求的MOM电容单元,使电容阵列符合射频CMOS的工艺特点,利于嵌入式应用。同时,采取增加辅助电容的办法扩大输入信号范围。该ADC在0.18μm 1P6M标准CMOS工艺下实现,版图面积为0.9 mm2,最高采样速率为1 MS/s,在1.8 V电源电压下,整体功耗仅为2 mW。     

基于16位SAR模数转换器的误差校准方法

为了实现较高精度(16位及更高)的逐次逼近(SAR)ADC,提出了一种误差自动校准技术。考虑到芯片面积、功耗和精度的折中,采用了电荷再分配分段电容DAC结构,并采用准差分输入方式提高ADC的信噪比。为了消除电容失配引入的误差,提出了一种误差自动校准算法,利用误差校准DAC阵列对电容失配误差进行量化并存储在RAM中,在AD转换过程中实现误差消除。     

一种可校正的12位C2C电容阵列混合结构SAR ADC

提出了一种可校正的12位C2C电容阵列混合结构逐次逼近型模数转换器(SAR ADC),其数模转换器(DAC)由低6位分裂式C2C DAC阵列与高6位二进制DAC阵列构成。提出的混合结构DAC既解决了中高精度二进制SAR ADC中总电容过大的问题,又避免了分段式二进制DAC分数值桥接电容无法与单位电容形成匹配的问题。该结构能显著降低整个ADC的动态功耗。此外,将高位终端电容和低2~6位量化电容拆分成相等的两个电容,引入冗余量,使得该ADC的电容权重可以被校准,降低了电容失配以及寄生电容的影响。最后,为了避免电容上极板复位信号因电容阵列容值大而导致的延时偏大问题,采用高6位DAC采样的方式,并在高6位DAC中引入单位电容大小的终端电容,弥补了参考电压区间不完整的缺陷。仿真结果显示,在1.5 V电压下,该ADC总体功耗仅为111.84 μW,ENOB为12.49位,SFDR为91.46 dB,SNDR为76.97 dB。     

一种用于14 bit SAR ADC的DAC设计

本文设计了用于14bit逐次逼近型模数转换器（SAR ADC）的DAC电路。针对该DAC,介绍一种全差分分段电容阵列结构以缩小DAC的版图面积;高二位权电容采用热码控制,用以改善高位电容在转换时跳变的尖峰以及DAC的单调性;对电容阵列采用数字校准技术,减小电容阵列存在的失配,以提高SAR ADC精度。校准前,SAR ADC的INL达到10LSB,DNL达到4LSB;与校准前相比,校准后,INL〈0.5LSB,DNL〈0.6LSB。仿真结果表明,本DAC设计极大改善SAR ADC的性能,已达到设计要求。     

基于数字自校准的14位SAR ADC的设计

为了降低电容型模数转换器（ADC）中的电容失配带来的非线性影响,提出了一种基于复用低位电容自校准的逐次逼近型（SAR）ADC电路结构,利用低位电容转化高位电容失配引起的误差电压,实现高位电容失配校准。在55 nm CMOS工艺下实现了该ADC结构。该结构ADC工作过程为失调误差提取与正常转换两阶段,失调误差提取阶段中利用低位电容将高位电容失配产生的误差电压转换为误差码并存储,将误差码与正常转化数字码求和得到最终的数字输出,实现电容失配自校准。为了提高ADC采样速率,该结构通过分段结构将电容阵列分为三段降低了单位电容数量。仿真结果表明,在1.2V电源电压,80 MSPS采样速率下,引入电容失配后电路功耗为3.72 m W,有效位数为13.45 bit,信噪失真比（SNDR）为82.75 dB,相比未校准分别提高4.41 bit,26.58 dB。     

一种基于扰动的SAR ADC数字校准算法

为了减少分段式电容阵列ADC中分段电容引起的电容失配效应对转换精度的影响,采用最小均方根(LMS)迭代方法,实现了一种基于扰动的逐次逼近型(SAR)ADC数字前台校准算法。对同一个模拟输入信号先后加入作为扰动的模拟失调电压+Δd和-Δd,依次进行量化。使用LMS对两次量化结果进行加权迭代,得到最佳权重,实现了对ADC的校准。针对电容失配效应、寄生电容效应的影响,搭建了14位SAR ADC数模混合仿真验证系统。仿真结果表明,该校准算法将系统的无杂散动态范围(SFDR)从62.6 dB提升到87.7 dB。     

A 1.8-2.6 GHz CMOS VCO with switched capacitor array and switched inductor array

The design of a 1.76-2.56 GHz CMOS voltage-controlled oscillator(VCO)with switched capacitor array and switched inductor array is presented.Fabricated in 0.18μm 1P6M CMOS technology,the VCO achieves a 37% frequency tuning range.The measured phase noise varies between-118.5 dBc/Hz and-122.8 dBc/Hz at 1 MHz offset across the tuning range.Power consumption is about 14.4 mW with a 1.8 V supply.Based on a reconfigurable LC tank with switched capacitor array and switched inductor array,the mnmg range is analyzed and derived in terms of design parameters,yielding useful equations to guide the circuit design.     

Microwave Group Delay Time Adjuster Using Parallel Resonator

This letter describes the design of a group delay time adjuster (GDTA) using a parallel resonator. The GDTA consists of a variable capacitor and a variable equivalent inductor. These components are controlled by two bias voltages separately. The variable equivalent inductor is realized using a high impedance transmission line terminated with the variable capacitor. Group delay time can be adjusted by varying the capacitance and the inductance while keeping the fixed resonance frequency. When the proposed GDTA is fabricated on the Korean RFID frequency band (908.5-914MHz), we could obtain about 3ns group delay time variation with excellent flatness     

A low-distortion BiCMOS seventh-order Bessel filter operating at2.5 V supply

This paper presents the design of a seventh-order continuous-time Bessel filter using a new low-voltage and highly linear BiCMOS transconductor. A high-gain and parasitic-insensitive integrator is obtained by using an active capacitor scheme. The filter has been designed to operate at a 2.5 V supply with a nominal -3 dB cutoff frequency of 600 kHz. It has been fabricated in 1 μm, double-poly 6-GHz BiCMOS process. The inband group delay variation is less than 10 ns. The total harmonic distortion (THD) measured with a 100 kHz input signal is less than -49 dB for a 2 V_pp amplitude and the dynamic range is 77 dB. The filter can be frequency tuned over almost one decade with a gain variation less than 0.2 dB in the passband. A common-mode rejection ratio (CMRR) of 53 dB in the passband is observed, thanks to a careful common-mode control strategy     

射频MEMS压控电容器

研究了射频 MEMS压控电容器的设计和制造工艺。压控电容器的制作采用了 MEMS制造技术 ,其主要结构为硅衬底上制作金属传输线电极和介质层 ,然后制作金属膜桥作为电容器的另一个电极。通过改变加在金属膜桥与传输线间的电压达到改变电容值的目的。这种压控电容器可以工作于射频和微波波段 ,具有很高的Q值。测试结果如下 :在 1 GHz、0 V时 Q值达到 3 0 0 ,0偏压电容值为 0 .2 1 p F,当加上驱动电压后 Cmax/ Cmin的变比约为 4∶ 1     

Compact, megavolt, rep-rated Marx generators

A concept for compact, megavolt Marx generators has been developed, resulting in several designs which are approximately half the diameter and half the height of conventional units. The customized Marx capacitor assemblies utilize multiple windings incorporated into a single common capacitor case. Spark gap switch electrodes extend directly from the external capacitor terminals, eliminating the need for additional buswork. In order to construct the Marx generator, two capacitor assemblies are positioned opposite each other so that the electrodes line up in a vertical column between the two assemblies. Because the entire assembly is housed inside a pressurized (207 kPa of SF₆) gas vessel, the need for individual switch housings is eliminated. A four-stage, 400-kV-output Marx generator has been tested, operating at a repetition rate of 2-3 pps (power supply limited) continuously for over 5000 discharge cycles at 85-kV stage charging voltage. A second design has been fabricated and tested, utilizing 16 Marx stages to develop a 1.5-MV (open circuit) output voltage, and is contained in a cylindrical gas vessel 76.2 cm in diameter and 55.9 cm in height, weighing approximately 72.6 kg. Experimental measurements indicate a stage inductance of approximately 45 nH per 100-kV Marx stage     

A 1.2- mu m CMOS current-controlled oscillator

A simple, fully symmetrical, current-controlled CMOS oscillator is presented. The oscillator uses two grounded capacitors. This 5-V architecture permits relatively large capacitor voltage amplitudes, thus minimizing jitter. The design also operates with power supply voltages as low as 3 V. Because there are no special capacitor requirements, the design is compatible with standard scaled digital CMOS processes. The use of a double differential latching comparator allows high-speed operation with good control linearity. The circuit was successfully fabricated using a 1.2- mu m CMOS process.<>     

Two different LNA optimizing techniques

Two different LNA design techniques,namely the classical two-port technique and the Shaeffer technique, have been introduced,compared and implemented for practical design.Their merits and drawbacks are also discussed.This paper mainly focuses on the former technique,which is seldom introduced in traditional papers. Since a parasitic capacitor of the transistor is included in the computation of the former technique,the errors caused by the ignorance of the capacitor have been minimized,which is superior to traditional techniques.Using the former technique,a fully integrated LNA is realized with only 1.4 dB while drawing 1.3 mA DC at 2.4 GHz for simulation results.Another version of the LNA is designed using the latter technique,which has been fabricated.     

Depletion trench capacitor technology for megabit level MOS dRAM

A new technology has been developed for future megabit level MOS dRAM's, in which a depletion-type capacitor is formed at a trench in the cell capacitor region. Trenches have been successfully formed by reactive ion etching utilizing CBrF3gas at a pressure of about 14 mTorr. Phosphorous could be doped onto the trench surface with sufficient controllability using a phospho-silicate glass film as a diffusion source. The capacitance of the depletion trench capacitor (DTC) was influenced by the surface orientation of the trench sidewalls. DTC breakdown voltage where gate oxide thickness was 20 nm was more than 7 V. This is large enough for practical use under 3-V operating conditions.     

一种适用于LDO的三级误差放大器的设计

为了促进LDO在低电源电压环境中的应用,提高其稳定性,在此采用SMIC0．35um,N阱CMOS工艺,设计并实现了适用于LDO内部误差放大器的一种单密勒电容频率补偿的三级CMOS运算放大器。仿真结果表明该运算放大器的工作电压范围宽（2．5～6．5V）,静态电流小,开环电压增益为112．16dB,相位裕度为89．03°,增益带宽积为6．04MHz,共模抑制比为89．3dB,电源抑制比为104．8dB。     

一种紧凑型宽带高功率微波驱动源

为实现对传输线开关振荡器或振荡天线进行快速充电,以提高其耐压能力和产生高频振荡信号的能量效率,本文研制了一种基于Tesla变压器的电容储能型脉冲驱动源。本文首先介绍该驱动源的工作原理和运行过程,接着利用等效电路方法分析了关键电路参数对负载充电过程的影响,然后介绍该驱动源的具体工程设计,最后介绍该驱动源初步测试结果以及将其应用于变压器油在10 ns量级脉冲下击穿特性研究的实验情况。实验表明,输出火花开关在中储电容器充电电压为-191 kV导通时,通过电感对等效电容为15 pF的传输线充电电压峰值为-224 kV,电压上升时间约10 ns。研究结果表明本文研究的驱动源能够满足对传输线开关振荡器等电容负载进行快速充电至数百kV高压的应用需求。