一种结构新颖的流水线Booth乘法器设计

在对传统Booth乘法器研究的基础上,介绍了一种结构新颖的流水线型布什(Booth)乘法器。使用基-4 Booth编码、华莱士树(Wallace Tree)压缩结构、64位Kogge-Stone前缀加法器实现,并在分段实现的64位Kogge-Stone前缀加法器中插入4级流水线寄存器,实现32 t×32 bit无符号和有符号数快速乘法。用硬件描述语言设计该乘法器,使用现场可编程门阵列(Field Programmable Gate Array,FPGA)进行验证,并采用SMIC 0.18 μm CMOS标准单元工艺对该乘法器进行综合。综合结果表明,电路的关键路径延时为3.6 ns,芯片面积＜0.134 mm,功耗＜32.69 mW。     

67×67位乘法器的改进四阶Booth算法实现

针对67×67位乘法器,提出并实现新型的设计方法.先提出改进的四阶Booth算法,对乘数编码,以减少部分积的数目,提高压缩速度和减少面积,再研究优化和分配方法,对部分积和进位信号以及一个134位的补偿向量进行优化分配,并对部分积压缩,最后研究K-S加法器的改进方法,求和以实现134位乘积.采用TSMC的0.18 μm工艺库,Synopsys的Design compiler工具和Altera的Quautus4.2工具分析结果表明,基于本文方法实现的电路比DesignWare自带的乘法器实现的电路相比,性能总体占优.     

基于Booth\CSD混合编码的模 乘法器的设计

在余数系统的设计中,模加法器和模乘法器的设计处于核心地位,尤其是模乘法器的性能,是衡量余数系统系能的主要标志之一。文中先推导出Booth编码下的模 乘法器设计的算法,然后针对Booth编码模乘法器设计中译码电路复杂的问题,提出了一种基于Booth/ CSD混合编码的模乘法器设计方法,基于Booth/CSD编码的模乘法器部分积的位宽相对传统的Booth编码乘法器而言,减少了50%;经试验证明,与传统的基-Booth编码的模乘法器相比这种混合编码的模乘法器的速度提高了5%,面积减少24.7%。     

基于改进的布斯算法FPGA嵌入式18×18乘法器

设计了一款嵌入FPGA的乘法器,该乘法器能够满足两个18b有符号或17b无符号数的乘法运算。该设计基于改进的布斯算法,提出了一种新的布斯译码和部分积结构,并对9-2压缩树和超前进位加法器进行了优化。该乘法器采用TSMC 0.18μm CMOS工艺,其关键路径延迟为3.46ns。     

Redundant binary partial product generators for compact accumulation in Booth multipliers

The use of signed-digit number systems in arithmetic circuits has the advantage of constant time addition. When signed-digit number systems are used in binary, they are referred as redundant binary. Here, we present a new encoding technique for generating redundant binary partial products for a multiplier, without using any additional hardware. We express each normal binary partial product in one's complement form, with an extra bit denoting the sign bit. The proposed redundant binary partial product generator (RBPPG) achieves the highest reduction in the number of partial products (75%) for a radix-4 multiplier. The carry-free nature of redundant binary adders is exploited to add the extra bits with the partial products, without using any extra adder stages. The new partial product generation (PPG) technique is shown to improve the speed of multipliers, with the least number of adder stages, irrespective of the multiplier size.     

基于FPGA的FIR数字滤波器的优化设计

提出采用正则有符号数字量（CSD）编码技术实现FIR滤波器。首先分析了FIR数字滤波器理论及常用设计方法的不足,然后介绍了二进制数的CSD编码技术及其特点,给出了其于CSD编码的定点常系数FIR滤波器设计过程,使用VHDI,语言实现了该常系数滤波器的行为描述。最后在Max＋PlusⅡ环境下进行实验仿真和验证,与DA和2C编码算法比较结果表明,用CSD编码技术实现的滤波器可以有效提高运算速度并降低FPGA芯片的面积占用。     

Constant Number Serial Pipeline Multipliers

The pipeline form of the serial/parallel multiplier for constant numbers, which operates without insertion of zero words between successive data, is presented. The constant number is in Canonical Signed Digit (CSD) form and the other factor in two's complement form. The CSD form was chosen because it yields significant hardware reduction. Also, for the above data forms the Lyon's serial pipeline multiplier is examined. For these designs, a special algorithm for the multiplication of two's complement numbers with constant numbers in CSD representation was developed. The proposed serial pipeline multipliers are compared with the existing schemes from the point of hardware complexity.     

FPGA-based digit-serial CSD FIR filter for image signal format conversion

This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for the MPEG2 TM 5 (test model 5). Canonical representation of a signed digit (CSD) is a method used to reduce cost by representing a signed number using the least amount of non-zero digits, thereby reducing the number of multiply operations. As Field Programmable Gate Arrays (FPGAs) have grown in capacity, improved in performance, and decreased in cost, they are becoming a viable solution for performing computationally intensive tasks, with the ability to tackle applications formerly reserved for custom chips and programmable digital signal processing (DSP) devices. A digit-serial CSD FIR filter design is realized and practical design guidelines are provided using FPGAs. An analysis of the performance comparison of bit-serial, serial distributed arithmetic, and digit-serial CSD FIR filters on a Xilinx XC4000XL-series FPGA is described. The results show that the proposed digit-serial CSD FIR filter is compact and an efficient implementation of real-time DSP applications on FPGAs.     

A New Redundant Binary Booth Encoding for Fast $2^{n}$-Bit Multiplier Design

The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition. To reduce the number of partial products, a high-radix-modified Booth encoding algorithm is desired. However, its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary (NB) to RB number conversion. This paper proposes a new RB Booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent Booth encoded digits to directly form an RB partial product to avoid the hard multiple of high-radix Booth encoding without incurring any correction vector. The proposed method leads to lower encoding and decoding complexity than the recently proposed RB Booth encoder. Synthesis results using Artisan TSMC 0.18-$mu{hbox {m}}$ standard-cell library show that the RB multipliers designed with our proposed Booth encoding algorithm exhibit on average 14% higher speed and 17% less energy-delay product than the existing multiplication algorithms for a gamut of power-of-two word lengths from 8 to 64 b.      

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tilebased FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也町以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.     

Minimization of switching activities of partial products for designing low-power multipliers

This work presents low-power 2's complement multipliers by minimizing the switching activities of partial products using the radix-4 Booth algorithm. Before computation for two input data, the one with a smaller effective dynamic range is processed to generate Booth codes, thereby increasing the probability that the partial products become zero. By employing the dynamic-range determination unit to control input data paths, the multiplier with a column-based adder tree of compressors or counters is designed. To further reduce power consumption, the two multipliers based on row-based and hybrid-based adder trees are realized with operations on effective dynamic ranges of input data. Functional blocks of these two multipliers can preserve their previous input states for noneffective dynamic data ranges and thus, reduce the number of their switching operations. To illustrate the proposed multipliers exhibiting low-power dissipation, the theoretical analyzes of switching activities of partial products are derived. The proposed 16 /spl times/ 16-bit multiplier with the column-based adder tree conserves more than 31.2%, 19.1%, and 33.0% of power consumed by the conventional multiplier, in applications of the ADPCM audio, G.723.1 speech, and wavelet-based image coders, respectively. Furthermore, the proposed multipliers with row-based, hybrid-based adder trees reduce power consumption by over 35.3%, 25.3% and 39.6%, and 33.4%, 24.9% and 36.9%, respectively. When considering product factors of hardware areas, critical delays and power consumption, the proposed multipliers can outperform the conventional multipliers. Consequently, the multipliers proposed herein can be broadly used in various media processing to yield low-power consumption at limited hardware cost or little slowing of speed.     

A 200-MHz complex number multiplier using redundant binaryarithmetic

Modern digital communication systems rely heavily on baseband signal processing for in-phase and quadrature (I-Q) channels, and complex number processing in low-voltage CMOS has become a necessity for channel equalization, timing recovery, modulation, and demodulation. In this work, redundant binary (RB) arithmetic is applied to complex number multiplication for the first time so that an N-bit parallel complex number multiplier can be reduced to two RE multiplications (i.e., an addition of N RB partial products) corresponding to real and imaginary parts, respectively. This efficient RE encoding scheme proposed can generate RB partial products with no additional hardware and delay overheads. A prototype 8-bit complex number multiplier containing 11.5 K transistors is integrated on 1.05×1.33 mm² using 0.8 μm CMOS. The chip consumes 90 mW with 2.5 V supply when clocked at 200 MHz     

Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSE-BitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSE-BitSlice technique has been applied to the design and implementation of 12 × 12 and 42 × 42 bit real multipliers, a complex multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits.     

Design of quadruple precision multiplier architectures with SIMD single and double precision support

This paper proposes architectures for dual-mode and tri-mode dynamically configurable multiplier for quadruple precision arithmetic. The proposed dual-mode QPdDP multiplier architectures can either compute on a pair of quadruple precision (QP) operands or provide SIMD support for two-parallel (dual) sets of double precision (DP) operands. The proposed tri-mode QPdDPqSP multiplier architectures are aimed to include the four-parallel (quad) single precision (SP) along with dual-DP and a QP operand processing. For the underlying largest sub-component, the mantissa multiplier, two methods are analyzed to design the dual-mode/tri-mode architectures. One is based on the Karatsuba method, and in another a dual-mode/tri-mode Radix-4 Modified Booth (MB) multiplier is proposed. The proposed dual-mode/tri-mode MB multiplier requires few extra 2:1 MUXs as an overhead compared to a simple MB multiplier. To support dual-mode/tri-mode functioning other important sub-components of the FP multiplication are also re-designed for multi-mode support. The proposed architectures are synthesized using UMC 90 nm ASIC technology, and are compared against prior literature in terms of area, period, and a unified metric “Area (Gate Count) × Period (FO4) × Latency × Throughput (in cycles)”. The dual-mode/tri-mode FP architectures with MB mantissa multipliers shows better timings, however, those with Karatsuba mantissa multipliers acquires smaller area.     

High speed multiplier using Nikhilam Sutra algorithm of Vedic mathematics

This article presents the design of a new high-speed multiplier architecture using Nikhilam Sutra of Vedic mathematics. The proposed multiplier architecture finds out the compliment of the large operand from its nearest base to perform the multiplication. The multiplication of two large operands is reduced to the multiplication of their compliments and addition. It is more efficient when the magnitudes of both operands are more than half of their maximum values. The carry save adder in the multiplier architecture increases the speed of addition of partial products. The multiplier circuit is synthesised and simulated using Xilinx ISE 10.1 software and implemented on Spartan 2 FPGA device XC2S30-5pq208. The output parameters such as propagation delay and device utilisation are calculated from synthesis results. The performance evaluation results in terms of speed and device utilisation are compared with earlier multiplier architecture. The proposed design has speed improvements compared to multiplier architecture presented in the literature.     

Modified Booth pipelined multiplication

A pipelined modified Booth multiplication is proposed for low power, high performance DSP application. The proposed multiplication is suitable for VLSI implementation. It has a better power-performance ratio than the traditional pipelined multiplier and modified Booth multiplier     

Two port adaptor for wave digital filters based on nonredundantradix-4 arithmetic

Wave digital filters synthesised from two port adaptors are highly recursive structures and hence for high speed implementations it is essential to reduce the latency of the adaptor. This is directly related to the number of addition levels used. Nonredundant radix-4 arithmetic has already been shown to nearly halve the number of levels compared with an uncoded multiplication with much less hardware overhead than the modified Booth algorithm. Nonredundant radix-4 arithmetic is applied to the two-port adaptor. The results compare favourably with previous approaches for most coefficient wordlengths of practical interest     

A Novel Diversity-Controlled Genetic Algorithm for Rapid Optimization of Bandpass FRM FIR Digital Filters Over CSD Multiplier Coefficient Space

The conventional frequency response masking (FRM) approach is one of the most well-known techniques for the design of sharp transition band finite impulse response (FIR) digital filters. The resulting FRM digital filters permit efficient hardware implementations due to an inherently large number of zero-valued multiplier coefficients. The hardware complexity of these digital filters can further be reduced by representing the remaining (non-zero) multiplier coefficient values by using their canonical signed-digit (CSD) representations. This paper presents a novel diversity-controlled (DC) genetic algorithm (GA) for the discrete optimization of bandpass FRM FIR digital filters over the CSD multiplier coefficient space. The resulting bandpass FIR digital filters are permitted to have equal or unequal lower and upper transition bandwidths. The proposed DCGA is based on an indexed look-up table of permissible CSD multiplier coefficients such that their indices form a closed set under the genetic operations of crossover and mutation. The salient advantage of DCGA over the conventional GA lies in the external control over population diversity and parent selection, giving rise to a rapid convergence to an optimal solution. The external control is achieved through the judicious choice of a pair of DCGA optimization parameters. An empirical investigation is undertaken for choosing appropriate values for these control parameters. The convergence speed advantages of the DCGA are demonstrated through its application to the design and optimization of a pair of bandpass FRM FIR digital filters with equal or arbitrary lower and upper transition bandwidths. In both cases, an increase of about an order of magnitude in the speed of convergence is achieved as compared to the conventional GAs.