Design of FIR filters for low implementation complexity

The minimisation of the total number of power-of-two terms is considered. The number of terms per coefficient is not constrained. Arbitrary phase filters are also designed where a method is introduced for the optimal utilisation of the filter gain. The method produces much better results than other methods in the literature with low computational requirements     

Improved RNS FIR filter architectures

A new architecture for implementing finite-impulse response (FIR) filters using the residue number system (RNS) is detailed. The design is based on using a restricted modulus set, with moduli of the form 2/sup n/,2/sup n/-1, and 2/sup n/+1. This does not restrict the modulus set to the common 3 modulus set {2/sup n/-1,2/sup n/,2/sup n/+1}, but any number of pairwise relatively prime moduli of this form, for example, {5,7,17,31,32,33}. Based on a comparison with a 2's complement design, the new RNS design can offer a significant speed improvement. The gain is obtained by using a set of small moduli, selected so as to minimize critical path delay and area. An algorithmic approach is used to obtain full adder based architectures that are optimized for area and delay. The modulus set is optimum based on cost parameters for each modulus. This new architecture presents a practical approach to implementing a fast RNS FIR filter.     

高速差分FIR滤波器的设计与实现

设计了一种对高速差分信号进行FIR滤波的滤波器结构。该结构采用FPGA内部RAM构成的异步FIFO乒乓接收高速输入数据，并以分频速率输出进行实时处理。FIR滤波器用VHDL语言和原理图相结合描述，并综合到Altera公司的Stratix系列芯片。综合结果表明．该设计能够接收高速差分信号，并能稳定工作在输入时钟的分频频率下。     

基于XC2V1000型FPGA的FIR抽取滤波器的设计与实现

介绍XC2V1000型现场可编程门阵列(FPGA)的主要特性和FIR抽取滤波器的工作原理,重点阐述用XC2V1000实现FIR抽取滤波器的方法,并给出仿真波形和设计特点.     

基于FPGA的FIR数字滤波器设计与实现

简要介绍了FIR数字滤波器的结构特点和基本原理,提出基于FPGA和DSP Builder的FIR数字滤波器的基本设计流程和实现方案。在Matlab/Simulink环境下,采用DSP Builder模块搭建FIR模型,根据FDATool工具对FIR滤波器进行了设计,然后进行系统级仿真和ModelSim功能仿真,其仿真结果表明其数字滤波器的滤波效果良好。通过SignalCompiler把模型转换成VHDL语言加入到FPGA的硬件设计中,从QuartusⅡ软件中的虚拟逻辑分析工具SignalTapⅡ中得到数字滤波器实时的结果波形图,结果符合预期。     

基于DSP/BIOS的FIR数字滤波器设计与实现

用可编程DSP器件实现数字滤波,通过修改滤波器参数可方便地改变滤波器的特性。以TMS320F2812数字信号处理器为核心,将滤波器算法作为DSP/BIOS的任务来实现,可方便地实现多任务系统。详细介绍一种基于DSP/BIOS的软件开发过程,并在DSK2812平台上实现数字滤波器的开发实例,对需进行数字信号处理的多任务软件开发具有一定的参考价值。     

A study of VLSI symmetric FIR filter structures

Symmetric FIR filters, which provide linear phase, are frequently used in digital signal processing. This paper presents a study of structures which take into account the particularities of the symmetry. A novel systolic structure is proposed. An efficient design is presented for the basic module which computes(x±y)h+G and which is only specific to symmetric filters. Special applications of carry-save or signed-digit notations, and tree-type multi-operand adders are shown to significantly enhance the computational speed of symmetric FIR filters.     

基于DSP/BIOS的FIR数字滤波器设计与实现

用可编程DSP器件实现数字滤波,通过修改滤波器参数可方便地改变滤波器的特性.以TMS320F2812数字信号处理器为核心,将滤波器算法作为DSP/BIOS的任务来实现,可方便地实现多任务系统.详细介绍一种基于DSP/BIOS的软件开发过程,并在DSK2812平台上实现数字滤波器的开发实例,对需进行数字信号处理的多任务软件开发具有一定的参考价值.     

基于Matlab的FIR带通滤波器设计及DSP实现

借助Matlab的FDATOOL滤波器设计分析软件,设计了一种FIR数字带通滤波器,并对一段含噪语音信号进行滤波。利用汇编语言编程,在DSP上实现了该滤波器。实验结果表明,该数字带通滤波器精确,稳定性好,易于移植,具有很强的实用性与灵活性。     

FIR数字滤波器的FPGA实现研究

为了研究不同结构的FIR数字滤波器FPGA实现对数字多普勒接收机中FPGA器件资源消耗及其实现的滤波器的速度性能．在Xilinx ISE10．1开发平台中,采用VerilogHDL语言分别实现了FIR数字滤波器的改进的串行结构、并行结构以及DA结构。并在ModelSim仿真验证平台中仿真了实现设计。结果表明,改进串行结构的实现消耗资源少但滤波速度慢．并行结构的实现滤波速度快但消耗资源多,而DA算法的实现速度仅取决于输入数据的宽度,所以滤波速度通常较快且消耗的资源较少。     

FIR数字滤波器的FPGA实现研究

为了研究不同结构的FIR数字滤波器FPGA实现对数字多普勒接收机中FPGA器件资源消耗及其实现的滤波器的速度性能,在Xilinx ISE10.1开发平台中,采用Verilog HDL语言分别实现了FIR数字滤波器的改进的串行结构、并行结构以及DA结构,并在ModelSim仿真验证平台中仿真了实现设计.结果表明,改进串行结构的实现消耗资源少但滤波速度慢,并行结构的实现滤波速度快但消耗资源多,而DA算法的实现速度仅取决于输入数据的宽度,所以滤波速度通常较快且消耗的资源较少.     

FIR数字滤波器的设计与实现

以窗函数法设计FIR数字滤波器,利用MATLAB工具软件辅助设计和仿真,对信号进行低通滤波,并使用CCS应用软件进行仿真及调试,实现了DSP下数字低通滤波器的设计.     

Design of optimal symmetric FIR receive filters

A method for designing optimal symmetric odd-length finite impulse response digital receive filters is proposed. The filter jointly minimises the mean power of intersymbol interference and additive noise or interference under the constraint that the filter coefficients are symmetric. The method yields exactly symmetric filters with the same performance as the earlier unconstrained design but with a lower computational complexity     

64阶FIR滤波器分布式算法优化及实现

讨论了基于FPGA分布式算法的64阶FIR滤波器设计原理,并详细研究了其改进方案,最后以"全并行分布式算法+查找表分割"方式完成了FIR滤波器的仿真设计。仿真结果表明上述方案能满足64阶FIR滤波器的设计要求。     

基于DSP Builder的FIR滤波器的设计与实现

现场可编程门阵列(FPGA)器件以其灵活的可配置特性,可以很好地解决并行性和速度问题而广泛应用于数字信号领域,但使用VHDL或VerilogHDL语言进行设计的难度较大.提出了一种采用DSP Builder实现有限冲激响应滤波器的设计方案,并以一个16阶低通FIR数字滤波器的实现为例,设计并完成软硬件仿真与验证.结果表明,该方法简单易行,能满足设计要求.     

Low-power and area-efficient FIR filter implementation suitable for multiple taps

This paper describes a 32-tap finite impulse response (FIR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have implemented a 32-tap FIR filter in 0.6-/spl mu/m CMOS technology with three levels of metal. The chip that occupies 2.3/spl times/2.5 mm/sup 2/ of silicon area has an operating frequency of 20 MHz and consumes 75 mW at V/sub dd/=3.3 V.     

Envelope-constrained H2 FIR filter design

In this paper, we consider an envelope-constrained (EC)H ₂ optimal finite impulse response (FIR) filtering problem. Our aim is to design a filter such that theH ₂ norm of the filtering error transfer function is minimized subject to the constraint that the filter output with a given input to the signal system is contained or bounded by a prescribed envelope. The filter design problem is formulated as a standard optimization problem with linear matrix inequality (LMI) constraints. Furthermore, by relaxing theH ₂ norm constraint, we propose a robust ECFIR filter design algorithm based on the LMI approach.     

FIR窄带滤波器组在现代雷达中的实现和优化方法

提出了一种动目标检测滤波器组在FPGA中的设计方法,给出了FIR滤波器组的设计原则和滤波器的设计步骤,并给出一组滤波器的频响曲线,运用该滤波器对某雷达回波数据进行了处理。实现了滤波器组在FPGA中的应用,并就实现过程作出了优化。     

FIR滤波器快速实现算法的最佳设计

针对实时信号处理中长阶数FIR滤波器运算量大的特点,分析并比较了包括快速算法在内的多种实现方法的性能,提出了不同方法的选择准则,得出了频域分段滤波方法中的最佳分段长度与系数阶数的关系,显著降低了连续信号FIR滤波的运算量。并提出利用代价函数,综合考虑最佳设计中的吞吐率和处理迟延。