Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

This paper proposes an 8?×?8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8?×?8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35?μm standard CMOS process.     

2GS/s 6-bit 自校准快闪ADC

A single channel 2-GS/s 6-bit ADC with cascade resistive averaging and self foreground calibration is demonstrated in 0.18-μ m CMOS. The calibration method based on DAC trimming improves the linearity and dynamic performance further. The peak DNL and INL are measured as 0.34 and 0.22 LSB, respectively. The SNDR and SFDR have achieved 36.5 and 45.9 dB, respectively, with 1.22 MHz input signal and 2 GS/s. The proposed ADC, including on-chip track-and-hold amplifiers and clock buffers, consumes 570 mW from a single 1.8 V supply while operating at 2 GS/s.     

10-bit 10Ms/S流水线A/D转换器的设计

在现有流水线A/D转换器设计的基础上,应用电荷泵改进了MOS模拟开关的性能,运用宽带运算放大器提高了电路速度,引入底极板采样和数字校正技术来提高精度,采用动态比较器实现较低的功耗.设计实现了一个10-bit 10Ms/S流水线A/D转换器,并以TSMC 0.35 CMOS工艺的Bsim 3v3模型用HSPICE对电路的性能进行仿真验证,结果表明其各项性能均达到预期的设计要求.     

新型4-bit和5-bit宽带砷化镓单片数字移相器

在GaAs基片上实现的多级级联3dB耦合线开关反射式宽带单片数字移相器在相移精度、输入回损等关键性能上良好,但通常面积很大,而多级级联的高低通网络移相器面积较小而宽带性能较差。通过多节GaAspHEMT开关的组合改变3dB耦合线的直通端和耦合端的反射体的电长度,在6～18GHz的频率范围内实现不同的相移量。该结构只采用两级3dB耦合线结构级联,减小了芯片面积,减小了多节耦合线级联引入的寄生损耗。测试结果验证了结构的合理性：性能上与传统结构相当,但芯片面积缩小为50%～60%。     

rried out. The Lagrange multipliers are

boundary conditions. A cell structure which is independent to the nodes is used to evaluate the integrals of EFG     

一个5-bit 4 GS/s的插值型模数转换器设计

设计了一款5-bit 4 GS/s的电阻插值型模数转换器(ADC),由预放大器阵列、高速比较器和编码器模块组成。定量分析了预放大器阵列的带宽和增益对ADC性能的影响,选取了最优的预放大器阵列结构,采样保持电路则选择了分布式采样,并采用电流逻辑模(CML)的比较器和编码电路。基于TSMC 65 nm工艺下进行仿真:在4 GHz的采样频率下,输入信号为200 MHz时,有效位数(ENOB)为4.85,SNDR为30.97,系统功耗为85 m W。     

An 18-bit high performance audio Σ-△ D/A converter

A multi-bit quantized high performance sigma-delta (Σ-△) audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simpler Σ-△ modulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average (DWA) mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between digital and analog circuits,every analog component is surrounded by a guard ring,which is an innovative attempt.The 18-bit DAC with the above techniques,which is implemented in a 0.18μm mixed-signal CMOS process,occupies a core area of 1.86 mm2.The measured dynamic range (DR) and peak SNDR are 96 dB and 88 dB,respectively.     

An 18-bit high performance audio ∑-△D/A converter

A multi-bit quantized high performance sigma-delta(Σ-Δ) audio DAC is presented.Compared to its singlebit counterpart,the multi-bit quantization offers many advantages,such as simplerΣ-Δmodulator circuit,lower clock frequency and smaller spurious tones.With the data weighted average(DWA) mismatch shaping algorithm,element mismatch errors induced by multi-bit quantization can be pushed out of the signal band,hence the noise floor inside the signal band is greatly lowered.To cope with the crosstalk between ...     

24-bit音频数-模转换器

英国ＷｏｌｆｓｏｎＭｉｃｒｏｅｌｅｃｔｒｏｎｉｃｓ公司推出的ＷＭ８７２０型ＩＣ是一种２４－ｂｉｔ９６ｋＨＺ数字音频数－模转换器,适用数字电视。这种新颖的多位Σ－△转换器在结构上能降低对影响到音质的计时起伏的敏感性。它也能极大地抑制输出数－模转换器的带外噪声。动态范围：１０２ｄＢ,Ｓ／Ｎ之比是１１５ｄＢ。其它特点：串行接口端口,数字插入式滤波。24-bit音频数-模转换器@陈善海     

一个低功耗1G-samples/s,6-bit折叠插值ADC芯片设计

本文提出了一种具有高线性度的折叠,插值结构数模转换器(ADC)。与高速并行数模转换器(Flash ADC)相比较,该结构具有面积小,功耗低的特点,适用于低功耗超宽带(UWB)接收机中。本文对电路各部分进行了设计,并在SMIC 0.18μm工艺下完成了版图设计和后仿真。版图核心电路面积(不包括PAD)仅为0.45mm2,在1G samples/s采样率,输入信号为488.77MHz时,总功耗仅为57mW,有效位(ENOB)达到5.74bits。     

An I/Q channel 12-bit 120?MS/s CMOS DAC with deglitch circuits

This paper describes an I/Q channel 12bit 120?MS/s DAC with deglitch circuits. The proposed DAC implemented in a 0.35???m CMOS n-well process employs three stage 4 bit thermometer decoders and deglitch circuits to minimize glitch energy and linearity error. The measurement results show a ±1.5?LSB/±1.3?LSB of INL/DNL and 31 pV·s of glitch energy. ENOB and SFDR are measured to be 10.5 bit and 71.09?dB at sampling frequency of 120?MHz and input frequency of 1?MHz with a total power consumption of 105?mW. Linearity error between I-channel DAC and Q-channel DAC is measured to be approximately 1.5?mV, i.e. the accuracy of 13 bit.     

An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR

An 80-MS/s 14-bit pipelined analog-to-digital converter (ADC) is presented in this paper. After gain error and offset extraction from prototype measurement, the improved circuit achieves spurious free dynamic range (SFDR) of 82.9 dB and signal-to-noise-and-distortion ratio (SINAD) of 64.1 dB for a 30.5 MHz input, maintained within 6 dB performance deterioration up to 170 MHz input. Differential nonlinearity (DNL) is 0.66 LSB and integral nonlinearity (INL) is 2.5 LSB. Low-jitter clock amplifier and buffers with balanced loads are used to reduce the jitter and skew between different stages. An on-chip voltage reference generator is schemed with low impedance to reduce noise and spurs of reference signals. The ADC is fabricated in a 0.18-μm CMOS process with core area of 3.86 mm², and consumes 518 mW at 1.8 V supply.     

支援视频信号的低功耗8-bit ADC

美国国家半导体公司研制成的ADC1175型A／D转换器，支持8－bit视频信号。采样频率为20MHz。该系统产品使用+5V单电压，功耗仅有60mW。典型总谐波失真（THD）是-55dB，最大微分非线性（DNL）误差为0．75LSB，典型有效位是75bit，最大微分相位（DP）0．5度，典型微分增益（DG）为0．7％。ADC1175CUM为24脚SOP封装，而ADC1175CIMT是24脚TSSOP封装。这两种型号批量单价2.79美元。支援视频信号的低功耗8-bit　ADC     

A 12-bit 1.0/2.0 GS/s Pipeline ADC in 0.18 µm SiGe BiCMOS

A 12-bit time-interleaved 1.0/2.0 GS/s pipeline analogue–digital converter (ADC) is presented and implemented in 0.18 µm SiGe BiCMOS. Such an ADC consists of two identical channels, each of which can operate at 1 GS/s. The two same channels can be interleaved to achieve 2 GS/s speed. In one-channel ADC, four lanes of pipeline ADCs with 250 MS/s are interleaved to realise 1 GHz conversion. To avoid the timing skew-induced error among the four lanes, a dedicated T/H is adopted in one channel. A clock buffer with low jitter is presented to provide a low-voltage swing clock for the T/H by using SiGe devices. The proposed timing system generates the phases needed accurately. A single reference buffer is employed in one-channel ADC to avoid the gain mismatches among the four lanes. An analogue mux with the proposed switch chooses the mode of interleaving or non-interleaving. A trimming digital–analogue converter is employed to eliminate the gain mismatches between the two channels. The measured SNDR and SFDR for one-channel ADC @ 1 GS/s are 60 and 76 dB with Nyquist input. For the interleaved two channels @ 2 GS/s, SNDR and SFDR can achieve 58 and 61 dB with Nyquist input.     

采用环型运放的12-bit 40-MS/s采样保持电路设计实现

为了保证模数转换器转换速度和精度,本文基于0.18微米工艺,设计实现了一款应用于12-bit 40-MS/s流水线ADC前端的采样保持电路.所采用的环型结构运放,可以简化设计、且占用面积小;同时,采用绝缘体上硅工艺,可以消除栅压自举开关中开关管的衬偏效应,改善开关的线性度,提高采样保持电路的性能.采样保持电路面积是0.023平方毫米.测试结果表明：在1.5V供电电压下,采样保持电路功耗是3.5mW;在1MHz输入频率、40MHz采样频率下,该采样保持电路无杂散动态范围可以达到76.85dB,满足12-bit 40-MS/s流水线模数转换器应用需求.     

一款应用于多通道CZT探测器的12-bit 1MS/s SAR-ADC芯片

本文提出了一种应用于多通道CZT探测器低功耗、小面积、抗辐照12位1MS/s逐次逼近模数转换器芯片。为了提高SAR-ADC的精度,提出了一种新型比较器,该比较器能够实现失调电压自校准功能。同时为了减少电荷分配DAC中电容失配的问题,提出了分散式电容阵列。通过电路级和版图级技术加固,提高该SAR-ADC芯片的抗辐照能力。原型芯片采用TSMC 0.35um 2P4M CMOS工艺。电源电压为3.3V和5V,采样率是1MS/s。该SAR-ADC芯片能够实现高达67.64dB的信纳比SINAD,然而仅消耗10mWz功耗。该芯片核心面积为1180um×1080um。     

An 8-bit 208 MS/s SAR ADC in 65 nm CMOS

An 8-bit low-power 208MS/s SAR analog-to-digital converter is presented. To achieve a high-speed and low-power operation, a reused terminating capacitor switching procedure is proposed. The proposed switching procedure halves the capacitors leading to a significant power saving over the conventional one. Moreover, the proposed architecture relaxes the settling time of DAC and subsequently improves the conversion rate. The ADC has been simulated in SMIC 65 nm 1.2 V CMOS technology. At a 1.2-V supply and 208 MS/s, the ADC consumes 2.7 mW and achieves an SNDR of 49.6 dB, an SFDR of 61.0 dB with 100 MHz inputs.     

一种应用于流水线ADC的14-bit 50MS/s 采样保持电路

A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.     

一个SFDR性能超过80dB的12-bit 40MS/s流水线模数转换器

摘要：本文介绍了一个以高无杂散动态范围(SFDR)和低功耗为优化目标,不需要校正的12-bit,40MS/s流水线模数转换器(ADC)。以4.9MHz正弦输入信号测试表明,本ADC微分非线性(DNL)的最大值为0.78LSB,积分非线性(INL)的最大值为1.32LSB,信噪失真比(SNDR)为66.32dB,SFDR为83.38dB。电路采用 0.18-um 1P6M CMOS工艺实现,整体芯片面积3.1mm×2.1mm,电源电压1.8V,功耗102mW。     

10-bit TFT-LCD源驱动电路的设计

DAC和驱动Buffer是TFT-LCD源驱动电路芯片中的重要模块,决定着芯片的主要性能。文章讨论了传统的R-DAC结构及其用于10-bit TFT-LCD源驱动电路时的弊端,详细阐述了新型R-DAC+C-DAC的原理以及设计方法,并采用0.35μm 5VCMOS工艺设计和实现了该电路。Hspice仿真结果表明,所设计的DAC电路的DNL和INL分别小于0.4LSB和1.5LSB,输出电压的建立时间小于3.5μs。该新型结构DAC的面积约是传统结构面积的1/8,且能够实现10亿色(210×210×210)的全真彩显示。