文章编号:1007-0249(2012)05-0091-07

负偏置温度不稳定性引起的晶体管老化已经成为影响集成电路可靠性的重要因素.高扇入多米诺或门是高性能集成电路中常用的动态电路,而负偏置温度不稳定性降低了多米诺或门的噪声容限并增大了其传输时延.本文提出了保持器和反相器均带有补偿晶体管的多米诺或门结构,通过开启补偿电路,使电路在老化以后仍然能够保持其抗干扰能力和传输延时,有效的延长了多米诺电路的使用寿命.     

电平转换电路的NBTI老化分析与容忍设计

电平转换电路是多电压设计中重要的组成部分,用来满足不同电压域间信号的传递。基于32 nm CMOS工艺,在100 ℃下,分析了NBTI老化对传统电平转换电路的影响,并提出应对老化的方案。设计了一种改进的老化容忍的电平转换电路,限制了交叉耦合对的竞争,并采用多阈值技术平衡了功耗与时延。仿真结果表明,与原电路相比,该电路可以在更低的输入电压下正常工作。不同输入电压下,功耗和时延大幅降低。该电路具有很好的老化容忍能力。     

一种抗老化消除浮空点并自锁存的老化预测传感器

随着集成电路芯片制造工艺进入纳米阶段,电路可靠性问题变得越来越严重,以负偏置温度不稳定性效应为代表的电路老化也逐渐成为影响其性能的重要因素.基于老化预测的精确性和传感器功能的多样性,提出了一种抗老化、可编程的老化预测传感器.其中稳定性检测器部分利用反馈回路解决了浮空点问题,同时整合了锁存器部分,实现了对老化预测结果的自动锁存,从而增加了老化预测的精确度,减小了一定的面积开销.最后通过HSPICE模拟器仿真验证了该传感器的优越性,且与经典结构相比降低了约21.43％的面积开销.     

低漏电流、抑制NBTI效应的多米诺电路

NBTI导致的晶体管老化成为影响电路稳定性的主导因素,同时,降低电路的泄漏功耗是电路设计的目标之一。多米诺电路广泛应用在高性能集成电路中。本文提出了一种多米诺电路用来抑制NBTI引起的多米诺电路衰退并同时降低待机模式下的泄漏电流。在待机模式下,利用2个晶体管将标准多米诺电路的动态节点和输出节点同时上拉为电源电平,从而将保持器和输出反相器中的pMOS晶体管同时置为NBTI的恢复模式。使用全0输入向量和其中增加的一个晶体管的堆栈效应降低待机模式下多米诺电路的泄漏电流。实验表明针对NBTI效应,该方法降低了最多33%的性能衰退,并同时减少了最多79%的泄漏电流。     

电路老化中考虑路径相关性的关键门识别方法

65nm及以下工艺,负偏置温度不稳定性(NBTI)是限制电路生命周期,导致电路老化甚至失效的最主要因素。本文提出了基于NBTI的时序分析框架,在确定电路中老化敏感的潜在关键路径集合的基础上,通过考虑路径相关性确定老化敏感的关键门。本方法简单易行,在65nm工艺下对ISCAS基准电路的实验结果表明:在保障电路经10年NBTI效应仍满足相同的时序要求的前提下,本方法较同类方法能更加准确得定位关键门,且关键门的数量较少,从而可减少抗老化设计的成本。     

一款消除浮空点并自锁存的老化预测传感器

针对负偏置温度不稳定性引起的组合逻辑电路老化,提出了一款消除浮空点并自锁存的老化预测传感器。该传感器不仅可以预测组合逻辑电路老化,而且能够通过传感器内部的反馈来锁存检测结果,同时解决稳定性校验器在锁存期间的浮空点问题,其延时单元为可控型延时单元,可以控制其工作状态。使用HSPICE软件进行仿真,验证了老化预测传感器的可行性,可以适用于多种环境中且不会影响传感器性能。与同类型结构相比,该传感器的稳定性校验器能够对检测结果进行自锁存,使用的晶体管数量减少了约8%,平均功耗降低了约20%。     

一种降低电路泄漏功耗的多阈值电压方法

目前,多阈值电压方法是缓解电路泄漏功耗的有效手段之一。但是,该方法会加重负偏置温度不稳定性(NBTI)效应,导致老化效应加剧,引起时序违规。通过找到电路的潜在关键路径集合,运用协同优化算法,将关键路径集合上的门替换为低阈值电压类型,实现了一种考虑功耗约束的多阈值电压方法。基于45 nm工艺模型及ISCAS85基准电路的仿真结果表明,在一定功耗约束下,该方法的时延改善率最高可达12.97%,明显优于常规多阈值电压方法。电路的规模越大,抗泄漏功耗的效果越好。     

采用双阈值配置的抗老化N型多米诺或门

N型多米诺或门是高性能集成电路常用的动态单元,负偏置温度不稳定性(NBTI)引起的PMOS管老化问题已成为降低多米诺或门电路可靠性的主要因素之一。仿真分析表明,N型多米诺或门中各种PMOS管受NBTI的影响有明显差别。针对这种差异,提出一种双阈值配置的抗老化多米诺或门。对电路老化起关键作用的保持PMOS管和反相器PMOS管采用低阈值电压设计。仿真结果表明,在保证噪声容限和功耗的条件下,该双阈值配置PMOS管的多米诺或门在10年NBTI老化后仍有0.397%的时序余量。     

刍议集成电路老化预测与容忍

集成电路特有的制备工艺,正在不断拓展。电源电压被限缩,提升了原有的集成性能。这种情形下,集成电路关涉的多重产业,也在快速进展。然而,伴随性能渐渐完善,集成电路潜藏着的老化疑难,也在逐渐凸显。拟定好的特征尺寸缩减,各时段的负偏置温度,凸显了不稳定的总倾向[1]。为此,有必要明晰老化预测特有的多重属性,探究可用的容忍技术。     

LDMOS功率放大器的温度特性及其温补电路设计

功率放大器偏置电路中的温度补偿设计是功率放大电路设计的关键部分.本文从理论分析和仿真的角度,并通过温度试验修正,确定了LDMOS功率放大器的温度系数,给出了典型应用电路,对功率放大器设计具有一定的借鉴意义.     

GaAs capacitively coupled domino logic gate

A novel GaAs capacitively coupled domino logic (CCDL) gate is proposed. Derived from capacitor-coupled logic, this domino gate offers complex gate design capability with relatively low power dissipation and high speed, making it suitable for VLSI implementations.<>     

FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32 nm FinFET technology.     

Mixed static and domino logic on the CMOS gate forest

In a semicustom design environment with unified transistor geometries, logic circuit optimization is achieved using an efficient physical circuit implementation. In particular, the semicustom realization of domino logic is demonstrated with a standard-cell and a multiplier design which are used to support the implementation of such a dynamic logic design style on a gate forest, which has a higher n count than p count. The mixture of complementary and dynamic logic allows the designer to improve the critical-path delay and to reduce the size of the layout. The domino standard-cell architecture supports multiple-output configurations and additional internal precharge. The operation time for a mixed static/dynamic multiplier is approximately 30% higher than that of the static version based on a carry select adder. This difference mainly affects the critical delay of the sign-extension path of the parallel adder array     

Monte Carlo analysis of a low power domino gate under parameter fluctuation

Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique (DTV) in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation.     

参数浮动下低功耗多米诺门的蒙特卡罗分析

Using the multiple-parameter Monte Carlo method, the effectiveness of the dual threshold voltage technique （DTV） in low power domino logic design is analyzed. Simulation results indicate that under significant temperature and process fluctuations, DTV is still highly effective in reducing the total leakage and active power consumption for domino gates with speed loss. Also, regarding power and delay characteristics, different structure domino gates with DTV have different robustness against temperature and process fluctuation.     

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45 nm CMOS technology.     

An ECL 5000-gate gate array with 190-ps gate delay

The authors describe an ECL 5000-gate gate array for use in mainframe computers. A modified paired-gate cell is introduced to obtain a high utilization of elements and a high functionality. The appropriate selection of emitter-follower currents is performed to achieve high performance for the LSI. The basic gate delay time is 190 ps/gate at a power dissipation of 2.56 mW/gate by using advanced bipolar transistors. To examine the performance of this gate array, a 16-bit multiplier has been implemented by utilizing the automatic CAD system and mounted on a 148-pin pin-grid array package. The multiplication time is 8.3 ns.     

Hot-carrier-induced degradation of gate dielectrics grown innitrous oxide under accelerated aging

Gate oxides grown with partial and complete oxidation in N₂ O were studied in terms of hot-carrier stressing. The DC lifetime for 10% degradation in g_m had a 15×improvement over control oxides not grown in a N₂O atmosphere. Further improvement in g_m degradation was observed in oxides that received partial oxidation as compared with control oxides. This improvement is due to the incorporation of nitrogen that reduces strained Si-O bonds at the Si/SiO₂ interface, leading to lower interface state generation (ISG). Improvements were also observed in I_g-V_g characteristics, indicating a reduction of trap sites both at the Si/SiO₂ interface and in the bulk oxide. Improved gate-induced drain leakage (GIDL) characteristics as a function of hot-carrier stressing for partial N₂O oxides were observed over control oxides. However, severe drain leakage that masked GIDL was observed on pure N ₂O oxides and is a subject for further study     

An ion-implanted Schottky-barrier gate field-effect transistor

Techniques of fabricating an n-channel silicon field-effect transistor using phosphorus ion implantation and a platinum silicide Schottky-barrier gate (SB-FET) have been developed. The platinum silicide Schottky-barrier top gate is part of the contact metallization process. The phosphorus-doped channel is obtained by using a 50-keV ion-implanted predeposition and an 1100°C drive-in. A range of implantation doses and drive-in times were used to achieve various SB-FET characteristics. A threshold/pinchoff voltage range of +0.4 to -7.5 V has been obtained with typical spreads of approximately 0.1 V across the slice. A positive threshold voltage represents a SB-FET that is normally off and is turned on by a forward-biased gate. Results have been obtained for