组合导航计算机容错技术研究

基于 SINS/CNS/GNSS 组合导航计算机,提出了一种容错设计的组合导航计算机。 首先,介绍了组合导航计算机容错设计的主要目的和设计思路,提出了容错组合导航计算机结构原理;其次,基于硬件元件功耗不同,设计了不同的硬件容错方法;然后,在硬件容错方法基础上设计了 N 版本程序方法和恢复块方法,实现了软件容错;最后,从导航源利用情况和组合导航计算机可用性两个方面对设计的容错导航计算机和传统导航计算机进行比较。实际应用结果表明,相对于传统导航计算机,设计的容错组合导航计算机可以有效检测隔离故障,提高组合导航计算机的可靠性和可用性。     

数字电路VHDL代码级故障容错自动插入

在数字电路源码级进行故障容错,是电路设计师需要考虑的问题,而一个自动化的容错工具,极大的提高了设计师的工作效率。本文在某种数据格式的基础上,论述了故障容错的插入过程。     

计算机容错技术及其展望

当今世界正越来越多地依赖电子计算机,计算机在人类社会中的作用越来越大,但是它的故障所引起的后果也越来越严重。因此人们迫切需要高可靠性的计算机系统。在这种情况下,计算机容错技术日益受到计算机学术界及工业界的重视。一、计算机容错技术的基本概念 (一)容错计算计算机容错技术又称容错计算(Fault-tolerantComputing),是计算机科学技术及电子科学技术的一个分支。这里“计算”一词的含义已远远超出了“数值计算”的范围,应理解为“对信息的处理及控制”。而“容     

提高系统可靠性的有效办法容错技术

论述了可靠怀设计的重要作用及提高系统可靠性的途径和方法。介绍了容错技术的概念和主要研究内容，具体介绍了硬件、软件等资源的冗余方案，特点及对系统可靠度的改善。     

地铁计算机联锁系统软件开发中的抗干扰技术

地铁计算机联锁软件是一个具有高可靠性、高可用性、高安全性的系统软件,需要在硬件和软件上采取一系列方法来满足用户的需求。重点介绍了在计算机联锁系统中如何实现软件抗干扰的方法,并对每一种方法进行了阐述,这些方法都在实际工程中得到应用,并被证明是用软件抗干扰的有效方法,可以达到最大限度地降低干扰对系统工作的影响,确保系统软件及时发现因干扰导致的程序出错。     

容错式计算机系统的同步策略

在任何多模块的系统中，同步的问题是关系到整个系统能否按正常步序协同工作的关键，这在容错系统中显得更加突出，本文所介绍的几种典型的软硬件“同步”策略，旨在缓和系统的“同步”节奏与环境产生的瞬间干扰这对矛盾，使容错系统设计师们便于选取合适的“同步”策略，保证系统工作在更佳状态。     

关于计算机系统的可靠性技术分析

随着互联网时代的到来,计算机成为了人们日常工作生活所不可或缺的实用工具之一,在提高工作效率的同时,也在一定程度上丰富了人们日常生活内容,有效的推动了社会进步。然而,计算机系统在运行时受制于自身系统以及外部运行环境而发生运行异常或故障情形,导致其可靠性降低。文章选取了几种能够提高计算机系统可靠性的技术加以深入分析,以为各种技术的推广使用积累经验。     

关于计算机服务器系统的容错技术

随着信息技术的发展,计算机服务器系统在我国的得到了非常广泛的应用,小到中小企业,大到电力、国防、卫生等重点行业都离不开计算机服务器系统提供7*24小时不间断的工作。因此,一旦计算机服务器系统发生故障,就可能会带来巨大的经济损失。基于此,本文对计算机服务器系统的容错技术进行了探讨。     

探讨铁路信号计算机联锁控制系统容错技术

铁路信号计算机联锁控制系统在国外发展的如火如荼,给我们带来了直观的认识,需要我们认真研究,从铁路信号系统的各个方面,从工作原理、技术特点、结构体系、输入输出电路、硬件配置.同时通过各项技术制式对比并进行一系列的总结,就目前而言,HOLLIASVSI2000铁路信号系统还是非常有优势的,主要在其各项指标的衡量上.本文主要从铁路信号的容错技术进行探讨,希望通过研究和探讨能够清晰了解容错技术主要构成,以及技术的难点,如何在铁路信号中运用,以及当前遇到的部分问题以及产生问题的原因进行分析,寻找一条理论和实践关联系的途径,保证在以后实践中能够解决问题,从而确保我们铁路的安全系数.也为未来的学习者和研究者提供一点建议和前瞻性的意见.     

提高系统可靠性的有效办法容错技术

论述了可靠性设计的重要作用及提高系统可靠性的途径和方法。介绍了容错技术的概念和主要研究内容，具体介绍了硬件、软件、时间和信息等资源的冗余方案、特点及对系统可靠度的改善。     

The New Fault Tolerant Onboard Computer for Microsatellite Missions

1IntroductionWith the space technology developing,much moreCommercial-Off-The-Shelf(COTS)devices are used inmicrosatellites that are mostlylocatedin Low Earth Or-bit(LEO)[1~3].The COTS devices have relatively lowpower consumption,high processing performan…     

Programmable Control of a Chemical Reactor Using a Fault Tolerant Computer

This paper discusses the operation of a chemical reactor and particularly the need for highly reliable instrumentation and control for critical processes. It describes the use of fault tolerance for the computer control to provide a level of reliability previously unachievable with standard computer control systems. The provision of highly reliable interface equipment to the reactor itself is described and approaches are presented for solving the problem of faults in the sensors and actuators. The paper discusses a specific example chemical reactor and the benefits that are achievable using a fault tolerant control computer system.     

Nucleus Plus容错功能扩充研究

Nucleus Plus是为实时嵌入式应用而设计的一个抢先式多任务操作系统，其95％的代码使用ANSIC写成，非常便于移植并能够支持大多数类型的处理器。本文根据容错管理软件的设计思想，提出了一种Nucleus Plus实时操作系统容错功能扩充方法，并在某航天三模冗余计算机平台上进行了验证。     

A Unified Method for Analyzing Mission Reliability for Fault Tolerant Computer Systems

A reliability model is proposed and evaluated for a fault tolerant computer system which consists of multiple classes of modules and allows for degraded modes of performance. Each module of a given class has both an active and a passive hazard rate; constant hazard rates are assumed for active and dormant failures, and the given class may operate either in N Modular Redundancy (NMR: n + 1 out of 2n + 1 = N) or as a standby sparing system. The model allows for mission-phase changes at deterministic time points when the numbers of modules per class can be changed. The analysis proceeds by generalizing the notions of standby and NMR redundancy, which for N = 3 is TMR (Triple Modular Redundancy), into a concept called hybrid-degraded redundancy. The probabilistic evaluation of the unified redundancy concept is then developed to yield, for a given modular class, the joint distribution of success and the number of nonfailed modules from that class, at special times. With this information, a Markov chain analysis gives the reliability of an entire sequence of phases (mission profile).     

基于CORBA的应用级容错系统的设计与实现

CORBA是一种当前流行的基于对象技术的中间件平台，它对应用屏蔽了分布式系统的异构性。但是目前的CORBA产品大多缺乏客错机制，而客错机制是分布式应用的关键问题之一。针对已有研究的缺陷和不足，文章设计并实现了一种新颖的应用级容错CORBA系统，采用对象复制技术和热备份技术来对抗服务对象失效，并有效保证了CORBA良好的互操作性。     

The Fault-Tolerant Mechanism of the CIN01-A System

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《故障诊断与容错控制》课程的实验教学系统设计

在介绍控制学科研究生课程《故障诊断与容错控制》的主要讲授内容基础上,结合学生需求和教学经验,设计了基于磁浮实验小车的悬浮系统故障诊断和容错控制实验系统,在介绍实验系统的原理、硬件和软件结构及其具体实现基础上,结合故障诊断、容错课程教学设计了综合实践环节。     

A Multimicroprocessor System for Fault Tolerant Control of an Articulated Mechanism

A multiprocessor system consisting of three processors built for reliable control of an electrically powered leg (the OSU Monopod) is described. All computations are done in a redundant fashion by two processors. Results are then compared by a different pair of processors, and all three processors participate in the identification of the faulty processor in case of a disagreement of the two sets of results. The system is reconfigured when one of the computers fails. Comparison and fault diagnosis are done by software.     

Power Consumption of Fault Tolerant Busses

On-chip interconnects in very deep submicrometer technology are becoming more sensitive and prone to errors caused by power supply noise, crosstalk, delay variations and transient faults. Error-correcting codes (ECCs) can be employed in order to provide signal transmission with the necessary data integrity. In this paper, the impact of ECCs to encode the information on a very deep submicrometer bus on bus power consumption is analyzed. To fulfill this purpose, both the bus wires (with mutual capacitances, drivers, repeaters and receivers) and the encoding-decoding circuitry are accounted for. After a detailed analysis of power dissipation in deep submicrometer fault-tolerant busses using Hamming single ECCs, it is shown that no power saving is possible by choosing among different Hamming codes. A novel scheme, called dual rail, is then proposed. It is shown that dual rail, combined with a proper bus layout, can provide a reduction of energy consumption. In particular, it is shown how the passive elements of the bus (bottom and mutual wire capacitances), active elements of the bus (buffers) and error-correcting circuits contribute to power consumption, and how different tradeoffs can be achieved. The analysis presented in this paper has been performed considering a realistic bus structure, implemented in a standard 0.13-mum CMOS technology.