Wide-Range Varactor-Tuned Terahertz Oscillator Using Resonant Tunneling Diode

We propose a wide-range varactor-tuned terahertz oscillator using a resonant tunneling diode (RTD) and estimate the tuning range. In a slot antenna, a varactor diode is placed in parallel with an RTD and can be operated with different bias voltages. Frequency tuning is possible by changing the varactor-diode capacitance with the bias voltage. A wide frequency tuning range >200 GHz (500 to 740 GHz) is obtained with an oscillator with a 20-μm-long antenna, 1.3-μm² RTD mesa, and 16-μm² varactor-diode mesa by electromagnetic-field analysis including a varactor-diode model.     

Room-Temperature Oscillation of Resonant Tunneling Diodes close to 2 THz and Their Functions for Various Applications

Compact and coherent source is a key component for various applications of the terahertz (THz) wave. We report on our recent results of THz oscillators using resonant tunneling diodes (RTDs). To achieve high-frequency oscillation, the electron delay time of RTD was reduced with a narrow quantum well and an optimized collector spacer thickness. Conduction loss at the air bridge connecting RTD and slot antenna, which works as a resonator and a radiator, was also reduced. By these structures, a fundamental oscillation up to 1.92 THz was obtained at room temperature. Theoretical calculation shows that an oscillation over 2 THz is further expected by improved structures of RTD and antenna. Using the offset slot antenna and two-element array configuration, high output power of 0.61 mW was obtained at 620 GHz. A direct intensity modulation of RTD oscillators up to 30 GHz, which is useful for high-speed wireless data transmission, was demonstrated. By the integration of a varactor diode, wide frequency sweep of 580–700 GHz in a single device and 580–900 GHz in a four-element array were also demonstrated. This result expands possible applications of RTD oscillators.     

A 50-GHz silicon IMPATT diode oscillator and amplifier

Recent experimental observations on a silicon impact avalanche transit-time diode oscillator and amplifier CW-operated at 50 GHz are presented. 1) CW oscillation power of 100 mW was obtained at an overall efficiency of 2 percent. The oscillation frequency was continuously tunable over a 1.3-GHz range by a sliding short. 2) Phase-locking has been achieved with a maximum normalized gain-bandwidth product of 0.1. The minimum locking signal power required for a 500-MHz locking bandwidth was 20 dB below the oscillator output. 3) Electronic tuning of the oscillator frequency was demonstrated by placing a millimeter-wave varactor diode in the tuning circuit. The output frequency versus the bias voltage on the varactor diode was linear with maximum frequency deviation of 300 MHz. Frequency modulation of the oscillator by driving the varactor with a sinusoidal source was obtained at a modulation frequency of 50 MHz. 4) Stable amplification with 13-dB gain was obtained, centered at 52.885 GHz with a 3-dB bandwidth of 1 GHz. The maximum output power obtained was 16 mW. Higher gain of about 17 dB was obtained at a reduced bandwidth. The noise figure of the amplifier was 36 dB. Equivalent circuits for the oscillator and the amplifier are derived. The calculated results agree reasonably well with the experimental observations.     

基于平面肖特基二极管的太赫兹频段倍频器的研究

基于研究肖特基变容二极管的半导体层结构分析与建模,通过研究太赫兹平面肖特基势全二极管半导体材料的 物理层结构,分析二极管结构的电磁效应及其频率响应特性。研究D 频段变容二极管高效率倍频器技术,在太赫兹频段 倍频器的性能对整个接收机的性能有着至关重要的影响。要实现高频率,高功率,宽频带,高效率,低噪声太赫兹倍频 技术是太赫兹技术领域的核心研究方向之一。研究基肖特基二极管倍频器的关键技术,分析了国内外现状及发展动态。     

A technique to improve the linearization of frequency–voltage characteristic of LC-VCO

This paper presents a very low-power linearization technique to improve the linearity of frequency-voltage characteristic of LC-VCO (voltage controlled oscillator) using MOS varactor. This reduces the VCO gain (K _VCO) variation and its required value over the tuning voltage range. Low K _VCO improves noise and reference spur performances at the output of phase lock loop/frequency synthesizer (FS). Low K _VCO variation reduces FS loop stability problem. Using this VCO circuit, a fully on-chip integer-N frequency synthesizer has been fabricated in 0.18 μm epi-digital CMOS technology for 2.45 GHz ZigBee application. The measured VCO phase noise is ?115.76 and ?125.23 dBc/Hz at 1 and 3 MHz offset frequencies, respectively from 2.445 GHz carrier and the reference spur of the frequency synthesizer is ?68.62 dBc. The used supply voltage is 1.5 V.     

K波段推-推介质振荡器设计

为了满足现代通信系统对于高频率与高稳定性信号源的需求,提出一种K波段介质振荡器。该振荡器通过推-推结构将两路子振荡器合二为一,使其能够在一个电路中同时实现振荡器和倍频器。在介质谐振器的两条耦合微带线上增加变容二极管模块,通过改变变容二极管的偏置电压调整谐振器中传输信号的相位。变容二极管模块的加入能够有效降低有源器件不一致性对电路的影响,减少两个子振荡器在基频处对输出信号的干扰,同时让振荡器获得200 MHz左右的输出信号频率可调范围。测试结果表明:在输出频率为20.96 GHz时,输出功率约为-4.59 dBm,在10 kHz时达到-66.50 dBc/Hz的相位噪声,在100 kHz时达到-94.31 dBc/Hz的相位噪声,基波抑制度达到-25.42 dBc。     

A wide-range 22-GHz LC-based CMOS voltage-controlled oscillator

This work presents a novel voltage-controlled oscillator (VCO) design and simulations that combine a varactor bank with a transformer in the LC tank to achieve a high-frequency range. While the varactor bank is responsible for changing the capacitance in the LC tank, the transformer acts as a means to change the value of the inductance, hence allowing tune-ability in the two main components of the VCO. A control mechanism utilises a mixed-mode circuit consisting of comparators and a state machine. It allows efficient tuning of the VCO by controlling the capacitance and transformer in the LC tank. The VCO has a 10.75–22.43 GHz frequency range and the VCO gain, K_VCO, is kept at a low value ranging from 98.6 to 175.7 MHz/V. The simulated phase noise is ?111 dBc/Hz at 1 MHz offset from the 10.75 GHz oscillation frequency. The circuit is designed and simulated in 28 nm CMOS technology and uses a 1 V supply drawing a typical power of 14.74 mW.     

Direct optical frequency modulation and injection locking of resonant tunnel diode oscillator

Preliminary results indicate that a resonant tunnel diode (RTD) oscillator can be optically tuned, frequency modulated, and injection locked. Experiments were performed in which a 2.8 GHz RTD oscillator was frequency modulated from DC to 100 MHz and injection locked over a 150 kHz bandwidth with a laser diode via fibre optics.<>     

一种超高频RFID阅读器中的双环锁相环

采用GF 130 nm CMOS工艺,设计了一种低功耗低噪声的电荷泵型双环锁相环,该锁相环可应用于符合国际及中国标准的超高频射频识别阅读器芯片。通过对双环锁相环在带宽和工作频率上的合理设置,以及对压控振荡器中变容二极管偏置电阻及电荷泵中参考杂散的理论分析和优化设计,改进了锁相环电路功耗和噪声性能。仿真结果表明,该锁相环在输出工作频率范围为840~960 MHz时,功耗为31.21 mW,在距中心频率840.125 MHz频偏100 kHz处的相位噪声为 -108.5 dBc/Hz,频偏1 MHz处的相位噪声为 -132.3 dBc/Hz。与同类锁相环相比较,本文电路在噪声和功耗方面具有一定优势。     

A 0.5 V LC-VCO with improved varactor tuning technique for WSN

A 0.5 V LC-VCO implemented in 0.18 μm CMOS technology for wireless sensor network is described in this paper. An improved varactor tuning technique is proposed to decrease low frequency noise up-conversion and AM–FM phase noise of VCO, also it can increase Q of LC tank and reduce power consumption of VCO. For coarse tuning of VCO, it can increase the varactor control voltage variation range. For fine tuning of VCO, it can reduce the varactor nonlinearity. The measured tuning range is 4.58–5.26 GHz and power consumption is 2.2 mW. The measured phase noise is ?114 dBc/Hz at 1 MHz frequency offset from a 4.8 GHz carrier.     

Varactor Controlled Gunn Oscillator at W-Band

This paper describes the experimental circuit and measured performance of varactor tuned Gunn oscillator at W-band. The power output of 12.5 dBm has been achieved when packaged GaAs Gunn diode is used. Linear frequency excursion of 150 MHz with power variation of 1 dB has been observed when varactor was given reverse bias from 0 to 20 volts. GaAs hyperabrupt varactor is used in parallel to gunn diode at a distance of odd multiple of λg/2 in waveguide channel.     

A 1.9 GHz ADPLL with 130 reference cycles settling time in 0.18 μm CMOS technology

A fast-settling all-digital phase-locked loop (ADPLL) is presented in this paper. We propose two techniques for reducing the settling time of an ADPLL, i.e. the oscillator tuning word (OTW) presetting technique and counter-based mode switching controller (CB-MSC). In the first technique, the OTW is preset in process, voltage, and temperature (PVT) calibration mode (P-mode), which leads to the digitally controlled oscillator being initialized with a frequency closer to the target. In the second technique, the CB-MSC is used to shorten the mode switching time. A prototype 1.9 GHz ADPLL with a 13 MHz reference is implemented in 0.18 μm CMOS process. Measurements show that the proposed techniques reduce the settling time by about 33 %. The proposed ADPLL settles within 130 reference cycles and presents a phase noise of ?116 dBc/Hz@1 MHz.     

A multi-band CMOS PLL-based frequency synthesizer for DRM/DRM+/DAB systems

A wideband frequency synthesizer is designed and fabricated in a 0.18 μm CMOS technology. It is developed for DRM/DRM+/DAB systems and is based on a programmable integer-N phase-locked loop. Instead of using several synthesizers for different bands, only one synthesizer is used, which has three separated divider paths to provide quadrature 8-phase LO signals. A wideband VCO covers a frequency band from 2.0 to 2.9 GHz, generates LO signals from 32 to 72 MHz, and from 250 to 362 MHz. In cooperation with a programmable XTAL multi-divider at the PLL input and output dividers at the PLL output, the frequency step can be altered from 1 to 25 kHz. It provides an average output phase noise of ?80 dBc/Hz at 10 kHz offset, ?95 dBc/Hz at 100 kHz offset, and ?120 dBc/Hz at 1 MHz offset for all the supported channels. The output power of the LO signals is tunable from 0 dBm to +3 dBm, and the phase of quadrature signals can also be adjusted through a varactor in the output buffer. The power consumption of the frequency synthesizer is 45 mW from a 1.8 V supply.     

A voltage-controlled oscillator with an ultra-low supply voltage and its application to a fractional-N phase-locked loop

With feature size scaling, the supply voltage of digital circuits is becoming lower and lower. As a result, the supply voltage of analogue and RF circuits must also be reduced for system on chip (SoC) realisation. This article proposes an ultra-low-supply voltage-controlled oscillator (ULSVCO) and designs a sigma–delta fractional-N frequency synthesiser which adopts such ULSVCO. A mathematical phase-noise model is built here to describe the noise performance of the low-supply voltage-controlled oscillator (VCO). The substrate of the cross-coupled NMOSFETs in the proposed ULSVCO is not grounded but connected to the supply to further reduce the supply voltage. Implemented in 0.18 μm CMOS technology, the proposed ULSVCO can be operated at a supply voltage as low as 0.41 V, the central frequency is set to 1.55 GHz, the phase noise is ?116 dBc/Hz@1.0 MHz. The minimum supply voltage is decreased by about 11% after our idea is adopted and the power consumption of the ULSVCO is only 1.04 mW. With the proposed ULSVCO, we design a sigma–delta-modulator (SDM) fractional-N phase-locked loop frequency synthesiser, which has a 1.43–1.75 GHz frequency tuning range. When the loop bandwidth is set to 100 KHz, the phase noise of our PLL is ?110 dBc/Hz@1.0 MHz.     

A 2.4 GHz 6.6 mA fully differential CMOS PLL frequency synthesiser

A 2.4 GHz 6.6 mA fully differential CMOS phase-locked loop (PLL) frequency synthesiser with an on-chip capacitance-calibrated loop filter is presented. The frequency synthesiser includes a differential-tuning voltage-control oscillator (VCO) and a fully differential charge-pump (CP) to reject the common-mode noise. A combination of analogue tuning and digital tuning techniques (4-bit binary weighted capacitor array) is utilised to extend the tuning range of the VCO. A novel topology and an optimisation strategy are utilised to reduce the power consumption of the frequency divider. The capacitance in the loop filter is on-chip calibrated so that the loop dynamic characteristics are accurately controlled despite the process variation. The frequency synthesiser has been implemented in UMC 0.18 μm CMOS. The measured results show that the VCO achieves a 29% tuning range, from 2.056 to 2.758 GHz. The phase noise of the frequency synthesiser is ? 117.2 dBc/Hz at 1 MHz frequency offset from the 2.3 GHz carrier. The settling time is less than 50 μs, and the capacitance in the loop filter could be on-chip calibrated to ±3.9% precision. The whole frequency synthesiser only consumes 6.6 mA current from a 1.8 V power supply.     

A 900 MHz low power LC-VCO with improved phase noise performance

In this paper, we present the design and development of a low-power LC-VCO with improved phase noise performance by implementing a new capacitor divider varactor configuration and a 2nd order notch filter. We propose a new time-weighted approach to model the effective capacitance experienced by the oscillating signal over the oscillation period. The modeled effective capacitance is used in the calculation of the oscillation frequency, which agrees well with the simulation results. Two VCOs are designed and fabricated in TSMC 0.18 μm technology. The oscillation frequency is tunable from 759 to 910 MHz with a tuning range of 18%. At 900 MHz carrier, the measured phase noise is ?126.1 dBc/Hz at 1 MHz frequency offset with 4.5 mW power consumption.     

A low phase noise PLL using Vackar VCO and a wide-locking range tunable divider for V-band signal generation in 65-nm CMOS

This paper presents a low phase noise integer-N phase-locked loop (PLL) for V-band signal generation. To enhance the frequency stability, we use a new class of Vackar voltage-controlled oscillator (VCO) in the PLL. The Vackar VCO achieves a low phase noise performance by effectively suppressing the AM-PM conversion. To properly align the locking range with the output of the VCO, a divider with wide locking range is realized by the current-mode logic (CML) D-flip-flops with tunable load. For spur reduction, an enhanced charge-pump structure is used to reject transient current glitches. With good static and dynamic current matching achieved in the charge pump, the reference spur is suppressed down to ?50 dBc. The designed PLL is implemented in a 65 nm RFCMOS process, and the measurement demonstrates a low phase noise signal up to 17 GHz. The in-band phase noise (at 1 MHz offset) and out-band phase noise (at 50 MHz offset) are ?103.6 and ?126.8 dBc/Hz, respectively. The PLL consumes 50.7 mW and occupies a chip area of 0.9 mm².     

Current-mode phase-locked loop with constant-Q active inductor CCO and active transformer loop filter

This paper presents a current-mode phase-locked loop (PLL) with a constant-Q CMOS active inductor current-controlled oscillator (CCO) and a CMOS current-mode active-transformer loop filter. The constant-Q active inductor provides a large and swing-independent quality factor such that the phase noise of the CCO utilizing the constant-Q active inductor is comparable to that of CCO with spiral inductors. The current-mode active-transformer loop filter offers the advantage of a large and tunable inductance and low silicon consumption such that the loop bandwidth of the PLL can be made small and tunable. The PLL was designed in TSMC-0.18 μm 6-metal 1.8V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3v3 device models. The phase noise of the PLL was analyzed using Cadence’s Verilog-AMS behavioral modeling. The phase noise of the CCO with the constant-Q active inductor is ?123.1 dBc/Hz at 1 MHz frequency offset, over 10 dB better as compared with that of the CCO with conventional active inductors, and is only a few dB higher than that of the CCO with spiral inductors. The phase noise of the PLL with an active-transformer loop filter and a constant-Q CCO is ?116 dBc/Hz at 1 MHz frequency offset, nearly 20 dB lower than that of the PLL with the same active-transformer loop filter and a conventional active-inductor CCO. The lock time, power consumption, and phase noise of the PLL are 60 ns, 34 mW, and ?116 dBc/Hz at 1 MHz frequency offset, respectively. The total silicon consumption of the PLL excluding bond pads is 0.013 mm².     

Frequency measurement using the phase-controlled oscillator

This paper describes the application of the phase-controlled oscillator to precision frequency comparison in order to improve the measurement accuracy. A relation derived between the counter readings, which measure the average frequency over time T, and the power spectrum of the added phase noise forms the basis for the design of the loop in various applications: frequency comparison, optimization of the operating parameters of frequency standards by detecting the frequency shift due to an applied parameter change, and assessment of the phase jitter generated in multiplier chains. The design procedure includes a determination of the error due to drifts in the oscillator and an estimate of the response time of the loop. An example of a loop which multiplies a noisy 5.6 kHz signal by 200 is given. In determining the mean frequency of a 9.2 MHz crystal oscillator compared to a rubidium vapor frequency standard the one-second counter readings of the multiplied beat signal are found to have a standard deviation of 1.16 × 10^-11.     

A 7-GHz multiloop ring oscillator in 0.18-μm CMOS technology

A novel delay stage for ring oscillator utilizing multiloop technique is presented in this paper. Different conventional delay stages for the multiloop ring oscillators have been reviewed and analyzed in this work. By using push-pull inverter as the secondary input in its delay cell, the proposed oscillator demonstrates a frequency improvement of up to 17% when compared with conventional designs. The fabricated oscillator is measured to cover a frequency range of 6.24–7.04 GHz. Operating in 1.8-V power supply, the oscillator manifests itself a phase noise of ?107.7 dBc/Hz@10 MHz offset from a center frequency of 6.25 GHz. The proposed oscillator consumes a current of 40–51 mA from the 1.8-V supply and occupies an area of 440 μm ×  430 μm.