一种用于大面积CMOS FPA的相关双采样保持电路

提出了一种基于动态源随器的、用于CMOS焦平面阵列的新结构相关双采样保持电路,并与现有的相关双采样保持电路作了详细的比较。理论分析和模拟结果表明,这种新结构的相关双采样保持电路具有结构简单、功耗小、驱动信号源少,以及能在芯片内实现双采样等优点。     

一种高性能CMOS采样/保持电路

提出了一种高性能CMOS采样/保持电路,它采用全差分电容翻转型的主体结构有效减小了噪声和功耗。在电路设计中提出了新型栅源电压恒定的自举开关来极大减小非线性失真,并同时有效抑止输入信号的直流偏移。该采样/保持电路采用0.18μm1P-6M CMOS双阱工艺来实现,在1.8V电源电压、32MHz采样速率下,输入信号直到奈奎斯特频率时仍能达到86.88dB的无杂散动态范围(SFDR),电路的信号噪声失真比(SNDR)为73.50dB。最后进行了电路的版图编辑,并对样片进行了初步测试,测试波形表明,电路实现了采样保持的功能。     

接触式图像传感器噪声抑制方法研究

介绍了接触式图像传感器(CIS)的简要原理和存在的噪声类型,阐述了用相关双采样来消除这些噪声的机理,分析了CIS要求的驱动信号CP、SP和采样保持信号SH1、SH2之间的时序关系,并用复杂可编程逻辑器件(CPID)来产生这几个信号.分析了相关双采样电路的工作原理,在此基础上进行了实验.实验表明,用相关双采样抑制CIS中的噪声,能够得到较为满意的结果.     

数字集成电路、双极集成电路、MOS集成电路

0327835一种用于大面积CMOS FPA的相关双采样保持电路[刊,中]/张智//半导体光电.—2003.24(4).—260-263(D2)提出了一种基于动态源随器的、用于CMOS焦平面阵列的新结构相关双采样保持电路,并与现有的相关双采样保持电路作了详细的比较。理论分析和模拟     

边积分边读出低噪声红外焦平面读出电路研究

设计了一款低噪声InGaAs焦平面读出电路.提出一种新型相关双采样电路结构,可在边积分边读出模式下有效抑制积分电容(0.15 pF)的KTC噪声.电路经0.5 μn5 V Nwell CMOS工艺流片,测试结果符合设计目标,在高帧频边积分边读出模式下工作状态良好,电路噪声约1.7×10-4V,动态范围大于80 dB.     

读出电路的输出摆幅和线性范围研究

焦平面读出电路的一种常用结构是以电容跨阻抗放大器（CTIA）作为输入级，相关双采样（CDS）方式提取信号并抑制噪声，源跟随器方式输出信号。本文比较了在不同的采样开关管和源随器组合方式下，电路的输出摆幅和线性范围的变化。并通过分析不同类型的开关管和源随器的输入输出特性，指出了这种变化的原因。最后得出结论，应当根据积分电容的积分端电压的变化方式，来选择适当的开关管和源随器组合，以获得最大的输出摆幅和线性范围。     

读出电路的输出摆幅和线性范围研究

焦平面读出电路的一种常用结构是以电容跨阻抗放大器(CTIA)作为输入级，相关双采样(CDS)方式提取信号并抑制噪声，源跟随器方式输出信号。本文比较了在不同的采样开关管和源随器组合方式下，电路的输出摆幅和线性范围的变化。并通过分析不同类型的开关管和源随器的输入输出特性，指出了这种变化的原因。最后得出结论，应当根据积分电容的积分端电压的变化方式，来选择适当的开关管和源随器组合，以获得最大的输出摆幅和线性范围。     

一种具有高线性度MOS采样开关的采样保持电路

通过采样保持电路中运放的复用,提出了一种具有高线性度MOS采样开关的模数转换器前端采样保持电路结构。这种结构可以显著降低采样开关导通电阻变化引入的非线性,从而在不增加开关面积和功耗的情况下,实现了高性能的采样保持电路。基于0.13?m的标准CMOS工艺,对提出的采样保持电路进行了仿真。在采样时钟频率为100MHz,输入信号频率1MHz时,仿真结果显示,无杂散动态范围(SFDR)达到了116.6dB,总谐波失真(THD)达到了112.7dB,信号谐波噪声比（SNDR）达到103.7dB,可以满足14比特流水线ADC对采样保持电路的要求。     

基于单像元多点采样的CCD信号采集电路

为抑制电荷耦合器件(CCD)读出信号噪声并确保信号完整性,提高微弱拉曼光谱信号的信噪比和光谱准确性,采用了一种单像元多点采样的CCD信号采集新方法。分析了背照式CCD面阵传感器在线性合并(line bining)操作下的时序特点,设计了完整帧信号捕捉算法和单像元多点采样的信号采集电路,完成了采集电路的控制逻辑设计。测试实验结果表明,采用该采集方法设置任意的积分时间,均可捕捉到一帧完整的光谱信号;与常规相关双采样方法相比,其信号均方差可降低51%~63%,极大地抑制了CCD探测器噪声。应用该电路成功采集了人体血液的拉曼光谱信号。     

一种具有采样保持功能的开关电容积分器

本文提出了一种开关电容积分器结构,运用增益提高技术的折叠式共源共栅放大器实现,可应用于具有采样保持功能的电路中.基于标准的65nm CMOS 工艺,通过 HSPICE 仿真验证,结果表明,该积分器在采样相与积分相能保持相同电平,且对输入信号起到采样和保持作用,在输入信号的 VPP =1.4V 、频率为10kHz 、采样频率为6.144M Hz 条件下,电路的 T HD 为-112dB .     

New dark current suppression CMOS readout circuit with novel CDS structure for large format QWIP FPA

A new Dark Current Suppression (DCS) CMOS readout circuits for large format Quantum-Well-Infrared Photo-detector (QWIP) Focal-Plane-Array (FPA) with novel CorrelatedDouble-Sampling (CDS) structure based on dynamic source-follower are proposed, which can overcome the drawbacks of the present techniques, such as sensitive to the non-uniformity of the QWIP materials, poor readout noise features, low frame frequency, limited injection efficiency and dynamic range, etc. The dummy is adopted to realize dark current suppression, while the cascode current mirror (with current ratio of 1:10) can increase charge sensitivity and reduce integration time. Through the novel CDS structure, the output waveform is boxcar, and the frame frequency is increased. Simulation results demonstrate that, in high background sense, the proposed DCS circuit can suppress the dark current, achieve good readout performance, such as low power consumption, high charge sensitivity, high resolution, large dynamic range, and insensitive to the non-uniformity of the QWIP materials.     

A new cryogenic CMOS readout structure for infrared focal planearray

A new current readout structure for the infrared (IR) focal-plane-array (FPA), called the switch-current integration (SCI) structure, is presented in this paper. By applying the share-buffered direct-injection (SBDI) biasing technique and off focal-plane-array (off-FPA) integration capacitor structure, a high-performance readout interface circuit for the IR FPA is realized with a pixel size of 50×50 μm². Moreover, the correlated double sampling (CDS) stage and dynamic discharging output stage are utilized to improve noise and speed performance of the readout structure under low power dissipation. In experimental SCI readout chip has been designed and fabricated in 0.8-μm double-poly-double-metal (DPDM) n-well CMOS technology. The measurement results of the fabricated readout chip at 77 K with 4 and 8 V supply voltages have successfully verified both the readout function and the performance improvement. The fabricated chip has a maximum charge capacity of 1.12×10⁸ electrons, a maximum transimpedance of 1×10⁹ Ω, and an active power dissipation of 30 mW. The proposed CMOS SCI structure can be applied to various cryogenic IR FPA's     

无线传感器网络中一种能量均衡的基于连通支配集的数据收集算法

采用连通支配集来构建虚拟骨干可以减轻无线传感器网络的广播风暴问题.目前已有大量工作通过构造最小连通支配集形成网络虚拟骨干来进行高效数据收集.然而,最小连通支配集并不能有效均衡节点的能量耗费,导致网络生命周期较短.提出了一种能量均衡的基于连通支配集的分布式算法EBCDS来进行数据收集,通过选择能量水平和度均比较大的节点组成连通支配集,支配集中的节点组成一个规模不大但具有较高能量水平的网络骨干.网络中的所有数据沿骨干在较小的寻路空间中转发,能够节省节点能量,使骨干节点不会因为能量不足而过早死亡.理论分析表明,EBCDS能以O(nlogn)的消息复杂度构造连通支配集,仿真实验表明,EBCDS能有效节省节点能耗并延长网络生命周期.     

Corrugated Quantum-Well Infrared Photodetector Focal Plane Arrays

Corrugated quantum-well infrared photodetectors (C-QWIPs) have been proposed for long-wavelength infrared detection. In this work, we optimize the detector structure and produce a number of large format focal plane arrays (FPAs). Specifically, we adopt one-corrugation-per-pixel geometry to increase the active detector volume and incorporate a composite cover layer to preserve the large sidewall reflectivity, which results in a large detector quantum efficiency. We also optimize the detector material structure such as the final state energy, the doping density, and the number of quantum well periods to improve the FPA operation under the existing readout electronics. As a result, high FPA sensitivity has been achieved, and their characteristics are in agreement with the detector model. Based on this model, we perform a systematic analysis on the FPA performance with a wide range of detector and system parameters. We find that C-QWIP FPAs are capable of high-speed imaging especially for those with longer cutoff wavelengths.     

Zone-based virtual backbone formation in wireless ad hoc networks

Efficient protocol for clustering and backbone formation is one of the most important issues in wireless ad hoc networks. Connected dominating set (CDS) formation is a promising approach for constructing virtual backbone. However, finding the minimum CDS in an arbitrary graph is a NP-Hard problem. In this paper, we present a novel zone-based distributed algorithm for CDS formation in wireless ad hoc networks. In this Zone algorithm, we combine the zone and level concepts to sparsify the CDS constructed by previous well-known approaches. Therefore, this proposed algorithm can significantly reduce the CDS size. Particularly, we partition the wireless network into different zones, construct a dominating tree for each zone and connect adjacent zones by inserting additional connectors into the final CDS (at the zone borders). Our comprehensive simulation study using a custom simulator shows that this zone-based algorithm is more effective than previous approaches. The number of nodes in the CDS formed by this Zone algorithm is up to around 66% less than that constructed by others. Moreover, we also compare the performance of Zone algorithm with some recently proposed CDS formation protocols in ns2 simulator.     

Switched-Capacitor Track-and-Hold Amplifiers With Low Sensitivity to Op-Amp Imperfections

This paper describes high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stages. They use a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS amplifiers, the circuits do not need a sampled-and-held input signal for their operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THAs with earlier circuits utilizing CDS. The results verify that their operation is far more robust than that of any previously described SC amplifiers     

面阵探测器相连缺陷元识别定位

面阵探测器相连缺陷元的光电信号与正常元基本相同,因此采用现有面阵测试方法无法识别相连缺陷元.针对相连缺陷元的特点,提出了借助改变面阵探测器光电响应的方法来实现相连缺陷元的识别定位.实验结果表明,该方法使面阵探测器分为两个不同透过率探测单元,多元相连缺陷元响应电压是相对应的两个不同透过率探测单元响应电压之和的平均值.采用MATLAB软件对测试数据进行分析处理,分析结果清晰给出缺陷元诸如个数、形状和位置等详细信息.采用本方法面阵探测器相连缺陷元可以被显著识别定位.研究结果为今后的面阵探测器评测与可靠性提高提供了参考.     

Switched-capacitor track-and-hold amplifier with low sensitivity to op-amp imperfections

This paper describes a high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stage. It uses a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS THAs, the circuit does not need a sample-and-held input signal for its operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THA with earlier circuits utilizing CDS. The results verify that its operation is far more robust than that of any previously described THA.