Copper interconnection lines: SARF characterization and lifetime test

Copper thin films have been deposited onto silicon substrates by means of two different deposition techniques, resulting in metallizations with different microstructure. In particular, transmission electron microscopy (TEM) observations have shown that the two types of films are characterized by different distributions of the grain size. Lifetime and SARF (Spectral Analysis of Resistance Fluctuations) tests have been performed on lines obtained from the two metallizations in order to compare their resistance to electromigration. The results of the tests confirm those already obtained in A1 based lines; in fact, a clear correlation exists among the average grain size, the lifetime and the level of electromigration noise.     

自适应光电混合互连分流结构建模与性能分析

针对片上光电混合互连网络(hybrid optoelect ronic network-on-chip,HONoC)拥 塞控制与自适应能力差、无法实现光电联合仿真等问题,提出一种适用于可重构阵列处理器 的自适应光电混合互连分流结构,在此结构上设计了自适应分流路由算法与一种低损耗无阻 塞的5端口光路由器,并搭建了基于System verilog与Verilog的光电混合互连功能仿真与 性能统计模型。实验结果表明,在边缘节点阻塞的情况下所设计的路由算法避免拥塞能力平 均提升了17.5%,光路由器所需交叉波导与微环谐振器数量大幅减少,平均光路由器级插入 损耗仅为0.522 dB,所设计的光电混合互连性能统计模型具有支持 设计拓扑、结构和路由策 略等功能,并且可以对资源使用、功耗开销、插入损耗等性能进行统计分析。     

Modeling of optical devices for the design of multistage interconnection network systems

Guidelines of the modeling of an all-optical architecture is presented. This basic architecture is universal and flexible. It can be used as the switching building block for a number of interconnection networks. The power analysis of an all optical buffering architecture [1] that can be interfaced with such an element is discussed. The modeling analysis is given in terms of the switch model, the multistage model and the power analysis of the optical buffer. The architecture uses bistable optical devices such as Fabry-Perot etalons, SEED and S-SEED. A number of important issues remain to be addressed, such as the use of different nonlinear optical devices, synchronization, and simulation.     

Thermal characterization of planar high temperature power module packages with sintered nanosilver interconnection

Many new innovations have emerged in the power electronics industry to aid in meeting the expanded market demand. In spite of that the interest in high temperature and high power applications has fueled new developments in wide bandgap semiconductor devices which are capable of operation above 200 °C, silicon devices are still prevalent in the marketplace and offer significant power ratings at affordable prices. Researches have kept pushing the limit of the application temperature of silicon devices. The key to offering functional and reliable silicon packages that can endure higher temperatures is through innovative thermal management and packaging. Effective thermal management of packaged devices can be accomplished through materials selection, design or a combination of the two. In this paper, we outline a newly designed packaging structure and the fabrication process of a functional double-sided power module switching units utilizing LTJT sintered silver for each interface. The thermal characteristics of the power module were measured in various cooling scenarios utilizing thermal transient measurements, structure function analysis and the transient dual interface method (TDIM), techniques developed by Mentor Graphics. Significant improvement of thermal performance of the fabricated module was demonstrated. The resulting improvements in thermal resistance of the power module, thermal simulation model agreement and construction, and comparison of double sided thermal results to single sided conventions are discussed.     

Modeling and characterization of ion-implanted GaAs MESFET's

Accurate modeling of GaAs IC's requires a good fit to the device characteristics over the entire range of gate and drain voltages. However, the existing circuit simulator models suitable for circuit simulation fail in the linear region of the current-voltage characteristics. In this paper, we demonstrate that the nonuniformity of the mobility and doping profiles strongly affects the linear region and propose an analytical model taking this nonuniformity into account. We also present the characterization techniques that relate the model parameters to the device physics and the fabrication methods. Excellent agreement with experimental data is obtained and the model is implemented into our GaAs IC circuit simulator.     

Modeling and characterization of gate oxide reliability

A technique of predicting the lifetime of an oxide to different voltages, different oxide areas, and different temperatures is presented. Using the defect density model in which defects are modeled as effective oxide thinning, many reliability parameters such as yield, failure rate, and screen time/screen yield can be predicted. This modeling procedure is applicable to both wafer-level and long-term reliability tests. Process improvements including defect gettering and alternative dielectrics such as chemical-vapor-deposited oxides are evaluated in the format of defect density as a function of effective oxide thinning     

Network interconnection and gateways

Major technical issues for interconnecting computer networks that must be solved, which include selection of a protocol level at which to interconnect, addressing, routing, fragmentation, and congestion control, are discussed. Specialized gateway devices used to interconnect networks and implement any necessary internet protocols are examined. Two leading alternatives have been developed by the DARPA (Defense Advanced Research Projects Agency) Internet community (datagram internet protocol) and by the CCITT (International Telegraphy and Telephony Consultative Committee) for public data networks (concatenation of virtual circuits). The new ISO standards encompass both approaches, but providing interoperability between them is still a problem     

Modeling and characterization of CMOS-compatible high-voltage device structures

The design, implementation, and modeling of high-voltage MOS transistors in a Standard CMOS technology is described. High voltage n- and p-channel transistors, with breakdown voltages of 50 and 180 V, respectively, have been fabricated. A SPICE-compatible model for these transistors is described, and its accuracy verified by comparison with experimental results.     

NGBOSS互联技术研究

根据NGBOSS业务的规划,未来的业务支撑系统分为客户业务运营支撑系统（CBOSS）和产品业务运营支撑系统（PBOSS）,现有BOSS系统星型互联的网络架构不具备对产品全网运营模式的支撑。未来新一代的NGBOSS将采用网状网互联技术,实现各省业务支撑平台间以及与基地业务平台间的互联互通。本文介绍了NGBOSS互联的网络结构、技术框架以及系统实现的关键技术。     

不同运营商间多媒体消息业务互通关键问题

多媒体消息业务(MMS)逐渐成为运营商继短信业务后又一重要的收入增长点.不同运营商的MMS的互通有助于MMS产业快速发展,更好满足用户的通信需求.本文探讨、分析了MMS网间互联互通时,网间承载协议、媒体格式、终端支持、网间互联架构等关键问题.比较了MMSC,IWGW合设、分设,全国一点互联、分省多点互联的优缺点,在此基...     

Modeling and characterization of molding compound properties during cure

During the encapsulation of electronic components stresses are generated due to curing effects and the difference in thermal shrinkage between molding compound and die. These residual stresses add up to the stresses generated during thermal cycling and mechanical loading and may eventually lead to product failure. In this paper we focus on three commercial molding compounds and analyze in detail the increase in elastic modulus and the change in viscoelastic behaviour during cure. This was done with a special shear tool which allows to measure mechanical properties with sufficient accuracy in the liquid as well as in the solid state. The cure dependent viscoelastic material behaviour was modeled using a cure dependent shift factor and rubber modulus.The viscoelastic behaviour of the molding compounds is also shown not to be stable. During postcure the materials slowly continue to crosslink thereby systematically changing their viscoelastic behaviour. The material models presented here therefore only account for the initial curing stage and do not include postcure.     

Modeling and characterization of electromigration failures underbidirectional current stress

Electromigration reliability of different metallization systems (Al-2%Si, Al-Cu/TiW, Cu, and TiN/Al-2%Si/TiN) and structures (Al-via and W-plug) under bidirectional current stress has been studied in a wide frequency range (from mHz to 200 MHz). The experimental results show that at low frequency, the damage healing factor and lifetime under ac stress increases with frequency. At very high-frequency regions, the pure ac lifetime was found to be determined by the thermal process (caused by asymmetrical geometry, etc.) instead of electromigration. All the observations are in agreement with an average current model     

Modeling and characterization of SIPOS emitter and quasi-SISemitter bipolar transistors

SIPOS (semi-insulating polycrystalline Si) emitter bipolar transistors have been fabricated with a common-emitter current gain of 8000 and a figure of merit (gain divided by intrinsic base sheet resistance) of 200 (kΩ/sq)^-1. The high gain is attributed to a relatively low interface recombination velocity of the emitter contact, as measured by photo-induced microwave reflectometry. The cutoff frequency is measured to be 250 MHz, the low value attributed to a large emitter contact resistance of the SIPOS emitter. The authors suggest that a new figure of merit-transconductance divided by emitter resistance-should be considered for the comparison of the high-frequency performances of high emitter efficiency bipolar transistors. A quasi-SIS semiconductor-insulator-semiconductor emitter bipolar with a poly-Si emitter and undoped SIPOS as an interfacial layer was also fabricated. By incorporating a field-enhancement factor in the SIPOS, the behavior of this transistor is successfully explained by a SIS emitter model. The ideality factor ratio in the Gummel plot is attributed to the different barrier heights of electrons and holes at the SiO₂/n-Si interface     

Public-key cryptography and open systems interconnection

The role of public-key cryptography in open systems interconnection (OSI) is discussed. A short tutorial introduction to public-key cryptography is followed by a discussion of how security fits into the OSI architecture, and what standards are being developed in this area. The use being made of public-key cryptography in the network layer and in the message handling system and directory application is also discussed     

Modeling of noninvasive microwave characterization of breast tumors

This paper describes an approach for the noninvasive microwave characterization of tumors in breast tissue. Tumors are modeled as lossy dielectric targets. Their complex natural resonances (CNR) can be extracted from the time-domain response and correlated with diagnostically useful properties. Finite-difference time-domain simulation is used to obtain the time-domain response from a tumor with a short electromagnetic pulse as an input. The normal breast tissue and tumor are modeled as dispersive media using the Debye model and CNRs are extracted using Prony's method. It is shown that the locations of the dominant CNRs are separated in the complex frequency plane as functions of the tumor dielectric properties. The technique has potential as a diagnostic tool to characterize breast lesions in conjunction with other imaging modalities such as ultrasound for detection.     

Description and evaluation of the FAST-Net smart pixel-basedoptical interconnection prototype

The design, packaging approach, and experimental evaluation of the free-space accelerator for switching terabit networks (FAST-Net) smart-pixel-based optical interconnection prototype are described. FAST-Net is a high-throughput data-switching concept that uses a reflective optical system to globally interconnect a multichip array of smart pixel devices. The three-dimensional optical system links each chip directly to every other with a dedicated bidirectional parallel data path. in the experiments, several prototype smart-pixel devices were packaged on a common multichip module (MCM) with interchip registration accuracies of 5-10 μm. The smart-pixel arrays (SPAs) consist of clusters of oxide-confined vertical-cavity surface-emitting lasers and photodetectors that are solder bump-bonded to Si integrated circuits. The optoelectronic elements are arranged within each cluster on a checkerboard pattern with 125-μm pitch. The experimental global optical interconnection module consists of a mirror and lens array that are precisely aligned to achieve the required interchip parallel connections between up to 16 SPAs. Five prototype SPAs were placed on the MCM to allow the evaluation of a variety of interchip links. Measurements verified the global link pattern across several devices on the MCM with high optical resolution and registration. No crosstalk between adjacent channels was observed after alignment. The I/O density and efficiency results suggest that a multi-terabit switch module that incorporates global optical interconnection to overcome conventional interconnection bottlenecks is feasible