Incorporating I DDQ Testing with BIST for Improved Coverage: An Experimental Study

In this paper we present an experimental study on the effectivenessof incorporating at-speed I _DDQ testing with traditionalBIST for improved test coverage. The high speed I _DDQtesting is conducted using the differential built-in on-chip current sensor(BICS) that we have recently developed. Two test chips were designed andfabricated implementing a CMOS version of the 74181 ALU chip. In copies ofthis circuit we included the capability of activating 45 differentrealistic CMOS faults: inter- and intra-layer shorts andopens. We examine the fault coverage of both Boolean (voltage) testing andI _DDQ testing for these realistic faults. An interestingfinding of our study is that I _DDQ testing also detectedseveral of the open faults. Moreover, these include precisely those openfaults for which two pattern voltage tests can get invalidated because oftransient switching states. Our results show that combining both Boolean andcurrent testing does enhance test coverage in a BIST environment.     

Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids

Quiescent Signal Analysis (QSA) is a novel electrical-test-based diagnostic technique that uses I _DDQ measurements made at multiple chip supply pads as a means of locating shorting defects in the layout. The use of multiple supply pads reduces the adverse effects of leakage current by scaling the total leakage current over multiple measurements. In previous work, a resistance model for QSA was developed and demonstrated on a small circuit. In this paper, the weaknesses of the original QSA model are identified, in the context of a production power grid (PPG) and probe card model, and a new model is described. The new QSA algorithm is developed from the analysis of I _DDQ contour plots. A family of hyperbola curves is shown to be a good fit to the contour curves. The parameters to the hyperbola equations are derived with the help of inserted calibration transistors. Simulation experiments are used to demonstrate the prediction accuracy of the method on a PPG.     

ITA: An algorithm for I DDQ testability analysis

This paper presents the I _DDQ Testability Analysis (ITA) algorithm for the estimation of a circuit design's leakage fault testability. The algorithm is based on the calculation of the probability of applying each of a set of essential vectors to each gate in the circuit. The essential vectors for each gate represent the minimal vector set that provides maximal leakage fault coverage.ITA assumes independence of circuit net values, except in the case of reconvergent fanout. Reconvergent fanout is identified by levelizing the circuit and propagating sets of labels from the primary inputs forward through the circuit, beginning with unique labels (integers) on each primary input. ITA evaluation of reconvergent fanout points then uses a backward implication procedure to calculate the essential vector probability values for the reconvergent gate, except in the case where backward implication is not deterministic.Results of an implementation of ITA are presented for a set of benchmark circuits, including a sample of the ISCAS '85 and '89 circuits.     

An Analog Self-Test Based on Differential I DD Monitoring Supported by Differential I OUT Checking

This paper proposes a novel DFT scheme that combines two test techniques—differential power supply current (I _DD ) monitoring and differential output current (I _OUT ) checking—in a single analog self-test. The DFT scheme is aimed at fully differential analog circuits. Fault detection is provided by means of differential measurement of the on-chip parameters, such as the I _DD and I _OUT currents. Due to the differential nature of the test principle used, no reference measurement is required prior to the test, thus the fault detection exhibits a significantly reduced dependency on process parameter variations, variation of temperature during the test as well as outside interference's. Based on measurement results, the realistic tolerance band for fault detection was determined and the fault coverage, resulting from previous simulation experiments, was adjusted.     

Design and Realization of a Built-In Current Sensor for IDDQ Testing and Power Dissipation Measurement

Built-in current sensor (BICS) is known to enhance test accuracy, defect coverage of quiescent current (I_DDQ) testing method in CMOS VLSI circuits. For new deep-submicron technologies, BICSs become essential for accurate and practical I_DDQ testing. This paper presents a new BICS suitable for power dissipation measurement and I_DDQ testing. Although the BICS presented in this paper is dedicated to submicron technologies that require reduced supply voltage, it can also be used for applications and technologies requiring normal supply voltage. The proposed BICS has been extended for on-line measurement of the power dissipation using only an additional capacitor. Power dissipation measurement is important for safety-critical applications and battery-powered systems. A simple self-test approach to verify the functionality and accuracy of BICSs has also been introduced. The proposed BICS has been implemented and tested using an N-well CMOS 1.2 m technology. Practical results demonstrate that a very good measurement accuracy can be achieved.     

Construction of Time-Relaxed c-Broadcast Networks

C-broadcasting is an information dissemination task where a message, originated at any node in a network, is transmitted to all other nodes with the restriction that each node having the message can transmit it to almost c neighbors simultaneously. If the transmission time of the message is set to be one time unit, a minimal c-broadcast network (c-MBN) is a communication network in which c-broadcasting from any node can be accomplished in log _c+1 n time units, where n is the number of nodes and log _c+1 n is the fastest possible broadcast time. If networks are sparse, additional time units may be required to perform c-broadcasting. A time-relaxed c-broadcast network, denoted as (t,c)-RBN, is a network where c-broadcasting from any node can be completed in log _c+1 n+t time units. In this paper, a network compounding algorithm is proposed to construct large sparse (t,c)-RBNs by linking multiple copies of a time-relaxed network of small size using the structure of another time-relaxed network. Computational results are presented to show the effectiveness of the proposed algorithm.     

Asymptotic behavior of periodicH ∞ a posteriori filters

The asymptotic behavior of linear periodic discrete-timeH a posteriori filters is discussed in this paper. We extend existing results for time-invariantH filters to study the problems arising from periodic discrete-time systems. Based on quasi-lifting techniques, a sufficient condition for ensuring feasibility and convergence ofH a posteriori filters is given.     

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

SeparateI DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis

I _DDQ testing uses an important property of CMOS ICs that in the steady state, the current consumption is very small. Therefore, a higher steady state current is an indicator of a probable process defect. Published literature gives ample evidence that elevation in the steady state current could be caused due to a variety of reasons besides process defects. As technology moves into deep sub-micron region, the increase in various transistor leakage currents have the potential of reducing theI _DDQ effectiveness. In this article, we propose the separation of VDD and VSS supplies for signal and bias paths so that various leakage current components are measured or computed. The methodology provides means for unambiguousI _DDQ testing, better defect diagnosis, and can be used for deep sub-micronI _DDQ testing.     

H ∞ and Robust Control of 2-D Systems in FM Second Model

This paper deals with output feedback stabilization and H control problems for two-dimensional (2-D) discrete linear systems without or with parameter uncertainty. The class of systems under investigation is described by the 2-D local state space Fornasini-Marchesini second model. We aim at designing a dynamical output feedback controller to achieve asymptotic stability and H performance for the 2-D system. It is shown that the design of output feedback controller can be recast into a convex optimization problem characterized by linear matrix inequalities (LMIs). The LMI solution is further extended to solve the robust stabilization problem for 2-D systems subject to norm-bounded uncertainty. The solutions for the H control and robust stabilization are applied to two application examples: thermal process control and robust stabilization of processes in Darboux equation.     

Quietest: A methodology for selecting I DDQ test vectors

Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current (I _DDQ ) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each I _DDQ measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I _DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I _DDQ measurement for all of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.     

Low-Voltage Differentiator for VHF Filtering

In this paper a G _m -C resonator circuit is proposed which is based on a new current-mode differentiating concept, compatible with low voltage and very high frequency operation.A prototype 4th-order 200 MHz band pass filter has been fabricated using a 0.8 m CMOS process and shows a side-band rejection lower than –80 dB. This response confirms the feasibility of the proposed resonator in very-high frequency applications such as IF band pass sections of RF front-end circuits. The filter consumes less than 5.5 mW from a 2.7 V supply and the measured dynamic range is 57 dB at IM3 of 0.5%, where the active area is 0.12 mm².     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.     

LEAP: An Accurate Defect-Free IDDQ Estimator

The quiescent current (I _DDQ) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of I _DDQ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the I _DDQ test. In this work, we present a method to estimate accurately the non-defective I _DDQ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG (Automatic Test Pattern Generation) to obtain vectors having low/high defect-free I _DDQ currents.     

Replacing I DDQ Testing: With Variance Reduction

This work is part of our effort to find an alternative to I _DDQ testing. Specifically, this paper presents our variance reduction post-processing approach in order to replace I _DDQ. It describes our test procedure based on Delta I _DDQ histograms. It shows how this test procedure can help to reduce variance, optimize test resources and reduce the impact of process drifting and resolution loss caused by the expected I _DDQ growth. Another practical aspect is discussed, namely the use of the proposed test procedure in a production test. We propose a new distribution model and revisit some experimental data, which provides a better understanding of the relationship between defect and fault. The results obtained so far confirm the pertinence of our test approach and the necessity of keeping current testing alive.     

Algorithms to select I DDQ measurement points to detect bridging faults

I _DDQ measurement is a time consuming process. Thus, reducing the number of I _DDQ measurements have a great impact on the test time. Carefully selecting a few I _DDQ measurement points is therefore an important problem. This problem has been studied for detecting leakage faults but not for bridging faults. We present novel algorithms to select I _DDQ measurement points to detect bridging faults. Experimental results obtained are very encouraging. The method can also be used: by test generators to compress I _DDQ test sets; and to maximize the fault coverage when a fixed number of measurement points are given.Research supported by NSF Grant No. MIP-9102509.     

Digital Modulator with Bandpass Delta-Sigma Modulator

A digital quadrature modulator with a bandpass -modulator is presented that interpolates orthogonal input carriers by 16 and performs a digital quadrature modulation at carrier frequencies f_s/4, –f_s/4 (f_s is the sampling frequency). After quadrature modulation, the signal is converted into an analogue IF signal using a bandpass modulator and a 1-bit D/A converter. The die area of the chip is 5.2 mm² (0.13 m CMOS technology). The total power consumption is 139 mW at 1.5 V with a clock frequency of 700 MHz (D/A converter full-scale output current 11.5 mA).     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

Reducing the CMOS RAM test complexity withI DDQ and voltage testing

In this article, we outline a RAM test methodology taking into accountI _DDQ and voltage based March tests. RAM test cost forms a significantly large portion of its total production cost and is projected to increase even further for future RAM generations.I _DDQ testing can be utilized to reduce this cost. However, owing to architectural and operational constrains of RAMs, a straight forward application ofI _DDQ testing has very limited defect detection capability. These constrains are removed by creating anI _DDQ test mode in RAMs. All bridging defects in RAM matrix, including the gate oxide defects, are detected by fourI _DDQ measurements. TheI _DDQ test is then supplemented with voltage based March test to detect the defects (opens, data retention) that are not detectable usingI _DDQ technique. The combined test methodology reduces the algorithmic test complexity for a given SRAM fault model from 16n to 5n+4I _DDQ measurements.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.