Accurate modelling of leakage currents in nanometre CMOS technologies

A technique to accurately estimate the leakage power in CMOS nanometer integrated circuits (ICs) is presented. The model has similar accuracy to SPICE and represents an important improvement with respect to previous works. The model can be used for a fast and accurate estimation of the standby power dissipated by large circuits     

Edge inversion channels and surface leakage currents in high-voltage semiconductor devices

It is shown that the electric field over the surface of semiconductor devices can be sufficient to induce edge inversion channels if the bias voltage is high and the surface charge density Q _s is low. In this case, the edge region of the devices containing the p-n-p structure (e.g., that of thyristors) functions as a planar p-channel MIS transistor with a combined gate and drain and the entire medium over the surface functions as the gate insulator. The current between the source and drain of this “edge MIS transistor” is the surface leakage current of the entire device. An analytical theory describing the current-voltage characteristic in the subthreshold mode is developed. It is shown that this new mechanism controls the total leakage current of high-voltage devices if |Q _s | and temperature T are small enough (|Q _s | < 4 nC/cm², T < 270 K and |Q _s | < 58 nC/cm², T < 600 K for silicon and silicon carbide devices, respectively).     

A compact test structure for characterisation of leakage currents in sub-micron CMOS technologies

This paper presents a compact test structure for the characterisation and modelling of leakage currents in sub-micron CMOS technologies, with which all leakage components can be directly extracted automatically and input/output influence is cancelled. The test structure can also be used for measurement of intrinsic I_ddq for defect detection.     

Analysis of leakage currents and impact on off-state powerconsumption for CMOS technology in the 100-nm regime

Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications     

Analysis of a high-voltage merged p-i-n/Schottky (MPS) rectifier

A new operating mode for the merged p-i-n/Schottky (MPS) rectifier structure is analyzed. It is shown that these devices exhibit superior forward-drop and turn-off-speed characteristics. As an example, for the same forward drop, the 400-V MPS rectifier is an order of magnitude faster in switching speed when compared to a p-i-n rectifier. In addition, for equal switching speed, the MPS rectifier has much lower forward drop and leakage current.     

An efficient driving method for a high-voltage CMOS driver IC

An efficient driving method for a high-voltage CMOS driver integrated circuit (IC) is proposed. It utilises an auxiliary circuit to reduce the voltage across the data driver IC when its output stages change their status. The auxiliary circuit can reduce the power consumption and relieve the thermal problems of the driver ICs. Moreover, it has load adaptive characteristics. Power consumption was reduced by 46% at one dot on/off image pattern.     

Dc leakage currents in trichloroethylene oxides

Undoped silicon dioxide is compared to oxide in which trichloroethylene (TCE) was used during growth. The gate leakage currents in MOS transistors are examined. It is shown that a reduction in the leakage current occurs in TCE oxides. A novel measurement technique is employed to examine the gate leakage currents of the MOSFETs.     

Characterization of leakage currents in long-lifetime capacitors

The purpose of this paper is to present a new procedure that yields the material parameters characterizing leakage currents in MOS devices (generation lifetime in the depletion region τg, recombination lifetime in the bulk τr, interfacial generation velocity S) by means of the linear-sweep technique at different temperatures and at different depths of the depletion region. This characterization method is applied to long-lifetime MOS capacitors for which different contributions to the leakage current (generation in the depletion region, diffusion from the neutral bulk and interfacial generation) are of the same order of magnitude.     

LECTOR: a technique for leakage reduction in CMOS circuits

In CMOS circuits, the reduction of the threshold voltage due to voltage scaling leads to increase in subthreshold leakage current and hence static power dissipation. We propose a novel technique called LECTOR for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. In the proposed technique, we introduce two leakage control transistors (a p-type and a n-type) within the logic gate for which the gate terminal of each leakage control transistor (LCT) is controlled by the source of the other. In this arrangement, one of the LCTs is always "near its cutoff voltage" for any input combination. This increases the resistance of the path from V/sub dd/ to ground, leading to significant decrease in leakage currents. The gate-level netlist of the given circuit is first converted into a static CMOS complex gate implementation and then LCTs are introduced to obtain a leakage-controlled circuit. The significant feature of LECTOR is that it works effectively in both active and idle states of the circuit, resulting in better leakage reduction compared to other techniques. Further, the proposed technique overcomes the limitations posed by other existing methods for leakage reduction. Experimental results indicate an average leakage reduction of 79.4% for MCNC'91 benchmark circuits.     

Method of dissipating heat generated in high-voltage CMOS driver IC

A method of dissipating the heat generated in a high-voltage CMOS driver IC, which is designed for use with a flat panel display, is proposed. It utilises a charge pump circuit to reduce the voltage across the driver IC when its output stages change their status. It can reduce the power consumption and relieve the thermal problems of driver ICs.     

Radiation-induced leakage currents in n-channel Silicon-on-sapphire MOST's

This paper describes an experimental study of the source-to-drain leakage currents in silicon-on-sapphire n-channel MOS transistors before and after exposure to ionizing radiation. The leakage currents are studied as a function of device geometry and various processing parameters. The effects on the leakage currents of wet and dry gate oxidations, the transistor channel length, and optical (UV) bleaching are described. A model of hole traps in the Al2O3is proposed to explain the radiation-induced leakage currents.     

Thickness dependence of stress-induced leakage currents in siliconoxide

The thickness dependence of high-voltage stress-induced leakage currents (SILC's) has been measured in oxides with thicknesses between 5 and 11 nm. The SILC's were shown to be composed of two components: a transient component and a DC component. Both components were due to trap-assisted tunneling processes. The transient component was caused by the tunnel charging and discharging of the stress-generated traps near the two interfaces. The DC component was caused by trap-assisted tunneling completely through the oxide. The thickness, voltage, and trap density dependences of both of these components were measured. The SILC's will affect data retention in electrically erasable programmable read-only memories (EEPROM's) and the DC component was used to estimate to fundamental limitations on oxide thicknesses     

Monolithic integration of 5 V CMOS and high-voltage devices

A fully CMOS-compatible HVIC technology has been developed that features 5 V high-performance digital CMOS with high-voltage devices of more than 400 V. This technology uses only one or two masks in addition to standard p-well CMOS technology. Design optimization has been achieved to meet the needs of both CMOS and high-voltage devices. A large number of different devices are available in this technology, including bipolar transistors, lateral MOS gate power devices, and high-voltage p-channel power devices     

Controlling substrate currents in junction-isolated ICs

Substrate currents can cause a variety of difficulties ranging from improper operation to catastrophic failure. The effects of substrate currents are characterized and techniques are developed for avoiding problems. Method of optimizing layout to control substrate currents and their effects are discussed. It is shown that these currents are strongly influenced by the properties of the die-attach interface. Fault conditions that can generate destructive hole and electron current densities in the substrate are described, and IC clamp diodes, often required to control these fault conditions, are analyzed. An example gives an appreciation of what must be considered in the design of a practical IC along with the results that might be expected     

Excess leakage currents in high-voltage 4<Emphasis Type="Italic">H</Emphasis>-SiC Schottky diodes

The high-voltage 4H-SiC Schottky diodes are fabricated with a nickel barrier and a guard system in the form of “floating” planar p-n junctions. The analysis of I–V characteristics measured in a wide temperature range shows that the forward current is caused by thermionic emission; however, the current is “excessive” in the reverse direction. It is assumed that the reverse current flows locally through the points of the penetrating-dislocation outcrop to the Ni-SiC interface. The shape of reverse I–V characteristics makes it possible to conclude that the electron transport is governed by the monopolar-injection mechanism (the space-charge limited current) with participation of capture traps.     

Intrinsic leakage in deep submicron CMOS ICs-measurement-based testsolutions

The high leakage current in deep submicron, short-channel transistors can increase the stand-by power dissipation of future IC products and threaten well established quiescent current (I_DDQ)-based testing techniques. This paper reviews transistor intrinsic leakage mechanisms. Then, these well-known device properties are applied to a test application that combines I_DDQ and ICs maximum operating frequency (F_max) to establish a novel two-parameter test technique for distinguishing intrinsic and extrinsic (defect) leakages in ICs with high background leakage. Results show that I_DDQ along with F_max can be effectively used to screen defects in high performance, low V_T (transistor threshold voltage) CMOS ICs     

Impact of silicon substrates on leakage currents

Leakage currents of n⁺-p-diodes, made on four different groups of p-type silicon substrates, are investigated at temperatures between 50 and 120°C. At these temperatures, diffusion of thermally generated minority carriers from the bulk is the dominant leakage current mechanism and determines the holding time of dynamic memories. Measurements at these temperatures show that for Czochral-sky-grown wafers (CZ) with a high interstitial oxygen concentration as is used for intrinsic gettering, the leakage current densities are about 1O× higher than for CZ wafers with a low oxygen concentration or floating-zone wafers (FZ), and are about 100× higher than for p-p⁺-epitaxial substrates. Simple analytical formulas explaining these large differences will be presented. Finally a short discussion about the optimum substrate for future high-density memories will be given.     

Subthreshold drain leakage currents in MOS field-effect transistors

There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (Vtx) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage Vi, the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between Viand Vtxthe surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below Vtx. The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.