A CCII‐based wide frequency range square waveform generator

In this paper, we propose a novel current‐mode solution suitable for the square waveform generation. The designed oscillator, which utilizes only two positive second‐generation current conveyors as active blocks, six resistors and a capacitor, is based on a current differentiation, instead of voltage integration, typical of developed solutions both in voltage‐mode and in current‐mode approaches, so avoiding circuit limitations due to the node saturation effects. The proposed circuit has been designed, as an integrated solution at transistor level, in a standard CMOS technology, with low‐voltage (± 1V) and low‐power (430µW) characteristics. Simulation results have confirmed the good circuit behaviour, also for working temperature drifts, showing good linearity in a wide oscillation frequency range, which can be independently adjusted through either capacitive (in the range pF ? µF) or resistive (in the range M Ω–G Ω) external passive components. Waiting for the chip fabrication, preliminary measurements have been performed using a laboratory breadboard employing the CCII with AD844 commercial component and sample capacitors and resistors. The experimental results have shown good agreement with both simulations and theoretical expectations. Copyright © 2011 John Wiley & Sons, Ltd.     

A current‐mode 1kHz/10kHz low‐voltage integrated analogue PLL for lock‐in portable applications

We present a low‐supply voltage (2V) low‐power consumption (500W) analogue phase‐locked loop (PLL), working at two low frequencies (1 and 10kHz), to be used in an integrated lock‐in amplifier. An externally settable control bit allows the switching operation between the two different frequencies. The circuit has been designed in a standard 0.6–m CMOS technology and differs from the standard analogue PLL architectures for the current mode implementation of both the loop filter and of the oscillator. Three different locked waveforms (sinusoidal, triangular, squared) can be obtained at the PLL output. Simulation results, obtained through the use of PSPICE and using accurate transistor models, will be proposed. The pull‐in ranges are about ±250Hz around 1 and ±1.3kHz around 10kHz, with pull‐in times of about 10 and 4ms, respectively. Copyright © 2003 John Wiley & Sons, Ltd.     

A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis,equalization, and slew rate control

A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd.     

0.5‐V fractional‐order companding filters

Novel configurations of fractional‐order filter topologies, realized through the employment of the concept of companding filtering, are introduced in this paper. As a first step, the design procedure is presented in a systematic algorithmic way, while in the next step, the basic building blocks of sinh‐domain and log‐domain integrators are presented. Because of the employment of metal–oxide–semiconductor (MOS) transistors operated in the subthreshold region, the derived filter structures offer the capability for operation in an ultra‐low‐voltage environment. In addition, because of the offered resistorless realizations, the proposed topologies are reconfigurable, in the sense that the order of the filter could be chosen through appropriate bias current sources. The performance of the derived fractional‐order filters has been evaluated through simulation and comparison results using the Analog Design Environment of the Cadence software and MOS transistor parameters provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180‐nm complementary MOS (CMOS) process. Copyright © 2014 John Wiley & Sons, Ltd.     

1‐V continuous‐time equalizers for multi‐gigabit short‐haul optical fiber communications

Two new CMOS analog continuous‐time equalizers for high‐speed short‐haul optical fiber communications are presented in this paper. The proposed structures compensate the limited bandwidth‐length product of 1‐mm step‐index polymer optical fiber channels (45 MHz, 100 m) and have been designed in a standard 0.18‐µm CMOS process. The equalizers are aimed for multi‐gigabit short‐range applications, targeting up to 2 Gb/s through a 50‐m step‐index polymer optical fiber. The prototypes operate with a single supply voltage of only 1 V and overcome the severe limitations suffered by the widely used degenerated differential pair caused by the low supply voltage. Copyright © 2012 John Wiley & Sons, Ltd.     

The CCII+ and the ICCII as basic building blocks in low‐pass filter realizations

Three new grounded capacitor current mode low‐pass filters using two inverting second‐generation current conveyor (ICCII) or one double output ICCII are given. The circuits employ the minimum number of passive circuit components, namely two resistors and two capacitors. The circuits are generated from three new voltage mode low‐pass filters realized with the ICCII. A new grounded capacitor CCII+ current mode low‐pass filter is generated from one of the new voltage mode low‐pass filters employing two ICCII?. A new grounded passive component low‐pass filter with independent control on Q and using three ICCII+ is also introduced. Spice simulation results based on using the 0.5 µm CMOS model are included to support the theoretical analysis. Copyright © 2007 John Wiley & Sons, Ltd.     

Output‐capacitorless segmented low‐dropout voltage regulator with controlled pass transistors

This article presents a low quiescent current output‐capacitorless quasi‐digital complementary metal‐oxide‐semiconductor (CMOS) low‐dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade‐off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post‐simulated in HSPICE in a 0.18 µm CMOS process to supply a stable load current between 0 and 100 mA with a 40 pF on‐chip output capacitor, while consuming 4.8 μA quiescent current. The dropout voltage of the LDO is set to 200 mV for 1.8 V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively. Copyright © 2015 John Wiley & Sons, Ltd.     

Filter‐based perturbation control of low‐frequency oscillation in voltage‐mode H‐bridge DC–AC inverter

This paper presents a new additional perturbation control method for suppressing low‐frequency oscillation in voltage‐mode H‐bridge DC–AC inverter. The stability boundary of the H‐bridge inverter is investigated from its small‐signal averaged model. High input voltage and light load would cause low‐frequency oscillation in this system. To this end, a filter‐based perturbation control (FBPC) is proposed for eliminating this oscillation, by using an analog filter to extract the unexpected signal and applying it to the control loop. Theoretical results show a larger stability range of the controlled system with the proposed FBPC. The simulation and experiment results show that the proposed controller can control the low‐frequency oscillation in H‐bridge DC–AC inverter well. Copyright © 2014 John Wiley & Sons, Ltd.     

Low‐voltage low‐power CMOS receiver front‐end for gigabit short‐reach optical communications

This article presents a new CMOS receiver analog front‐end for short‐reach high‐speed optical communications, which compensates the limited product bandwidth length of 1‐mm step‐index plastic optical fiber (SI‐POF) channels (45 MHz · 100 m) and the required large‐diameter high‐capacitance Si PIN photodetector (0.8 mm–3 pF). The proposed architecture, formed by a transimpedance amplifier and a continuous‐time equalizer, has been designed in a standard 0.18‐µm CMOS process with a single supply voltage of only 1 V, targeting gigabit transmission for simple no‐return‐to‐zero modulation consuming less than 23 mW. Experimental results validate the approach for cost‐effective gigabit SI‐POF transmission. Comparative analysis with previously reported POF receivers has been carried out by introducing a useful figure of merit. Copyright © 2012 John Wiley & Sons, Ltd.     

Impact of stray inductances of the power loop on false trigger‐on in the zero‐voltage‐switching full‐bridge converter

Here, we propose an exhaustive theoretical investigation and experimental verification of the false trigger‐on phenomenon, which would lead to the interaction between the upper and lower devices during the switching transient, in the zero‐voltage‐switching (ZVS) full‐bridge converter. An equivalent model of the converter, which takes not only the parasitic capacitors of the metal–oxide–semiconductor field‐effect transistors into account but also the stray inductances of the main circuit, is presented. Based on the model, a comprehensive study of the false trigger‐on phenomenon is carried out. According to the analysis results, the stray inductances of the metal–oxide–semiconductor field‐effect transistors have negligible influence on the false trigger‐on phenomena since the soft‐switching is realized. The false trigger‐on phenomenon is induced by the stray inductances of the main circuit. Moreover, the arrangement of the switching sequence would cause significant discriminations in the false trigger‐on phenomena because of the specific working mode of the ZVS full‐bridge converter. According to the investigation results, optimization methods are presented to suppress the induced voltage. At last, the theoretical investigations are verified by tests of a ZVS full‐bridge converter. Copyright © 2016 John Wiley & Sons, Ltd.     

Ultra‐low voltage fractional‐order circuits using current mirrors

Fractional‐order blocks, including differentiators, lossy and lossless integrators as well as filters of order 1 + a (0 < a < 1), are presented in this paper. The proposed topologies offer the benefit of ultra low‐voltage operation; in addition, reduced circuit complexity is achieved compared to the corresponding companding schemes, which have been already introduced in the literature. The ultra‐low voltage operation is performed through the employment of metal oxide semiconductor transistors biased in the subthreshold region. The reduction of circuit complexity is achieved through the utilization of current mirrors as active elements for realizing the required building blocks. The performance of the proposed fractional‐order circuits has been evaluated through the Analog Design Environment of the Cadence software and the design kit provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm complementary metal oxide semiconductor process. Copyright © 2015 John Wiley & Sons, Ltd.     

A novel single‐stage AC–DC converter with quasi‐resonant zero‐voltage‐switching for high power factor and high efficient applications

A new single‐stage‐isolated ac–dc converter that can guarantee both high efficiency and high power factor is proposed. It is based on a new dc–dc topology that has prominent conversion ratio similar to that of boost topology so that it is adequate to deal with the universal ac input. In addition, since it utilizes the transformer more than others based on the general flyback topology, the size of whole power system can be reduced due to the reduced transformer. Moreover, the voltage stresses on the secondary rectifiers can be clamped to the output voltage by adopting the capacitive output filter and clamp diode, and the turn‐off loss in the main switch can be reduced by utilizing the resonance. Furthermore, since this converter operates at the boundary conduction mode, the line input current can be shaped as the waveform of a line voltage automatically and the quasi‐resonant zero‐voltage switching can be obtained. Consequently, it features higher efficiency, lower voltage stress, and smaller sized transformer than other topologies. A 100 W prototype has been built and tested as the validation of the proposed topology. Copyright © 2010 John Wiley & Sons, Ltd.     

Reduction of neutral conductor current in a three‐phase four‐wire low‐voltage distribution line

In a low‐voltage distribution line in a three‐phase four‐wire system, the neutral conductor current is increased by a current consisting mainly of the third harmonic, which has no phase rotation if the balance of the load has been removed, when harmonic generation equipment is included in the load. The increase of this neutral conductor current increases the waveform distortion of the receiving end voltage, and various kinds of waveform interference occur. To reduce the neutral conductor current, insertion of an active filter for the third harmonic wave near the load has been proposed, and a protective effect against waveform interference has also been reported. In this paper, a method for drastically reducing the neutral conductor current by using LC resonance, which is simpler than an active filter, is proposed. © 2010 Wiley Periodicals, Inc. Electr Eng Jpn, 171(4): 19–27, 2010; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20897     

A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit

A low‐jitter and low‐power dissipation delay‐locked loop (DLL) is presented. A proposed multi‐band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak‐to‐peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.     

A sub‐1 V nanopower temperature‐compensated sub‐threshold CMOS voltage reference with 0.065%/V line sensitivity

We present the design of a nanopower sub‐threshold CMOS voltage reference and the measurements performed over a set of more than 70 samples fabricated in 0.18 µm CMOS technology. The circuit provides a temperature‐compensated reference voltage of 259 mV with an extremely low line sensitivity of only 0.065% at the price of a less effective temperature compensation. The voltage reference properly works with a supply voltage down to 0.6 V and with a power dissipation of only 22.3 nW. Very similar performance has been obtained with and without the inclusion of the start‐up circuit. Copyright © 2013 John Wiley & Sons, Ltd.     

Impact of parasitics on even symmetric split‐capacitor arrays

This paper analyzes the impact of parasitic capacitances in the performance of split capacitive‐based digital‐to‐analog converter arrays and presents a procedure for the optimal sizing of these structures for given linearity specifications. It also demonstrates that parasitics are often the main responsible for the nonlinear behavior of these arrays, particularly for low‐to‐medium resolution converters. In order to validate the analysis, two versions of a complete low‐power, low‐voltage successive‐approximation register analog‐to‐digital converter (ADC), intended for a disposable multi‐channel bio‐medical monitoring system, have been fabricated in a 0.35 µm standard complementary metal‐oxide‐semiconductor technology. The only difference between these two prototypes is that in one of them, the capacitive array is surrounded by dummy capacitors, while in the other prototype is not. Hence, the former achieves better mismatch performance at the expense of increased parasitics. The experimental results demonstrate that the version without dummy capacitors obtains higher effective resolution than the ADC with dummies, the power consumption being essentially the same for both prototypes, namely: 130nW at 2kS/s from a 1‐V supply. These results are in full agreement with the analysis reported in the paper and confirm the proposed sizing procedure. Copyright © 2012 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

Low‐Voltage‐Ride‐Through Performance of an HVDC Transmission System Using Two Modular Multilevel Double‐Star Chopper‐Cells Converters

This paper presents an intensive discussion on a long‐distance high‐voltage direct‐current (HVDC) transmission system that combines two modular multilevel cascade converters based on double‐star chopper cells (MMCC‐DSCC) with DC power cables. Hereinafter, a single MMCC‐DSCC is referred to as a DSCC converter or just as a DSCC for the sake of simplicity. The HVDC transmission system is required to provide low‐voltage‐ride‐through (LVRT) capability to enhance transmission system availability. This paper proposes a new LVRT method without any direct information exchange between the two DSCC converters. The validity of the method is verified, using simulated waveforms from the software package of “PSCAD/EMTDC” and experimental waveforms from a three‐phase 200‐V, 400‐Vdc, 10‐kW, 50‐Hz downscaled HVDC system with a set of 300‐meter‐long DC power cables.     

Analysis and implementation of a fourth‐order bandpass filter for R‐wave detection of an implantable cardiac microstimulator

This paper presents an ultra‐low‐power fourth‐order bandpass operational transconductance amplifier‐C (OTA‐C) filter for an implantable cardiac microstimulator used to detect the R‐wave of intracardiac electrograms. The OTA‐C filter fabricated by TSMC 0.35‐µm complementary metal–oxide–semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low‐frequency OTA‐C filter can be realized by ultra‐low transconductance with on‐chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA‐C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra‐low transconductance, linearity, and noise, are also discussed. Measurement results show that the low‐voltage, low‐power filter has a bandwidth between 10 and 50 Hz, third inter‐modulation distortion of ?40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R‐wave. Copyright © 2012 John Wiley & Sons, Ltd.