Innovative design methodologies in quantum‐dot cellular automata

Current transistor‐based IC fabrication technology faces many trivial issues such as those of excess power dissipation, expensive fabrication and short channel effects at very low device size [1]. Quantum‐dot cellular automata (QCA)‐based digital electronics on the other hand provide scope for further development in the future by shrinking the device size. Current QCA logic circuits are based on logic synthesis using Inverters and (three or five input) Majority Gates. In this paper, a new design methodology has been described that can be used to create circuits with even greater device substrate densities than what are currently achieved in existing QCA designs. Based on the proposed methodology, a new QCA inverter is proposed. It is further tested through simulations on QCA Designer. Through the simulations, it is subsequently proved to be much more reliable and robust than the presently used common QCA inverter(s). In the second section of this paper, simple QCA circuits such as ring oscillators using odd number of inverters in daisy chains are described and designed using the proposed inverter design. Copyright © 2013 John Wiley & Sons, Ltd.     

Design of efficient QCA multiplexers

A new methodology to realize efficient multiplexers using quantum‐dot cellular automata (QCA) is presented in this paper. The novel designs here demonstrated fully exploit the intrinsic logic capabilities of the basic building block in the QCA domain: the Majority Gate. An efficient logic formulation is derived for the 4:1 multiplexing function that can be recursively applied to the realization of multiplexers with any fan‐in, by adding in the worst‐case path only one level of Majority Gate for each input doubling. A 16:1 multiplexer designed by applying the proposed recursive approach requires less than 1600 cells and consumes only 12 clock phases to complete the operation. Copyright © 2015 John Wiley & Sons, Ltd.     

Architecture for an external input into a molecular QCA circuit

A simple architecture for data input into a molecular quantum-dot cellular automata (QCA) circuit from an external CMOS circuit is proposed. A “T”-shaped interconnect, utilizing fixed-polarization cells to provide the desired polarization, is controlled via external electrodes connected to a standard CMOS input driver. The applied input signal is used to gate either the propagation of a fixed polarization, P=+1, or that of the complementary fixed polarization, P=−1, into the QCA circuit. The architecture utilizes the field-driven clocking scheme proposed in recent literature to achieve transduction between applied input voltage and a molecular configuration. The system is modelled using the coherence vector formalism with a three-state basis and simulated using the QCADesigner simulation tool.     

A comparative analysis and design of quantum‐dot cellular automata memory cell architecture

Quantum‐dot cellular automata (QCA) nanotechnology is considered as the best candidate for memory system owing to its dense packages and low power consumption. This paper analyzes the drawbacks of the previous QCA memory architectures and improves memory cell that exploits regular clock zone layout by employing two new clocking signals and a compact Read/Write circuit. The proposed layout is verified with the modified QCADesigner simulator and is analyzed by considering the noise effect. This design, occupying only a fraction of the area compared with the previous memory design, has superior performance. It is shown that the clock circuitry is very regular, helping manufacturability for physical implementation. Comparisons show that Read/Write latency of the proposed design is mitigated, the overall cell number, control cell and layout area are reduced (100%), and its performance against random charge noise is presented to be better. Copyright © 2010 John Wiley & Sons, Ltd.     

Novel quantum‐dot cellular automata implementation of flip‐flop and phase‐frequency detector based on nand‐nor‐inverter gates

CMOS technology faces fundamental challenges such as frequency and power consumption due to the impossibility of further reducing dimensions. For these reasons, researchers have been thinking replacement of this technology with other technologies such as quantum‐dot cellular automata (QCA) technology. Many studies have been done to design digital circuits using QCA technology. Phase‐frequency detector (PFD) is one of the main blocks in electrical and communication circuits. In this paper, a novel structure for PFDs in QCA technology is proposed. In the proposed design, the novel D flip‐flop (D‐FF) with reset ability is used. The D‐FF is designed by the proposed D latch which is based on nand‐nor‐inverter (NNI) and an inverter gate. This proposed D latch has 22 cells and 0.5 clock cycle latency and 0.018‐μm² area. The inverter gate of the D‐FF has output signal with high polarization level and lower area than previous inverters, and the NNI gate of the D‐FF is a universal gate. The proposed PFD has 141 cells, 0.17‐μm² occupied area, and two clock cycle latency that is smaller compared with PFD and is based on common inverter and majority gates.     

Design and simulation of modular 2n to 1 quantum‐dot cellular automata (QCA) multiplexers

In this paper a novel design of a quantum‐dot cellular automata (QCA) 2 to 1 multiplexer is presented. The QCA circuit is simulated and its operation is analyzed. A modular design and simulation methodology is developed, which can be used to design 2ⁿ to 1 QCA multiplexers using the 2 to 1 QCA multiplexer as a building block. The design methodology is formulated in order to increase the circuit stability. Copyright © 2009 John Wiley & Sons, Ltd.     

Design of novel efficient adder and subtractor for quantum‐dot cellular automata

Quantum‐dot cellular automata (QCA) is one of the new emerging technologies being investigated as an alternative to complementary metal oxide semiconductor technology. This paper proposes optimized one‐bit full adder (FA) for implementation in QCA. The fault effects at the proposed FA outputs due to the missing cell defects are analyzed, and the test vectors for detection of all faults are identified. Also, the efficient designs of one‐bit full subtractor (FS), one‐bit FA/FS and four‐bit carry flow adder (CFA) are presented using the proposed FA. These structures are designed and simulated using QCADesigner software. The proposed designs are compared with other previous works. In comparison with the best previous design, the proposed FA has 25% and 26% improvement in cells count and area, respectively, and it is faster. For the proposed FS, FA/FS and CFA, the obtained results confirm that these designs are more efficient in terms of area, cell count and delay. Therefore, the implementation of these designs may lead to the efficient use of the calculative unit in various applications, which may be used as a basic building block of a general purpose nanoprocessor. Copyright © 2014 John Wiley & Sons, Ltd.     

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates

Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd.     

多特征故障字典及其在模拟电路可测性分析中应用

提出一种新的模拟电路可测性分析模型——多特征故障字典模型。该模型首先获得输出端的阶跃响应输出波形,提取出波形的多个特征量,将所有特征量形成一特征向量,不同故障类别对应的特征向量组成一特征矩阵。然后由PSPICE软件中的Monte-Carlo分析的结果计算出阈值,在该阈值下将特征矩阵转换成整数编码表,从而计算可测性分析指标-检测率与隔离率。仿真与实测数据表明:与传统模拟电路可测性分析方法相比,提出的方法优点有:1)不需要传递函数,可以适用于复杂电路;2)仅需要一个输出测点,容易实现;3)对于容差模拟电路,同样可以取得较好的检测率与隔离率。