New SRAM design using body bias technique for low‐power and high‐speed applications

In this paper, a new SRAM cell with body‐bias actively controlled by a control circuit and word line is introduced to realize low‐power and high‐speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade‐off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%. Copyright © 2013 John Wiley & Sons, Ltd.     

Charge‐sharing read port with bitline pre‐charging and sensing scheme for low‐power SRAMs

In this paper, we present our decoupled differential read (DDR) port and bitline (BL) pre‐charging scheme. The proposed scheme allows the charge sharing between bitlines during the read operation. DDR port isolates the internal nodes, thus improves the read static noise margin and allows the subthreshold operation. BLs are not pre‐charged to full V_DD. Read port is designed such that for the read ‘1’ operation, BL shares its charge with BLB, and for read ‘0’ operation, BL is charged toward V_DD and BLB is discharged to the ground. The proposed non‐V_DD BL pre‐charging and the charge‐sharing mechanism provide substantial read power savings. Virtual power rail is used to suppress the BL leakages. A dynamic voltage level shifting pre‐amplifier is used that shifts both BLs to the middle voltage and amplifies the voltage difference. Single‐ended write driver is also presented that only conditionally charges the write BL. The proposed 10‐transistor static random access memory cell using DDR provides more than 2 times read static noise margin, ~72% read power savings, and ~40% write power savings compared with the conventional six‐transistor static random access memory. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

The proposed 10T SRAM cell design is implemented for different CNTFET parameters like pitch, number of tubes, chirality, dielectric materials, and flatband voltage to analyze its effect on various performance parameters. The channel gate width, average read, and write power increase, but leakage power, read delay, and write delay decrease with the increase in pitch of CNTFET, whereas all these parameters are directly proportional to the number of tubes. Chirality alteration shows inverse effect on threshold voltage, read delay, and write delay although other parameters are directly related to it. The performance parameters are evaluated for various dielectric materials, and HfO₂ gives the best results for low power and high-speed applications. Analysis of flatband voltage on proposed 10T SRAM is performed by keeping flatband voltage constant for n-CNTFET and varied for p-CNTFET. Extensive analysis has been done to scrutinize the sharing of powers and delay of 10T SRAM because of variations in supply voltage and temperature. The supply voltage sweeps for a range between 0.6 and 1.2 V, and range of temperature variation is considered from −27 to 127°C. The stability of the proposed SRAM cell is calculated using N-curve method to find voltage and current information. The CNTFET based 10T SRAM cell depicts that it persists supply voltage and temperature variation significantly superior than CMOS.     

Development of NbTi superconducting strands and cables for the field winding of a 200‐MW‐class high‐energy‐density superconducting generator

The NbTi superconducting strands and cables for the field winding of the 200‐MW‐class high‐energy‐density‐type superconducting generator are developed. They are composed of Cu/Cu‐10wt%Ni/Nb‐46.5wt%Ti superconducting strands and the 10‐kA (at 5 T)‐class 9‐strand compacted cables. The diameter of strands is 1.33 mm, and the 9‐strand compacted cables are 2.4 mm thick and 6.0 mm wide. In order to produce high‐current‐density NbTi strands, we made strands under controlled aging heat treatments, the total and final strains, and the strains between heat treatments, by using large‐scale extruder. Moreover, in order to produce high‐stability and low‐AC‐loss NbTi strands and cables, the matrix ratio of strands and the cross sections of strands are optimized. The current density of NbTi filaments for the four‐time‐aging manufactured 1.33‐mm‐diameter strands was J_C=3150 A/mm² at 5 T, 1150 A/mm² at 8 T. The critical current of the 9‐strand compacted cable is 10.7 kA at 5 T. The AC losses of the final compacted cables are less than 100 kW/m³ at 5 T, 5 T/s, that is, decreased to less than half of the target of the AC loss value (< at 5 T, 5 T/s). Compared with the strand (Cu ratio 1.77), the minimum quench energy (MQE) of the strand (Cu ratio>2) increased about 40% at the operation mode current of the superconducting generator. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 156(3): 24– 31, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20266     

A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

CMOS high‐precision loser‐take‐all circuit

This paper presents a new current‐mode CMOS loser‐take‐all circuit. The proposed circuit consists of a basic cell that allows implementation of a multi‐input configuration by repeating the cell for each additional input. A high‐speed feedback structure is employed to determine the minimum current among the applied inputs. The significant feature of the circuit is its high accuracy and high‐speed operation. Additionally, the input dynamic range of the circuit can be efficiently controlled via the biasing current. HSPICE simulation results are presented to verify the performance of the circuit, where under a supply voltage of 2.5 V, bias current of 100 µA, and frequency of 10 MHz, the input dynamic range increases within 0–100 µA and the corresponding error remains as low as 0.4%. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Noise‐immune dual‐rail dynamic circuit for wide fan‐in gates in asynchronous designs

Dual‐rail dynamic logic circuits can provide inverting and noninverting outputs, especially for asynchronous designs, to implement complicated gates at the cost of approximately doubling the area and power consumption. In this paper, a new dual‐rail dynamic circuit is proposed which has lower die area consumption and higher noise immunity without dramatic speed degradation for even wide fan‐in gates for asynchronous circuits. The main idea in the proposed circuit is that voltage due to the current of the pulldown network (PDN) is compared with the reference voltage to provide two complementary outputs. The reference voltage almost corresponds to the leakage current of the PDN with all transistors being off. The proposed circuit is compared with conventional dual‐rail circuits such as differential domino logic and differential cross‐coupled domino logic. Simulation results for 32‐bit‐wide OR gates designed using high‐performance 16‐nm predictive technology model demonstrate significant performance advantages such as 66% power reduction and at least 2.86× noise‐immunity improvement at the same delay compared to the differential domino circuits. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A calculation method of field current of synchronous machines at sudden short‐circuit

The mutual leakage reactance between D‐axis damper and field windings is ignored in conventional D‐axis equivalent circuits. It has been pointed out, however, that the calculated value of the field current differs considerably from the measured value if this reactance is not taken into account. This is due to the difficulty of determining the physically correct damper winding impedance value. A method of determining the equivalent circuit constants using the mutual leakage reactance has been reported previously, where the D‐axis damper winding time constant is measured from the upper and lower envelopes of field current at sudden three‐phase short‐circuit. Yet there are machines for which the upper and lower envelopes of field current are not readily established, and in this case the method is unsatisfactory. The authors describe a method to accurately identify the equivalent circuit constants taking into account the mutual leakage reactance, using a standstill test with a small‐capacity DC power supply (DC decay testing method). The field current at sudden short‐circuit can be simulated accurately using these equivalent circuit constants. The validity of the proposed method is demonstrated by implementation results on two salient‐pole synchronous machines at the same specifications (one with damper winding, the other without). Furthermore, the dependent relation between the armature leakage reactance and mutual leakage reactance, as well as its influence on the calculation of field transient currents, are made clear. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 151(3): 61–70, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20113     

A family of memristor‐based reactance‐less oscillators

In this paper, we present for the first time a family of memristor‐based reactance‐less oscillators (MRLOs). The proposed oscillators require no reactive components, that is, inductors or capacitors, rather, the ‘resistance storage’ property of memristor is exploited to generate the oscillation. Different types of MRLO family are presented, and for each type, closed form expressions are derived for the oscillation condition, oscillation frequency, and range of oscillation. Derived equations are further verified using transient circuit simulations. A comparison between different MRLO types is also discussed. In addition, detailed fabrication steps of a memristor device and experimental results for the first MRLO physical realization are presented. Copyright © 2013 John Wiley & Sons, Ltd.     

A novel analog switch for high‐precision switched‐capacitor applications

The performance of a switched‐capacitor circuit strongly depends on its analog switches. This paper introduces a new technique to design a high‐precision analog metal‐oxide‐semiconductor switch for switched‐capacitor applications. The accuracy of analog switches is a critical parameter to determine overall performance of the discrete‐time analog systems. To satisfy the accuracy requirements of the switch, a novel technique to minimize the charge injection and clock feedthrough errors by using a very simple structure is proposed. Moreover, an innovative approach to increase the OFF resistance of the switch and consequently minimizing its leakage current is presented. To evaluate the performance of the proposed switch, simulations are done in TSMC 0.18μm standard complementary metal‐oxide‐semiconductor technology with BSIM3V3 device models. The ON and OFF resistances of the switch are one of the most important factors that should be considered while investigating analog switches. The ON resistance of the proposed switch is less than 560Ω over entire input signal range which completely satisfies the tracking bandwidth requirements. In addition, since the proposed switch provides an ultrahigh OFF resistance in the range of several GΩs, the leakage current of the proposed switch is negligible. Simulation results also show that switch‐induced errors are significantly eliminated by using the proposed cancellation technique. The output error charge due to charge injection and clock feedthrough over a wide range of input signal variation is very low (less than 1.6 fC). Moreover, simulation results show that the proposed switch achieves signal to noise plus distortion ratio of 80.55 dB, effective number of bits of 13.08, total harmonic distortion of ?81.41 dB, and spurious‐free dynamic range of 87.7 dB for a 2.5‐MHz sinusoidal input of 800‐mV peak‐to‐peak amplitude at 200‐MHz sampling rate with a 1.8‐V supply voltage. Consequently, the simulation results verify that the proposed switch can significantly improve the dynamic and static performances of a switched‐capacitor circuit.     

A portable class of 3‐transistor current references with low‐power sub‐0.5 V operation

This work proposes a new class of current references based on only 3 transistors that allows sub‐0.5 V operation. The circuit consists of a 2‐transistor block that generates a proportional‐to‐absolute‐temperature or a complementary‐to‐absolute‐temperature voltage and a load transistor. The idea of a 3T current reference is validated by circuit simulations for different complementary metal‐oxide‐semiconductor technologies and by experimental measurements on a large set of test chips fabricated with a commercial 0.18 μm complementary metal‐oxide‐semiconductor process. As compared to the state‐of‐art competitors, the 3T current reference exhibits competitive performance in terms of temperature coefficient (578 ppm/°C), line sensitivity (3.9%/V), and power consumption (213 nW) and presents a reduction by a factor of 2 to 3 in terms of minimum operating voltage (0.45 V) and an improvement of 1 to 2 orders of magnitude in terms of area occupation (750 μm²). In spite of the extremely reduced silicon area, the fabricated chips exhibit low‐process sensitivity (2.7%). A digital trimming solution to significantly reduce the process sensitivity is also presented and validated by simulations.     

Analysis and design of a high‐compliance ultra‐high output resistance current mirror employing positive shunt feedback

This paper reports a novel high‐compliance, very accurate and ultra‐high output resistance current mirror. These features are achieved by employing a combination of negative and positive feedbacks in the proposed circuit. This makes the proposed current mirror unique in gathering ultra‐high output resistance, high compliance, and high accuracy ever demanded merits. The principle of operation of this structure is discussed, its main formulas are derived and its outstanding performance is verified by Cadence post‐layout simulations. Designed in the IBM 130‐nm standard CMOS process, the circuit consumes 230 × 110 µm² of silicon area. Post‐layout simulation results indicate that with a 3.3‐V power supply, output voltage compliance of 0.93V_Supply is achieved at a maximum output current of 96 μA. Moreover, an extremely ultra‐high output resistance of 320 GΩ is achieved, which is one of the highest reported values of output resistance for current mirrors implemented using regular CMOS technology. The ?3 dB upper cut‐off frequency of the proposed circuit is 100 MHz and the output/input current transfer error is 0.1%. The whole circuit, including bias circuitry, consumes 0.57 mW when delivering 96 μA to the load. Copyright © 2014 John Wiley & Sons, Ltd.     

A data aware 9T static random access memory cell for low power consumption and improved stability

Reducing the power consumption in static random access memory can significantly improve the system power efficiency, reliability, and performance. In this paper, we propose a data aware static random access memory cell to reduce the power consumption during read and write operation. The proposed cell contains nine transistors with separate read/write ports. The write operation in the proposed cell is controlled by an additional write signal instead of word line. Because of isolation of the storage nodes with bit lines, read signal‐to‐noise margin is equal to ideal hold signal‐to‐noise margin of the conventional cell. The proposed cell saves approximately more than 43% active power compared with the 6T cell and other published cells. The proposed cell gives faster write access and low leakage current compared with the conventional and other cells. About 99% standby column power reduction, with 128 cells, is observed in the proposed cell. Copyright © 2013 John Wiley & Sons, Ltd.     

Study on field demonstration of high‐sensitivity SF6 leakage detection method for gas insulated switchgear

SF6 gas is widely used in power equipment such as gas insulated switchgear or gas circuit breaker. However, its global warming potential is 23,500 times higher than that of CO₂. In consideration of environmental protection, detection of SF6 gas leakage with high sensitivity is necessary. The authors proposed an algorithm to accurately estimate the average gas temperature from the tank surface temperature for establishing a high‐sensitive SF6 slow leak detection technology. Since the gas temperature depends on the temperature of the conductor, the algorithm was characterized by estimating the gas temperature from the tank surface temperature and the load current. The relationship among the tank surface temperature, the gas temperature, and the current was preliminarily investigated by the use of the thermal fluid analysis and stored in the database. By use of this method, the fluctuation of the converted pressure in the basic examination test was suppressed to 20% as compared with that without considering the current. In addition, database was also created from the machine learning of field test result in substitution. In the field test, it was confirmed that the detection time of 0.5%/year slow leak could be detected in about 8 months by considering the load current.     

Proposal of flux‐lock‐type fault current limiter with high‐TC superconducting element

This paper proposes a new type of fault current limiter (FCL), which consists of a high‐T_C superconducting (HTS) element and two coils wound on the same core without any leakage magnetic flux. In this FCL, either the limiting impedance or the initial limiting current level can be controlled by adjusting the inductances and the winding direction of the coils. Therefore, this FCL could relax the material restrictions on high‐T_C superconducting FCL. A current‐limiting experiment by a model FCL was carried out, and the limiting performance was observed. The initial limiting current level of the model FCL was 1.7 times higher than the critical current of the HTS element, and the fault current is suppressed to 52% immediately after the short‐circuit in the test. Considering voltage–current characteristics of a high‐T_C superconductor in a computer simulation, the calculated results almost agreed with the experimental results. © 1999 Scripta Technica, Electr Eng Jpn, 127(1): 31–38, 1999     

Low‐voltage high‐performance current mirrors: Application to linear voltage‐to‐current converter

Current mirror is one of the basic building blocks of analog VLSI systems. For high‐performance analog circuit applications, the accuracy and bandwidth are the most important parameters to determine the performance of the current mirror. This paper presents an efficient implementation of a CMOS current mirror suitable for low‐voltage applications. This circuit combines a shunt input feedback, a regulated cascade output and a differential amplifier to achieve low input resistance, high accuracy and high output resistance. A comparison of several architectures of this scheme based on different architectures of the amplifier is presented. The comparison includes: input impedance, output impedance, accuracy, frequency response and settling time response. These circuits are validated with simulation in 0.18µm CMOS TSMC of MOSIS. In this paper, a linear voltage to current converter, based on the adapted current mirror, is proposed. Its static and dynamic behaviour is presented and validated with the same technology. Copyright © 2009 John Wiley & Sons, Ltd.     

Preliminary results from an analog implementation of first‐order TDCNN dynamics

This work falls into the category of linear cellular neural network (CNN) implementations. We detail the first investigative attempt on the CMOS analog VLSI implementation of a recently proposed network formalism, which introduces time‐derivative ‘diffusion’ between CNN cells for nonseparable spatiotemporal filtering applications—the temporal‐derivative CNNs (TDCNNs). The reported circuit consists of an array of Gm‐C filters arranged in a regular pattern across space. We show that the state–space coupling between the Gm‐C‐based array elements realizes stable and linear first‐order (temporal) TDCNN dynamics. The implementation is based on linearized operational transconductance amplifiers and Class‐AB current mirrors. Measured results from the investigative prototype chip that confirms the stability and linearity of the realized TDCNN are provided. The prototype chip has been built in the AMS 0.35 µm CMOS technology and occupies a total area of 12.6 mm sq, while consuming 1.2 µW per processing cell. Copyright © 2010 John Wiley & Sons, Ltd.     

A 0.75‐V, 4‐μW, 15‐ppm/°C, 190 °C temperature range,voltage reference

A low‐voltage, low‐power, low‐area, wide‐temperature‐range CMOS voltage reference is presented. The proposed reference circuit achieves a measured temperature drift of 15 ppm/°C for an extremely wide temperature range of 190 °C (?60 to 130 °C) while consuming only 4 μW at 0.75 V. It performs a high‐order curvature correction of the reference voltage while consisting of only CMOS transistors operating in subthreshold and polysilicon resistors, without utilizing any diodes or external components such as compensating capacitors. A trade‐off of this circuit topology, in its current form, is the high line sensitivity. The design was fabricated using TowerJazz semiconductor's 0.18‐µm standard CMOS technology and occupies an area of 0.039 mm². The proposed reference circuit is suitable for high‐precision, low‐energy‐budget applications, such as mobile systems, wearable electronics, and energy harvesting systems. Copyright © 2015 John Wiley & Sons, Ltd.