A data aware 9T static random access memory cell for low power consumption and improved stability

Reducing the power consumption in static random access memory can significantly improve the system power efficiency, reliability, and performance. In this paper, we propose a data aware static random access memory cell to reduce the power consumption during read and write operation. The proposed cell contains nine transistors with separate read/write ports. The write operation in the proposed cell is controlled by an additional write signal instead of word line. Because of isolation of the storage nodes with bit lines, read signal‐to‐noise margin is equal to ideal hold signal‐to‐noise margin of the conventional cell. The proposed cell saves approximately more than 43% active power compared with the 6T cell and other published cells. The proposed cell gives faster write access and low leakage current compared with the conventional and other cells. About 99% standby column power reduction, with 128 cells, is observed in the proposed cell. Copyright © 2013 John Wiley & Sons, Ltd.     

A novel low‐power receiver topology for RF and microwave applications

A novel low‐power receiver topology for radio‐frequency and microwave applications is presented. The proposed solution exploits a simple connection between the low‐noise amplifier and the subsequent mixer, which is realized by means of a high‐value resistor and a current mirror, achieving low noise and high linearity performance with an extremely low power consumption. The criteria for its optimal design are derived in order to accomplish the main trade‐offs among noise figure (NF), linearity, and current consumption performance. As a case of study, the new topology has been designed in the case of I/Q direct conversion receiver for IEEE 802.15.4 standard (ZigBee) applications at 2.45 GHz. The receiver exhibits a NF of 8.7 dB, 50Ω input impedance, a voltage gain of 26 dB, an input‐referred third‐order intercept point of ?13 dBm, and a power consumption of 8.6 mW, which represent one of the best performance trade‐offs obtained in the literature. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐noise low‐power front‐end logarithmic amplifier for neural recording system

In this work, a low‐power, low‐noise logarithmic preamplifier for biopotential and neural recording application is presented. The amplifier is based on a linear limit logarithmic amplifier technique, and an active filter as a DC cancellation filter has been included to its input in order to eliminate DC offsets, which are produced at the electrode–tissue interface. This system has been simulated in a UMC standard 90‐nm 1P9M CMOS process. Five dual gain stages are used to produce the required linear limit logarithmic amplifier. The dynamic range of the amplifier is measured to be 48 dB which covers the signals with amplitude from 20 μV to 5 mV. The amplifier consumes 23.5 μW from a 1.2‐V power supply and has a maximum gain of 69.8 dB. The simulated input referred noise is 5.3 μV over 0.1 Hz to 20 kHz. Copyright © 2012 John Wiley & Sons, Ltd.     

A subthreshold current‐sensing ΣΔ modulator for low‐voltage and low‐power sensor interfaces

A continuous‐time (CT) ΣΔ modulator for sensing and direct analog‐to‐digital conversion of nA‐range (subthreshold) currents is presented in this work. The presented modulator uses a subthreshold technique based on subthreshold source‐coupled logic cells to efficiently convert subthreshold current to digital code without performing current‐to‐voltage conversion. As a benefit of this technique, the current‐sensing CT ΣΔ modulator operates at low voltage and consumes very low power, which makes it convenient for low‐power and low‐voltage current‐mode sensor interfaces. The prototype design is implemented in a 0.18 µm standard complementary metal‐oxide semiconductor technology. The modulator operates with a supply voltage of 0.8 V and consumes 5.43 μW of power at the maximum bandwidth of 20 kHz. The obtainable current‐sensing resolution ranges from effective number of bits (ENOB) = 7.1 bits at a 5 kHz bandwidth to ENOB = 6.5 bits at a 20 kHz bandwidth (ENOB). The obtained power efficiency (peak FoM = 1.5 pJ/conv) outperforms existing current‐mode analog‐to‐digital converter designs and is comparable with the voltage‐mode CT ΣΔ modulators. The modulator generates very low levels of switching noise thanks to CT operation and subthreshold current‐mode circuits that draw a constant subthreshold current from the voltage supply. The presented modulator is used as a readout interface for sensors with current‐mode output in ultra low‐power conditions and is also suitable to perform on‐chip current measurements in power management circuits. Copyright © 2014 John Wiley & Sons, Ltd.     

New SRAM design using body bias technique for low‐power and high‐speed applications

In this paper, a new SRAM cell with body‐bias actively controlled by a control circuit and word line is introduced to realize low‐power and high‐speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade‐off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%. Copyright © 2013 John Wiley & Sons, Ltd.     

A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

A battery charger with maximum power point tracking function for low‐power photovoltaic system applications

A battery charger with MPPT function for low‐power PV system applications is presented in this study. For effective miniaturization, the battery charger is designed with high‐frequency operation. Some current‐sensing techniques are studied, and their MPPT implementation is compared. A battery charging method is also designed to prolong battery lifetime without the use of battery current sensors. The operation principles and design considerations of the proposed PV charger are analyzed and discussed in detail. A laboratory prototype is implemented and tested to verify the feasibility of the proposed scheme. Experimental results show that high MPPT accuracy and conversion efficiency can be simultaneously achieved under high‐frequency operation. Copyright © 2010 John Wiley & Sons, Ltd.     

Digitally‐assisted constant‐on‐time dynamic‐biasing technique for bandwidth and slew‐rate enhancement in ultra‐low‐power low‐dropout regulator

A digitally‐assisted constant‐on‐time dynamic‐biasing (COT‐DB) technique has been proposed to enable significant enhancement in dynamic performances, while the average current consumption can be kept to ultralow level. This dynamic‐biasing technique has a predefined magnitude and duration on biasing current boost, which is beneficial to estimate power budget in systems with finite energy source. The proposed technique has been applied to a low‐dropout regulator (LDO) to demonstrate the effectiveness. Experimental results show that significant improvements in settling times during load‐transients and line‐transients are as much as 880×, while the current consumption is only 1.02 μA. In fact, for the same dynamic performances, the average current consumption of LDO with COT‐DB technique can be as low as 0.39% of the LDO with heavy static biasing. The digitally‐assisted implementation of the technique also allows robust augmentation of the technique onto almost all analog systems. Copyright © 2015 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

Low‐frequency noise analysis and minimization in Gilbert‐cell‐based mixers for direct‐conversion (zero‐IF) low‐power front‐ends

Low‐frequency (flicker) noise is one of the most important issues in the design of direct‐conversion zero‐IF front‐ends. Within the front‐end building blocks, the direct‐conversion mixer is critical in terms of flicker noise, since it performs the signal down‐conversion to baseband. This paper analyzes the main sources of low‐frequency noise in Gilbert‐cell‐based direct‐conversion mixers, and several issues for minimizing the flicker noise while keeping a good mixer performance in terms of gain, noise figure and power consumption are introduced in a quantitative manner. In order to verify these issues, a CMOS Gilbert‐cell‐based zero‐IF mixer has been fabricated and measured. A flicker noise as low as 10.4 dB is achieved (NF at 10 kHz) with a power consumption of only 2 mA from a 2.7 V power supply. More than 14.6 dB conversion gain and noise figure lower than 9 dB (DSB) are obtained from DC to 2.5 GHz with an LO power of ?10 dBm, which makes this mixer suitable for a multi‐standard low‐power zero‐IF front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

Parallel operation of four‐switch full‐bridge power amplifiers and a unique digital control scheme for advanced magnetic resonance imaging

In recent years, magnetic resonance imaging (MRI) systems have been in demand to diagnose moving parts in the human body such as the heart or the blood in angiography, where images should be taken in milliseconds instead of minutes. Gradient power amplifiers, which are small but vital components for advanced MRI, require higher output power capacity as well as faster rise/fall dynamic response characteristics under a variety of specified current reference signals. This paper presents a novel switch‐mode gradient power amplifier using IGBTs which are connected in parallel to a conventional four‐switch full‐bridge power conversion circuit at their inputs/outputs in order to realize a higher power density. To satisfy the design specifications, which require minimized ripple and improved rise/fall dynamic response characteristics of the current in the gradient coil, a unique digital control scheme based on an optimal type 1 servo system is proposed and described in detail. The effectiveness of the above is discussed and evaluated through computer‐aided analysis. It is expected that the proposed techniques will greatly expand the diagnostic targets and improve the image quality of MRI. © 2000 Scripta Technica, Electr Eng Jpn, 132(1): 64–72, 2000     

A configurable 2‐Gbps LVDS transceiver in 150‐nm CMOS with pre‐emphasis,equalization, and slew rate control

A configurable full‐duplex low‐voltage differential signaling transceiver is presented, which can be configured to operate either for smaller differential channels (a few inches of striplines) or for longer channels (10 m of twisted pair cables). The configurability is embedded in the form of functionalities like pre‐emphasis, equalization, and slew rate control within the transceiver. The transmitter employs a hybrid voltage–current‐mode driver, which due to replica action, achieves a high‐impedance current‐mode signal dispatch and at the same time provides a matched impedance at the near end for improved intersymbol interference. The transmitter achieves slew rate control through a band‐limited pre‐driver, while the pre‐emphasis is achieved through a capacitive feed‐forward. The receiver employs a large‐input common‐mode first stage enclosed in a common‐mode control loop that enables its first stage to also act like a domain shifter (VDDIO‐to‐VDDCORE) reducing the overall power consumption. The equalization in the receiver is implemented by using carefully sized active inductive loads inside the receiver. The transceiver is designed and fabricated in 150‐nm complementary metal–oxide–semiconductor, sharing the space with a larger die, occupying an area of 400 × 400μm. The measurement results demonstrate that the transceiver is operating at 2 Gbps both for a 4‐in microstrip and a 10‐m twisted pair CAT6 cable with 30 and 180 ps of total jitter, respectively. The built‐in impedance calibrator minimizes the spread in the on‐die termination at the near end provided by the transmitter‐minimizing bit error rate across process, voltage, and temperature corners. The transmitter consumes a total power of 17 mW operating at 2 Gbps, that is, 8.5 pJ/bit of energy consumption; the receiver consumes a total power of 3.5 mW while driving a load of 5 pF at 2 Gbps. Copyright © 2016 John Wiley & Sons, Ltd.