Unified subharmonic oscillation conditions for peak or average current mode control

This paper is an extension of the author's recent research in which only buck converters were analyzed. Similar analysis can be equally applied to other types of converters. In this paper, a unified model is proposed for buck, boost, and buck–boost converters under peak or average current mode control to predict the occurrence of subharmonic oscillation. Based on the unified model, the associated stability conditions are derived in closed forms. The same stability condition can be applied to buck, boost, and buck–boost converters. Based on the closed‐form conditions, the effects of various converter parameters including the compensator poles and zeros on the stability can be clearly seen, and these parameters can be consolidated into a few ones. High‐order compensators such as type‐II and PI compensators are considered. Some new plots are also proposed for design purpose to avoid the instability. The instability is found to be associated with large crossover frequency. A conservative stability condition, agreed with the past research, is derived. The effect of the voltage loop ripple on the instability is also analyzed. Copyright © 2014 John Wiley & Sons, Ltd.     

Fast‐scale stability limits of a two‐stage boost power converter

There are many applications in power electronics that demand high step‐up conversion ratio between the source and the load. A simple way of achieving such a high voltage ratio is by cascading DC–DC boost converters in a few stages. The individual converters in such a cascaded system are usually designed separately applying classical design criteria. This paper investigates the stability of the overall system of a cascade connection of two boost converters under current mode control. We first demonstrate the bifurcation behavior of the system, and it is shown that the desired periodic orbit can undergo fast‐scale period doubling bifurcation leading to subharmonic oscillations and chaotic regimes under parameter variation. The value of the intermediate capacitor is taken as a design parameter, and we determine the minimum ramp slope in the first stage required to maintain stability. It is shown that smaller capacitance values give rise to wider stability range. We explain the bifurcation phenomena using a full‐order model. Then, in order to simplify the analysis and to obtain a closed‐form expression to explain the previous observation, we develop a reduced‐order model by treating the second stage as a current sink. This allows us to obtain design‐oriented stability boundaries in the parameter space by taking into account slope interactions between the state variables in the two stages. Copyright © 2015 John Wiley & Sons, Ltd.     

Application of duality principle to synthesis of single‐stage power‐factor‐correction voltage regulators

The duality principle is applied to derive new single‐stage power‐factor‐correction (PFC) voltage regulators. This paper begins with an application of duality transformation to conventional discontinuous‐conduction‐mode buck, buck‐boost and boost converters. The resulting dual converters operate in the discontinuous capacitor voltage mode. These new converters provide the same PFC property, but in the dual manner. It is proved that in the practical case of the input being a voltage source, the mandatory insertion of inductance between the voltage input and the ‘dual PFC converter’ does not affect the power‐factor‐correcting property. A new single‐stage PFC regulator is derived by taking the dual of a well‐known circuit based on a cascade of conventional boost and buck converters. Analytical design expressions are derived, illustrating the relation between current stress and component values. Experiments are performed to confirm the operation of the circuit and its power‐factor‐correcting capability. Copyright © 2003 John Wiley & Sons, Ltd.     

Fast‐transient DC‐DC converter using a high‐performance error amplifier with a rapid output‐voltage control technique

This letter presents a method for improving the transient response of DC‐DC converters. The proposed technique replaces the conventional error amplifier with a combination of two different amplifiers to achieve a high loop gain and high slew rate. In addition, a rapid output‐voltage control circuit is employed to further reduce the recovery time. The proposed technique was applied to a four‐phase buck converter, and the chip was implemented using a 0.18‐μm CMOS process. The switching frequency of each phase was set at 2 MHz. Using a supply voltage of 2.7–5.5 V and an output voltage of 0.6–1.5 V, the regulator provided up to 2‐A load current with maximum measured recovery time of only 6.2 and 6.5 μs for increasing and decreasing load current, respectively. Copyright © 2017 John Wiley & Sons, Ltd.     

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques

A new fast‐response buck converter using accelerated pulse‐width‐modulation techniques is proposed in this article. The benefits of the accelerated pulse‐width‐modulation technique is fast‐transient response, simple‐compensation design, and no requirement for slope compensation; furthermore, some power management problems are minimized, such as EMI (Electro Magnetic Interference), size, design complexity, and cost. The traditional voltage‐mode speed is slower with the transient response, so an accelerated pulse‐width‐modulation technique is used to solve the problem of slowed transient response in this article. The proposed buck converter has excellent conversion efficiency with a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 µm CMOS 2P4M processes, and the total chip area is 1.32 × 1.22 mm². Maximum output current is 300 mA when the output voltage equals 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 1–2.6 V. Maximum transient response is less than 5 µs. The simulation and experimental results are presented in this article. Copyright © 2011 John Wiley & Sons, Ltd.     

Sampled‐data poles,zeros, and modeling for current‐mode control

Exact and approximate sampled‐data models in closed forms are derived for switching DC–DC converters under peak/valley current‐mode control. The corresponding sampled‐data poles and zeros in closed forms are also derived. The location and stability conditions of the poles and zeros, boundary conditions of subharmonic instability, and nulling of the audio‐susceptibility are also derived. It is proved that the stable operating range of the source voltage is linearly proportional to the ramp slope. The sampled‐data models agree with previous experiment results and accurately predict the subharmonic instability. The different view from the sampled‐data model about the number and stability (minimum phase) of pole and zero does not necessarily invalidate the traditional continuous‐time averaged model. However, this different view gives better prediction about converter dynamics and is useful for the analog or digital controller design for DC–DC converters. Copyright © 2011 John Wiley & Sons, Ltd.     

Single‐stage single‐switch PFC converter for wide‐input extreme step‐down voltage applications

This paper presents a new single‐stage single‐switch high power factor correction AC/DC converter suitable for low‐power applications (< 150 W) with a universal input voltage range (90–265 V_rms). The proposed topology integrates a buck–boost input current shaper followed by a buck and a buck–boost converter, respectively. As a result, the proposed converter can operate with larger duty cycles compared with the existing single‐stage single‐switch topologies, hence, making them suitable for extreme step‐down voltage conversion applications. Several desirable features are gained when the three integrated converter cells operate in discontinuous conduction mode. These features include low semiconductor voltage stress, zero‐current switch at turn‐on, and simple control with a fast well‐regulated output voltage. A detailed circuit analysis is performed to derive the design equations. The theoretical analysis and effectiveness of the proposed approach are confirmed by experimental results obtained from a 100‐W/24‐V_dc laboratory prototype. Copyright © 2011 John Wiley & Sons, Ltd.     

Dynamic modeling of a dual active bridge DC to DC converter with average current control and load‐current feed‐forward

Bidirectional power flow is needed in many power conversion systems like energy storage systems, regeneration systems, power converters for improvement of the power quality and some DC‐DC applications where bidirectional high power conversion and galvanic isolation are required. The dual active bridge (DAB) is an isolated, high voltage ratio DC‐DC converter suitable for high power density and high power applications, being a key interface between renewable energy sources and energy storage devices. This paper is focused on the modeling and control design of a DC‐DC system with battery storage based on a DAB converter with average current mode control of the output current and output voltage control. The dynamic response of the output voltage to load steps is improved by means of an additional load‐current feed‐forward control loop. An analytical study of the load‐current feed‐forward is presented and validated by means of both simulations and experimental results. Copyright © 2014 John Wiley & Sons, Ltd.     

后缘调制Buck变换器的周期借用数字电流控制

为了解决数字电流控制环路的硬件处理速度与带宽之间的矛盾,提出了基于后缘调制Buck变换器的周期借用数字电流控制方法,实现了传统延迟电流控制的硬件速度要求和无拍差电流控制的环路带宽.针对谷值、平均值和峰值电流控制目标,建立了电流控制律,研究了次谐振荡现象及其消除方法,分析了周期借用数字电流控制的Buck变换器鲁棒性.仿真结果表明,周期借用数字电流控制和无拍差电流控制的Buck变换器具有相同的瞬态性能,并且优于延迟电流控制.     

DSP based proportional integral sliding mode controller for photo-voltaic system

The buck–boost converter is controlled using different algorithms like voltage mode control, current mode control, V² control, enhanced V² control, Sliding Mode Control (SMC), and Proportional Integral (PI) control. In all these algorithms the steady state error is more. On combining PI control and sliding mode control the steady error can be minimized. In industry and commercial applications involving Photo-Voltaic (PV) systems, uses buck–boost converter. In this converter above control algorithms are implemented using hardware circuitry or microcontroller. In industry and commercial applications Digital Signal Processor (DSP) is used for automation purposes and the same DSP can be used to implement control algorithms so as to get maximum electrical energy from solar energy. The efficient utilization of resources such as DSP is achieved as we are using the same DSP for implementing control algorithm. In the proposed study, PI control method and sliding mode control methods are combined to obtain a Proportional Integral Sliding Mode Control (PISMC) and it is used to control the buck–boost converter which is used to drive the electrical loads from solar energy. The buck–boost converter is designed, simulated and implemented. The algorithms PI, SMC and PISMC are simulated in using MATLAB simulink and then implemented in DSP TMS 320 2808. In the proposed study PISMC, a stable and efficient output voltage is obtained in which the steady state error and maximum overshoot are minimum. The PISMC is better in terms of transient and steady state performances as validated by our experiments. The proposed study will work in real-time since DSP is used for implementing the control algorithms and found to be better in terms of speed and regulation. The proposed DSP based PISMC can also be used to control other types of DC–DC converters.     

Calculation of steady‐state solution of parallel‐connected buck converters with active current sharing and its parameter sensitivity

In this paper, the effect of active current‐sharing control on the steady‐state operation of parallel‐connected buck converters is investigated. The system under study consists of N voltage‐mode‐controlled buck converters connected in parallel. Three kinds of active current‐sharing schemes are considered, namely, master–slave scheme with automatic master, master–slave scheme with dedicated master, and democratic scheme. Using the principle of charge balance, the mechanism of the operating point drift arising from active current sharing is examined. A general formulation of the steady‐state solution under active current sharing is derived. Moreover, detailed parameter sensitivity analysis is performed to evaluate the effect of parameters' variation on the operating point. The results from sensitivity analysis can be used to categorize parameters for facilitating practical design. Computer simulations are presented to verify the analytical results. Copyright © 2010 John Wiley & Sons, Ltd.     

Non‐isolated single‐switch DC–DC converters with extended duty cycle for high step‐down voltage applications

Several new topologies of single‐switch non‐isolated DC–DC converters with wide conversion gain and reduced semiconductor voltage stress are proposed in this paper. Most of the proposed topologies are derived from the conventional inverse of SEPIC (Zeta) converter. The proposed topologies can operate with larger switch duty cycles compared with the existing single switch topologies, hence, making them well suitable for high step‐down voltage conversion applications. With extended duty cycle, the current stress in the active power switch is reduced, leading to a significant improvement of the system losses. Moreover, the active power switch in some of the proposed topologies is utilized much better compared to the conventional Zeta and quadratic‐buck converters. The principle of operation, theoretical analysis, and comparison of circuit performances with other step‐down converters are discussed regarding voltage and current stress and switch silicon utilization. Finally, simulation and experimental results for a design example of a 50 W/5 V at 42‐V input voltage operating at 50 kHz will be provided to evaluate the performance of the proposed converters. Copyright © 2014 John Wiley & Sons, Ltd.     

Dynamic modeling of DC–DC converters with peak current control in double‐stage photovoltaic grid‐connected inverters

In photovoltaic (PV) double‐stage grid‐connected inverters a high‐frequency DC–DC isolation and voltage step‐up stage is commonly used between the panel and the grid‐connected inverter. This paper is focused on the modeling and control design of DC–DC converters with Peak Current mode Control (PCC) and an external control loop of the PV panel voltage, which works following a voltage reference provided by a maximum power point tracking (MPPT) algorithm. In the proposed overall control structure the output voltage of the DC–DC converter is regulated by the grid‐connected inverter. Therefore, the inverter may be considered as a constant voltage load for the development of the small‐signal model of the DC–DC converter, whereas the PV panel is considered as a negative resistance. The sensitivity of the control loops to variations of the power extracted from the PV panel and of its voltage is studied. The theoretical analysis is corroborated by frequency response measurements on a 230 W experimental inverter working from a single PV panel. The inverter is based on a Flyback DC–DC converter operating in discontinuous conduction mode (DCM) followed by a PWM full‐bridge single‐phase inverter. The time response of the whole system (DC–DC + inverter) is also shown to validate the concept. Copyright © 2011 John Wiley & Sons, Ltd.     

Quasi‐V2 hysteretic control boost DC–DC regulator with synthetic current ripple technique

Conventionally, a high accuracy operational amplifier (OPA)‐based current sensor is used for sensing current message under a full load range, which increases the cost characteristic. Instead of a high accuracy OPA‐based current sensor, this paper describes using a switching inductor quasi‐V² hysteretic control boost dc–dc regulator with a proposed current‐sensing technique named emulated‐ramp feedback (ERF), which can improve transfer efficiency under a full load range. Two control systems are presented in this paper. The first system, a hysteretic voltage control switching boost converter with ERF, achieves the hysteretic voltage control in a boost regulator and lowers the cost characteristic without using compensator. The second system, a quasi‐V² hysteretic voltage control switching boost converter with ERF, demonstrates the compatibility of ERF technique in rippled‐based control boost converters. The regulator was implemented with TSMC 0.25‐µm HV CMOS process. Experimental results show the second system can work under the specification of 5–12 V with a 0 to 300‐mA load range. Additionally, this system attained a recovery time is 27/95 µs for step‐up/step‐down in a 100 to 300‐mA continuous conduction mode load current, and a peak efficiency of 92.1% with a chip area of only 1.014 mm². Copyright © 2016 John Wiley & Sons, Ltd.     

具有快速负载动态响应的DC／DC开关变换器开环控制新策略

采用何种控制策略和如何实现控制方法是决定开关变换器的效率和性能的主要因素。单周控制方法是近年来提出的一种新型非线性控制策略。这对输入电源电压的变化具有快速的动态跟踪能力,但对负载变化的抑制能力差,基于等效受控源平均法,提出了一种新的非线性控制方法,使得PWM开关变换器的输出电压,在负载干扰和电源电压干扰下,具有优良的动态响应特性。以降压型变换器为例,首先建立开关变换器大信号低频平均电路模型。通过分析平均电路模型,可以推导出一种新型开环非线性控制策略。这种控制方法具有固有的稳定性,快速动态响应和无过冲等优点。为了实现新的控制方法,建立了电感电压低频分量的数学模型。计算机仿真和实验测试结果证明理论预期分析。     

A modified dual current mode control method with an adaptive current bandwidth

In this paper, a new adaptive dual current mode control method (ADCMC) is presented, being a result of the modification of existing dual current mode control (DCMC) by introducing an adaptive current bandwidth. The ADCMC offers several important advantages over DCMC, such as no peak‐to‐average error in the inductor current, better transient response of current loop, and improved line regulation. A detailed analysis of the proposed ADCMC is performed for three types of DC–DC power electronics converters: buck, boost, and non‐inverting buck–boost converter. The performances of the ADCMC are tested with simulations and experiments. The obtained results confirm the analysis and validity of the proposed ADCMC method. Copyright © 2015 John Wiley & Sons, Ltd.     

Dynamic model of one‐cycle control for converters operating in continuous and discontinuous conduction modes

In this paper a new dynamic model of one‐cycle‐controlled converters operating either in continuous or in discontinuous conduction mode (DCM) is introduced. The static and dynamic behaviour is analysed by using sampled‐data modelling combined with the small‐signal linearization of the average model of the converter's power stage. The proposed model is valid for frequencies up to half the switching frequency and, while the other dynamic models presented in the literature cover continuous conduction mode only, it also gives an accurate prediction of the system's dynamic behaviour in the DCM. The model allows to determine the closed‐form expression of the reference‐to‐output transfer function G of the system, which is a fundamental prerequisite for the design of a conventional output feedback control circuit aimed at improving the dynamic behaviour of the system in response to load variations. In this paper it is also shown that one‐cycle control does not work properly in switching converters operating in deep DCM if some specific design constraints are not fulfilled. The theoretical predictions are confirmed by the results of suitable numerical simulations and laboratory experiments on a one‐cycle‐controlled buck‐switching converter. Copyright © 2008 John Wiley & Sons, Ltd.     

Filter‐based perturbation control of low‐frequency oscillation in voltage‐mode H‐bridge DC–AC inverter

This paper presents a new additional perturbation control method for suppressing low‐frequency oscillation in voltage‐mode H‐bridge DC–AC inverter. The stability boundary of the H‐bridge inverter is investigated from its small‐signal averaged model. High input voltage and light load would cause low‐frequency oscillation in this system. To this end, a filter‐based perturbation control (FBPC) is proposed for eliminating this oscillation, by using an analog filter to extract the unexpected signal and applying it to the control loop. Theoretical results show a larger stability range of the controlled system with the proposed FBPC. The simulation and experiment results show that the proposed controller can control the low‐frequency oscillation in H‐bridge DC–AC inverter well. Copyright © 2014 John Wiley & Sons, Ltd.     

Dynamics of PFC power converters subject to time‐delayed feedback control

Power factor correction converters are power electronics circuits used as AC‐DC power supplies. These systems are well known to exhibit nonlinear phenomena such as subharmonic oscillations and chaotic regimes. These undesirable behaviors increase the THD and therefore can jeopardize enormously the system performances. In this paper, time delay feedback control is applied to stabilize a two‐stage power factor correction AC‐DC converter when it exhibits these instabilities under traditional controllers. This control technique introduces many advantages to the most and widely used average current mode control through widening the stability domain of the system. By appropriately selecting the time delay feedback gain and the time delay period, the undesirable subharmonic components are eliminated, whereas the desired ones remain unchanged. A harmonic balance approach is used for studying the dynamics of the system under the new control scheme and to obtain the stabilization domain. Copyright © 2010 John Wiley & Sons, Ltd.     

Control of sub‐harmonic oscillation in peak current mode buck converter with dynamic resonant perturbation

In this paper, a dynamic resonant perturbation (DRP) method is proposed to control sub‐harmonic oscillation in a peak current mode controlled buck converter. Different from the traditional non‐feedback resonant parametric perturbation method, the proposed DRP method extracts an approximate sinusoidal control signal from the output voltage. The self‐stabilizing condition for the designed control signal is presented, and its analog circuit implementation is given as well. Furthermore, the system stability boundary is obtained by investigating the system eigenvalues, and the control parameter is effectively determined. The presented simulation and experiment results show that the proposed DRP method eliminates sub‐harmonic oscillation without sacrificing the peak value of the inductor current and features with a self‐stabilizing characteristic for external condition changes. Copyright © 2014 John Wiley & Sons, Ltd.