Phase error analysis in CMOS injection‐coupled LC quadrature oscillator (IC‐QO)

This paper presents a novel approach to study the phase error in source injection coupled quadrature oscillators (QOs). Like other LC QOs, the mismatches between LC tanks are the main source of phase error in this oscillator. The QO is analyzed where the phase error and oscillation frequency are derived in terms of circuit parameters. The proposed analysis shows that the output phase error is a function of injection current and the current of source equivalent capacitor. As a result, it is shown that increasing of tail current and LC tank quality factor decreases the phase error. Derived equations show that the phase error can be cancelled and even controlled by adjusting bias currents. To evaluate the proposed analysis and consequent designed QO, a 5.5 GHz CMOS QO is designed and simulated using the practical 0.18 µm TSMC CMOS technology. The experiments show good agreement between analytical equations and simulation results. Copyright © 2013 John Wiley & Sons, Ltd.     

Phase noise analysis of source injection coupled quadrature oscillator

This paper analyzes the thermally induced phase noise and the up-conversion of flicker noise into phase noise of source injection coupled quadrature oscillator (SIC-QOSC), for the first time. Furthermore, this paper provides a complete analysis for the injection current of the SIC-QOSC and extracts the closed-form expressions for it for the first time, too. These expressions lead to obtaining the harmonics of the injection current as well as the oscillation amplitude, which is necessary for the phase noise analysis. To evaluate the extracted equations, this paper compares the calculated results with appropriate simulations. Comparisons confirm the accuracy of the proposed injection current expressions and the phase noise formulas. Using the closed-form equations of phase noise, designers can understand the SIC-QOSC's design tradeoffs and design the oscillator for given phase noise.     

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

This study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to ?123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to ?193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.     

A 5 GHz quadrature relaxation oscillator with mixing for improved testability or compact front‐end implementation

We demonstrate by measurements on a test circuit that a 5 GHz relaxation oscillator with accurate quadrature outputs and low phase‐noise can be obtained, and that these favorable properties can be preserved while the mixing function is performed by this oscillator. This is useful either to measure the quadrature error at a low frequency, or to implement a low‐intermediate frequency (IF) or zero‐IF (homodyne) radio frequency front‐end. Copyright © 2008 John Wiley & Sons, Ltd.     

An inductorless CMOS quadrature oscillator continuously tuneable from 3.1 to 10.6 GHz

Modern RF front‐ends require wide tuning‐range oscillators with quadrature outputs. In this paper we present a two‐integrator quadrature oscillator, which covers the whole bandwidth of UWB applications. A circuit prototype in a 130 nm CMOS technology is continuously tuneable from 3.1 to 10.6 GHz. The circuit die area is less than 0.013mm², leading to a figure‐of‐merit FOMA of ?176.7dBc/Hz at the upper frequency. The supply voltage is 1.2 V, and the power consumption is 7 mW at the lower frequency and 13 mW at the upper frequency. Copyright © 2010 John Wiley & Sons, Ltd.     

Experimental comparison of phase‐noise in cross‐coupled RC‐ and LC‐oscillators

Relaxation RC‐oscillators are notorious for their poor phase‐noise performance. However, there are reasons to expect a phase‐noise reduction in quadrature oscillators obtained by cross‐coupling two relaxation oscillators. We present measurements on 5 GHz oscillators, which show that in RC‐oscillators the coupling reduces both the phase‐noise and quadrature error, whereas in LC‐oscillators the coupling reduces the quadrature error, but increases the phase‐noise. A comparison using standard figures of merit indicates that quadrature RC‐oscillators may be a viable alternative to LC‐oscillators when area and cost are to be minimized. Copyright © 2009 John Wiley & Sons, Ltd.     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

Frequency–amplitude relations for cross‐coupled voltage‐controlled oscillator

Dependence of frequency on amplitude and control bias is considered for the cross‐coupled voltage‐controlled oscillator. Closed form expressions are derived for frequency of oscillation as a function of amplitude, for positive and negative control bias voltages. Theory of nonlinear ordinary differential equations is utilized to show that the capacitance–voltage relation is the main cause of frequency shift with amplitude. Furthermore, the case of small amplitudes relative to control voltage is analyzed, and a closed form expression is derived for dependence of frequency on amplitude. This relation is then verified using the concept of effective capacitance. The effective capacitance approach is also used to extend the analysis to large voltage swings. Dependence of frequency on tuner control voltage is calculated for both bias polarities. Implications of the aforementioned equations for voltage‐controlled oscillator performance are discussed. Numerical calculations and simulations are used to compare and verify the closed form equations, showing good agreement. Copyright © 2012 John Wiley & Sons, Ltd.     

A 4.8–6.8 GHz low phase noise LC VCO in 0.13‐µm CMOS technology

This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd.     

Electronically controlled oscillator with linear frequency adjusting for four‐phase or differential quadrature output signal generation

This paper introduces novel four‐phase oscillator employing two Dual‐Output Controlled Gain Current Follower Buffered Amplifiers (DO‐CG‐CFBAs), single Current Amplifier, three resistors, and two grounded capacitors suitable for differential quadrature signal production (floating outputs). To control the frequency of oscillation (FO) and condition of oscillation (CO), only the current gain adjustment of active elements is used. The circuit was designed by well‐known state variable approach. The oscillator employs three active elements for linear control of FO and to adjust CO and provides low‐impedance voltage outputs. Furthermore, two straightforward ways of automatic amplitude gain control were used and compared. Active elements with very good performance are implemented to fulfill required features. Suitable CMOS implementation of introduced DO‐CG‐CFBA was shown. Important characteristics of the designed oscillator were verified experimentally and by PSpice simulations to confirm theoretical and expected presumptions. Copyright © 2013 John Wiley & Sons, Ltd.     

Transformer‐coupled π‐network differential CMOS oscillator circuit topology

This paper reports a novel oscillator circuit topology based on a transformer‐coupled π‐network. As a case study, the proposed oscillator topology has been designed and studied for 60 GHz applications in the frame of the emerging fifth generation wireless communications. The analytical expression of the oscillation frequency is derived and validated through circuit simulations. The root‐locus analysis shows that oscillations occur only at that resonant frequency of the LC tank. Moreover, a closed‐form expression for the quality factor (Q) of the LC tank is derived which shows the enhancement of the equivalent quality factor of the LC tank due to the transformer‐coupling. Last, a phase noise analysis is reported and the analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results obtained through SpectreRF simulations in the Cadence design environment with a 28 nm CMOS process design kit commercially available. Copyright © 2016 John Wiley & Sons, Ltd.     

Evaluation and comparison of GHz‐range LC oscillators using time‐varying root‐locus

This paper presents a comprehensive comparison between complementary metal‐oxide‐semiconductor (CMOS) LC‐oscillator topologies often used in GHz‐range transceivers. The comparison utilizes the time‐varying root‐locus (TVRL) method to add new insights into the operation of different oscillators. The paper focuses on the treatment of the TVRL trajectories obtained for different oscillators and establishes links between the trajectories and physical phenomena in oscillators. The evaluation of the root trajectories shows the advantages of the TVRL method for comparing oscillator topologies, which is also extended towards the analysis of voltage‐controlled oscillators. The necessary circuit simplifications required in closed‐form root‐locus analysis are avoided by the TVRL, which allows precise oscillator comparison and reveals details on the topology specifics. The derived conclusions have been verified by the Cadence Spectre‐RF simulator on 130‐nm CMOS process. Copyright © 2011 John Wiley & Sons, Ltd.     

Design and implementation of switched coil LC‐VCOs in the GHz range using the self‐inductance technique

This paper presents the design and implementation of dual‐band LC‐VCOs in the GHz‐range featuring a switched coil LC‐tank. The proposed design exploits the self‐inductance technique. The design of the coil starts from simple considerations and back‐of‐the‐envelope calculations, then electromagnetic simulations are used to optimize the coil layout. The sizing of the switch and its impact on the VCO performance are addressed as well. The VCOs have been implemented in 65 nm CMOS technology. Good correlation between simulated and measured tuning range and phase noise is obtained for all designs, thus confirming the validity and robustness of the design methodology and coil models. Copyright © 2013 John Wiley & Sons, Ltd.     

A linear,ultra wideband,low‐power, 2.1–5 GHz,VCO

A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a UWB‐FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage‐to‐current (V‐to‐I) converter which translates the VCO input voltage modulation signal to current. Two single‐ended inverter buffers are employed to drive either a differential or a single‐ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of ?7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB‐FM applications is covered for the entire industrial temperature range (?40 to 125^°C). Copyright © 2010 John Wiley & Sons, Ltd.     

Quadrature VCOs based on direct second harmonic locking: Theoretical analysis and experimental validation

We propose a theoretical analysis of the class of quadrature VCOs (QVCOs) based on two LC‐oscillators directly coupled by means of the second harmonic. The analysis provides the conditions for the existence and stability of steady‐state quadrature oscillations and a simplified model for the phase noise (PN) transfer function with respect to a noise source in parallel to the tank. We show that the figure of merit defined as the product between PN and current equals that of the single VCO, confirming that quadrature generation is achieved by this class of QVCO without degrading that figure of merit. An analytical model for the phase quadrature error due to tank mismatches is also proposed. The validity of all analytical models is discussed against numerical simulations. A practical implementation at 3.26 GHz with ±20% tuning range in a 0.13µm CMOS technology is also presented, confirming the main theoretical findings. Copyright © 2009 John Wiley & Sons, Ltd.     

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

In this paper, a true‐single‐phase clock latching based noise‐tolerant (TSPCL‐NT) design for dynamic CMOS circuits is proposed. A TSPCL‐NT dynamic circuit can isolate and filter noise before the noise enters into the dynamic circuit. Therefore, it cannot only greatly enhance the noise tolerance of dynamic circuits but also release the signal contention between the feedback keeper and the pull‐down network effectively. As a result, noise tolerance of dynamic circuits can be improved with lower sacrifice in power consumption and operating speed. In the 16‐bit TSPCL‐NT Manchester adder, the average noise threshold energy can be enhanced by 3.41 times. In the meanwhile, the power‐delay product can be improved by 5.92% as compared with the state‐of‐the art 16‐bit XOR‐NT Manchester adder design under TSMC 90 nm CMOS process. Copyright © 2014 John Wiley & Sons, Ltd.     

A 6‐Gbps/lane receiver for a clock‐forwarded link in 65‐nm CMOS process

For a 6‐Gbps/lane clock‐forwarded link, a wireline receiver has been developed. The phases of the sampling clocks are aligned to the center of the input data eye by a clock and data recovery (CDR) circuit. In the CDR circuit, the sampling clock phases are rotated by a phase rotating phase locked loop (PLL). A three‐tap decision feedback equalizer (DFE) compensates for the loss of cable together with a continuous‐time linear equalizer (CTLE) to ensure sufficient eye opening for the CDR circuit to find the optimum sampling phase. The DFE coefficients are adaptively calculated based on the data and edge samples. Implemented in a 65‐nm CMOS process, the three‐lane 6‐Gbps/lane receiver for a clock‐forwarded link occupies 0.63 mm² including pads and consumes 288 mA from a 1.2‐V supply. Copyright © 2015 John Wiley & Sons, Ltd.     

Analysis of flicker noise conversion to phase noise in CMOS differential LC oscillators

An analysis of the flicker noise conversion to close‐in phase noise in complementary metal‐oxide semiconductor (CMOS) differential inductance‐capacitance (LC)‐voltage controlled oscillator is presented. The contribution of different mechanisms responsible for flicker noise to phase noise conversion is investigated from a theoretical point of view. Impulse sensitivity function theory is exploited to quantify flicker noise to phase noise conversion process from both tail and core transistors. The impact of different parasitic capacitances inside the active core on flicker noise to phase noise conversion is investigated. Also, it is shown how different flicker noise models for core metal‐oxide semiconductor (MOS) transistors may result in different close‐in phase noise behaviors. Based on the developed analysis, design guidelines for reducing the close‐in phase noise are introduced. Copyright © 2015 John Wiley & Sons, Ltd.     

Channel noise enhancement in small geometry MOSFET and its influence on phase noise calculation of integrated voltage‐controlled oscillator

Channel noise enhancement due to MOSFET scaling and its influence on phase noise estimation of fully integrated VCO have been studied. The channel noise of MOSFET increases due to the hot electron effect of small geometry MOSFET is obvious. The channel noise coefficient, γ, of NMOS is 3.5 for 40‐nm gate length, 2.0 for 90‐nm gate length in spite of being ⅔ for long channels MOSFET. Simultaneously, calculation of phase noise of fully integrated VCO shows large difference using γ=⅔ because the part of noise performance of VCO gain‐cell depends on channel noise of MOSFET. Calculated phase noise showed good agreement with measured data when the optimum value of channel noise of MOSFET was adopted. Copyright © 2005 John Wiley & Sons, Ltd.     

Newly proposed hybrid resonant commutation bridge‐leg link snubber‐assisted three‐phase ZVZCS‐PWM soft‐switching inverter

This paper presents the newly proposed hybrid resonant commutation bridge‐leg link (HRCB) snubber circuit which can achieve zero voltage and zero current soft‐switching commutation for single‐phase and three‐phase voltage source‐type inverter, along with its unique features and operation principle. The circuit parameter design approach for the HRCB snubber circuit and the determination estimating scheme of the gate pulse timing processing which is more suitable and acceptable for single‐phase and space voltage vector modulated three‐phase voltage source inverter using the HRCB snubber circuit are described in this paper. In particular, the three‐phase voltage source soft‐switching inverter associated with the proposed HRCB circuits are evaluated and discussed from simulation and experimental viewpoints. The practical effectiveness of the HRCB snubber‐assisted three‐phase voltage source soft‐switching inverter using IGBT power modules which is based on the instantaneous space voltage vector modulation is clarified on the output voltage waveform, actual efficiency of electromagnetic noise in comparison with three‐phase voltage source‐type conventional hard‐switching inverter. © 2006 Wiley Periodicals, Inc. Electr Eng Jpn, 157(4): 75–84, 2006; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20111