A 12‐bit 10‐MS/s SAR ADC with a binary‐window DAC switching scheme in 180‐nm CMOS

This paper presents an energy‐efficient 12‐bit successive approximation‐register A/D converter (ADC). The D/A converter (DAC) plays a crucial role in ADC linearity, which can be enhanced by using larger capacitor arrays. The binary‐window DAC switching scheme proposed in this paper effectively reduces DAC nonlinearity and switching errors to improve both the spurious‐free dynamic range and signal‐to‐noise‐and‐distortion ratio. The ADC prototype occupies an active area of 0.12 mm² in the 0.18‐μm CMOS process and consumes a total power of 0.6 mW from a 1.5‐V supply. The measured peak differential nonlinearity and integral nonlinearity are 0.57 and 0.73 least significant bit, respectively. The ADC achieves a 64.7‐dB signal‐to‐noise‐and‐distortion ratio and 83‐dB spurious‐free dynamic range at a sampling rate of 10 MS/s, corresponding to a peak figure‐of‐merit of 43 fJ/conversion‐step.     

A 0.5‐V 5.9‐fJ/conversion‐step SAR ADC in 0.18‐μm CMOS

In this paper, we present a 434‐nW 8‐bit successive approximation register analog‐to‐digital converter (SAR ADC). We mainly consider the optimization of power consumption. A modified split‐capacitor array involving a novel switching scheme is proposed, which reduces the switching power consumption to just 13.8 for the single‐ended scheme without any losses in performance. Based on the SMIC CMOS 0.1 μm EEPROM 2P4M process, the simulation results show that at 0.5 V supply voltage, 300 kS/s sample frequency, and 4.98 kHz input frequency, the ADC achieves an signal‐to‐noise‐plus‐distortion ratio (SNDR) of 49.58 dB and effective number of bits (ENOB) of 7.94, and consumes 434 nW, resulting in a figure of merit of 5.9 fJ/conversion step. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 7.5‐μW 0.08‐mm2 single‐ended SC delta‐sigma ADC for acoustic sensor applications

This study presents an ultra‐low‐power, small‐size, 1‐bit, single‐ended, and switched‐capacitor (SC) delta‐sigma analog‐to‐digital converter (ADC) for wireless acoustic sensor nodes. This wireless sensor node has a delta‐sigma ADC that converts the sensed signal to a digital signal for convenient data processing and emphasizes the features of small size and low‐power consumption. The chip area of the delta‐sigma ADC is dominated by the capacitor; therefore, a novel common‐mode (CM) controlling technique with only transistors is proposed. This ADC achieves an extremely small size of 0.08 mm² in a 130‐nm CMOS process. The conventional operational transconductance amplifiers (OTAs) are replaced by inverters in the weak inversion region to achieve high power efficiency. At 4‐MHz sampling frequency and 0.7‐V power supply voltage, the delta‐sigma ADC achieves a 55.8‐dB signal‐to‐noise‐plus‐distortion ratio (SNDR) and a 298‐fJ/step figure‐of‐merit (FOM) in a signal bandwidth of 25 kHz, while consuming only 7.5 μW of power. Copyright © 2015 John Wiley & Sons, Ltd.     

A 0.6‐V sub‐mW X‐band RFSOI CMOS LNA with novel complementary current‐reused technique

A fully integrated 0.6 V low‐noise amplifier (LNA) for X‐band receiver application based on 0.18 μm RFSOI CMOS technology is presented in this paper. To achieve low noise and high gain with the constraint of low voltage and low power consumption, a novel modified complementary current‐reused LNA using forward body bias technique is proposed. A diode connected MOSFET forward bias technique is employed to minimize the body leakage and improve the noise performance. A notch filter isolator is constructed to improve the linearity of low voltage. The measured results show that the proposed LNA achieves a power gain of 11.2 dB and a noise figure of 3.8 dB, while consuming a DC current of only 1.6 mA at supply voltage of 0.6 V. Copyright © 2017 John Wiley & Sons, Ltd.     

A 14b 150 MS/s 140 mW 2.0 mm2 0.13µm CMOS A/D converter for software‐defined radio systems

This work proposes a 14 b 150 MS/s CMOS A/D converters (ADC) for software‐defined radio systems requiring simultaneously high‐resolution, low‐power, and small chip area at high speed. The proposed calibration‐free ADC employs a wide‐band low‐noise input sample‐and‐hold amplifier (SHA) along with a four‐stage pipelined architecture optimizing scaling‐down factors for the sampling capacitance and the input trans‐conductance of amplifiers in each stage to minimize thermal noise effect and power consumption. A signal‐insensitive 3‐D fully symmetric layout achieves a 14 b level resolution by reducing a capacitor mismatch of three MDACs. The prototype ADC in a 0.13µm 1P8M CMOS technology demonstrates a measured differential nonlinearity (DNL) and integral nonlinearity within 0.81LSB and 2.83LSB at 14 b, respectively. The ADC shows a maximum signal‐to‐noise‐and‐distortion ratio of 64 and 61 dB and a maximum spurious‐free dynamic range of 71 and 70 dB at 120 and 150 MS/s, respectively. The ADC with an active die area of 2.0mm² consumes 140 mW at 150 MS/s and 1.2 V. Copyright © 2010 John Wiley & Sons, Ltd.     

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A new solution for an ultra low voltage bulk‐driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n‐well 0.18‐µm complementary metal–oxide–semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6‐dB steps. At minimum gain, the PGA offers nearly rail‐to‐rail input/output swing and the input referred thermal noise of 2.37 μV/Hz^1/2, which results in a 63‐dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5‐pF load capacitance and the third‐order input intercept point (IIP₃) is 1.62 V. The circuit performance was simulated with LTspice. Copyright © 2016 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

A 1.9‐GHz silicon‐on‐insulator CMOS stacked‐FET power amplifier with uniformly distributed voltage stresses

A 1.9‐GHz single‐stage differential stacked‐FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32‐μm 2.8‐V thick‐oxide MOSFETs in a 0.18‐μm silicon‐on‐insulator CMOS process. The input cross‐coupled stacked‐FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked‐FET power amplifier in sub‐micrometer CMOS technology. With a 4‐V supply voltage, the proposed power amplifier with an integrated output coupled‐resonator balun showed a small‐signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power‐added efficiency of 41.5% at the operating frequency. Copyright © 2017 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

Design‐oriented model for power‐driven design optimization of SC‐ΣΔ modulators

A behavioral model for switched‐capacitors sigma‐delta modulators, suitable for power‐driven design, is presented. Because of the oversampling behavior of this kind of analog‐to‐digital converters, transistor‐level simulations are extremely time consuming. Thus, accurate behavioral models are mandatory in the preliminary design steps to cut the development time. However, when the power consumption of the modulator is pushed down to the absolute minimum level, second‐order effects affecting the settling behavior of the switched‐capacitor integrator must be taken into account. Furthermore, by means of an accurate noise model, based on a second‐order transfer function of the amplifier, a global power minimization is achieved, and the optimum partitioning between the switch and op‐amp noise is obtained. In spite of the improved accuracy, the proposed model requires only a few parameters of the amplifier in the integrator. This allows to easily link the model to an external set of circuit equations, to be derived for the specific amplifier used in the modulator. The model was used in the design of a third‐order modulator in an STM 90‐nm technology. The silicon samples exhibit an effective resolution of 15.2‐b with a 500‐Hz output rate, an oversampling ratio of 500, and a Schreier figure‐of‐merit of 162 dB, with a 38‐μW power consumption at 1.2‐V supply.     

A 300‐mA load CMOS low‐dropout regulator without an external capacitor for SoC and embedded applications

This study proposes a 300‐mA external capacitor‐free low‐dropout (LDO) regulator for system‐on‐chip and embedded applications. To achieve a full‐load range from 0 to 300 mA, a two‐scheme (a light‐load case and a heavy‐load case) operation LDO regulator with a novel control circuit is proposed. In the light‐load case (0–0.5 mA), only one P‐type metal–oxide–semiconductor input‐pair amplifier with a 10‐pF on‐chip capacitor is used to obtain a load current as low as 0. In the heavy‐load case (0.5 to 300 mA), both P‐type metal–oxide–semiconductor and N‐type metal–oxide–semiconductor differential input‐pair amplifiers with an assistant push‐pull stage are utilized to improve the stability of the LDO regulator and achieve a high slew rate and fast‐transient response. Measurements show an output voltage of 3.3 V and a full output load range from 0 to 300 mA. A line regulation of 1.66 mV/V and a load regulation of 0.0334 mV/mA are achieved. The measured power‐supply rejection ratio at 1 kHz is −65 dB, and the measured output noise is only 34 μV. The total active chip size is approximately 0.4 mm² with a standard 0.5 μm complementary metal–oxide–semiconductor process. Copyright © 2017 John Wiley & Sons, Ltd.     

Impact of high‐κ gate dielectric and other physical parameters on the electrostatics and threshold voltage of long channel gate‐all‐around nanowire transistor

High‐κ gate‐all‐around structure counters the Short Channel Effect (SCEs) mostly providing excellent off‐state performance, whereas high mobility III–V channel ensures better on‐state performance, rendering III–V nanowire GAAFET a potential candidate for replacing the current FinFETs in microchips. In this paper, a 2D simulator for the III–V GAAFET based on self‐consistent solution of Schrodinger–Poisson equation is proposed. Using this simulator, capacitance–voltage profile and threshold voltage are characterized, which reveal that gate dielectric constant (κ) and oxide thickness do not affect threshold voltage significantly at lower channel doping. Moreover, change in alloy composition of In_xGa_1‐xAs, channel doping, and cross‐sectional area has trivial effects on the inversion capacitance although threshold voltage can be shifted by the former two. Although, channel material also affects the threshold voltage, most sharp change in threshold voltage is observed with change in fin width of the channel (0.005 V/nm for above 10 nm fin width and 0.064 V/nm for sub‐10 nm fin width). Simulation suggests that for lower channel doping below 10²³ m⁻³, fin width variation affects the threshold voltage most. Whereas when the doping is higher than 10²³ m⁻³, both the thickness and dielectric constant of the oxide material have strong effects on threshold voltage (0.05 V/nm oxide thickness and 0.01 V/per unit change in κ). Copyright © 2014 John Wiley & Sons, Ltd.     

A 1.2 V 83 dB DR single‐ended input SC ΔΣ modulator including a large‐swing analog buffer for portable ECG applications

This study proposes a subsystem consisting of an analog buffer and a single‐ended input to a fully differential ΔΣ modulator to obtain low‐power consumption for portable electrocardiogram applications. With the proposed subsystem, the need for an inverting amplifier is avoided, and low‐power consumption is achieved. The ΔΣ modulator with a second order, 1 bit, and cascade of integrators feedforward structure consumes a low power, in which an inverting and a non‐inverting path implement a single‐ended input to fully‐differential signals. A double sampling technique is proposed for a digital‐to‐analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low‐power consumption. Input‐bias and output‐bias transistors working in the weak‐inversion region are implemented to obtain an extremely large swing for the analog buffer. At a supply voltage of 1.2 V, signal bandwidth of 250 Hz, and sampling frequency of 128 kHz, the measurement results show that the modulator with a buffer achieves a 77 dB peak signal‐to‐noise‐distortion ratio, an effective‐number‐of‐bits of 12.5 bits, an 83 dB dynamic range, and a figure‐of‐merit of 156 dB. The total chip size is approximately 0.28 mm² with a standard 0.13 µm Complementary Metal‐Oxide‐Silicon (CMOS) process. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.008‐mm2, 35‐μW, 8.87‐ps‐resolution CMOS time‐to‐digital converter using dual‐slope architecture

This paper presents a high resolution time‐to‐digital converter (TDC) for low‐area applications. To achieve both high resolution and low circuit area, we propose a dual‐slope voltage‐domain TDC, which is composed of a time‐to‐voltage converter (TVC) and an analog‐to‐digital converter (ADC). In the TVC, a current source and a capacitor are used to make the circuit as simple as possible. For the same reason, a single‐slope ADC, which is commonly used for compact area ADC applications, is adapted and optimized. Because the main non‐linearity occurs in the current source of the TVC and the ramp generator of the ADC, a double gain‐boosting current source is applied to overcome the low output impedance of the current source in the sub‐100‐nm CMOS process. The prototype TDC is implemented using a 65‐nm CMOS process, and occupies only 0.008 mm². The measurement result shows a dynamic range with an 8‐bit 8.86‐ps resolution and an integrated non‐linearity of ±1.25 LSB. Copyright © 2016 John Wiley & Sons, Ltd.     

A low‐power small‐area 10‐bit analog‐to‐digital converter for neural recording applications

In vivo neural recording systems require low power and small area, which are the most important parameters in such systems. This paper reports a new architecture for reducing the power dissipation and area, in analog‐to‐digital converters (ADCs). A time‐based approach is used for the subtraction and amplification in conjunction with a current‐mode algorithm and cyclical stage, which the conversion reuses a single stage for three times, to perform analog‐to‐digital conversion. Based on introduced structure, a 10‐bit 100‐kSample/s time‐based cyclical ADC has been designed and simulated in a standard 90‐nm Complementary Metal Oxide Semiconductor (CMOS) process. Design of the system‐level architecture and the circuits was driven by stringent power constraints for small implantable devices. Simulation results show that the ADC achieves a peak signal‐to‐noise and distortion ratio (SNDR) of 59.6 dB, an effective number of bits (ENOB) of 9.6, a total harmonic distortion (THD) of ?64dB, and a peak integral nonlinearity (INL) of 0.55, related to the least significant bit (LSB). The ADC active area occupies 280µm × 250µm. The total power dissipation is 5µW per conversion stage and 20µW from an 1.2‐V supply for full‐scale conversion. Copyright © 2010 John Wiley & Sons, Ltd.     

A 63‐dB gain OTA operating in subthreshold with 20‐nW power consumption

This paper presents a two‐stage bulk‐driven operational transconductance amplifier operating in weak‐inversion region. The proposed amplifier is upgraded using recycling structure, current shunt technique, positive feedback source degeneration and indirect frequency compensation feedback to enhance transconductance under a reasonable stability. Combining these approaches leads to an ultra‐low‐power high performance amplifier without increasing power dissipation compared to the conventional one. Simulation results in 0.13‐µm complementary metal–oxide–semiconductor technology show the proposed structure achieves a 63‐dB DC gain at 0.25‐V supply voltage with just 20‐nW power dissipation. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

DC–3 GHz low‐noise,flat‐gain‐response,and high‐linearity amplifier

This paper describes the design, fabrication, and testing of a DC–3 GHz ultra‐wideband low‐noise amplifier (LNA) using Avago ATF‐54143 enhanced‐mode pseudomorphic high‐electron mobility transistor. Negative feedback network is introduced to ensure unconditional stability of the LNA over the full waveband. Simulation results show that the LNA provides a gain varying between 14.872 and 14.052 dB, a noise figure (NF) of less than 2.2 dB, and voltage standing wave ratios (VSWRs) approaching 2. A high simulated output third‐order intercept point (OIP₃) of >30.2 dBm is achieved. In contrast, in 1‐dB bandwidth of DC–3 GHz, the measured gain is nominal at 13.10 dB. The obtained NF changes in a small range of 2–2.178 dB, and the measured VSWRs are no more than 1.64, which are better than obtained from simulation results. At the same time, OIP₃ at 1, 2, and 3 GHz is 30.3, 29.13, and 29.34 dBm, respectively, while the output at the 1‐dB compression point (P _1dB ) is 15.43, 14.83, and 14.33 dBm, respectively. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Programmable feedforward linearized CMOS OTA for fully differential continuous‐time filter design

In this paper, a feedforward linearization method for programmable CMOS operational transconductance amplifier (OTA) is described. The proposed circuit technique is developed using simple source‐coupled differential pair transconductors, a feedback‐loop amplifier for self‐adjusting transcoductance (g_m) and a linear reference resistor (R). As a result, an efficient linearization of a transfer characteristic of the OTA is obtained. SPICE simulations show that for 0.35µm AMS CMOS process with a single +3V power supply, total harmonic distortion at 1 V_pp and temperature range from ?30 to +90°C is less than ?49.3 dB in comparison with ?35.8 dB without linearization. Moreover, the input voltage range of linear operation is increased. Power consumption of the linearized OTA circuit is 0.86 mW. Finally, the OTA is used to design a third‐order elliptic low‐pass filter in high‐frequency range. The cut‐off frequency of the operational transconductance amplifier‐capacitor (OTA‐C) filter is tunable in the range of 322.6 kHz–10 MHz using the feedforward linearized OTAs with the digitally programmable current mirrors. Copyright © 2009 John Wiley & Sons, Ltd.     

67‐90 GHz broadband power detector with 3 GHz output bandwidth for on‐chip test of millimeter‐wave circuits

This paper presents the design of a compact and wide bandwidth millimeter‐wave power detector, integrated at the output of an E‐band power amplifier and implemented in a 55‐nm SiGe BiCMOS process. It is based on a nonlinear PMOS detector core, and its measured output voltage tracks the output power of the PA from 67 to 90 GHz. It provides an insertion loss lower than 0.2 dB, and its responsivity can be tuned between 8 and 17 V/W. The output bandwidth is bigger than 3 GHz, which allows built‐in self‐test when transmitting multigigabit millimeter‐wave signals.