A design methodology for power‐efficient reconfigurable SC ΔΣ modulators

This paper presents a methodology to design reconfigurable switched‐capacitor delta‐sigma modulators (ΔΣMs) capable of keeping their corresponding power efficiency figures constant and optimal for a set of resolutions and signal bandwidths. This method is especially suitable for low‐bandwidth, medium‐to‐high‐resolution specifications, which are common in biomedical application range. The presented methodology is based on an analytic model of all different contributions to the power dissipation of the ΔΣM. In particular, a novel way to predict the static power dissipated by integrators based on class A and class AB operational transconductance amplifier is presented. The power‐optimal solution is found in terms of filter order, quantizer resolution, oversampling ratio, and capacitor dimensions for a targeted resolution and bandwidth. As the size of the sampling capacitors is crucial to determine power consumption, three approaches to achieve reconfigurability are compared: sizing the sampling capacitors to achieve the highest resolution and keep them constant, change only the first sampling capacitor according to the targeted resolution, or program all sampling capacitors to the required resolution. The second approach results in the best trade‐off between power efficiency and simplicity. A reconfigurable ΔΣM for biomedical applications is designed at transistor level in a 0.18‐µm complementary metal–oxide–semiconductor process following the methodology discussed. A comparison between the power estimated by the proposed analytic model and the transistor implementation shows a maximum difference of 17%, validating thus the proposed approach. Copyright © 2014 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

A front‐end receiver with a dual cross‐coupling technique for MICS applications

This paper presents a front‐end receiver with a dual cross‐couple technique for Medical Implant Communication Services M applications, using a standard complementary metal‐oxide semiconductor process. A lower‐power design is achieved using a resistive feedback, g_m‐boosting technique along with a current reuse topology in the receiver's transconductance stage. In addition, a dual cross‐coupling configuration applied at the input stage increases overall gain performance and reduces power consumption. The measured power dissipation of the low‐noise amplifier is only 0.51 mW. The conversion gain of the receiver is 19.74 dB, while the radio frequency and local oscillator frequencies are respectively 403.5 and 393.5 MHz, and the LO power is 0 dBm. The chip exhibits excellent isolation below −70 dB from LO to intermediate frequency and LO to radio frequency. Copyright © 2016 John Wiley & Sons, Ltd.     

Programmable feedforward linearized CMOS OTA for fully differential continuous‐time filter design

In this paper, a feedforward linearization method for programmable CMOS operational transconductance amplifier (OTA) is described. The proposed circuit technique is developed using simple source‐coupled differential pair transconductors, a feedback‐loop amplifier for self‐adjusting transcoductance (g_m) and a linear reference resistor (R). As a result, an efficient linearization of a transfer characteristic of the OTA is obtained. SPICE simulations show that for 0.35µm AMS CMOS process with a single +3V power supply, total harmonic distortion at 1 V_pp and temperature range from ?30 to +90°C is less than ?49.3 dB in comparison with ?35.8 dB without linearization. Moreover, the input voltage range of linear operation is increased. Power consumption of the linearized OTA circuit is 0.86 mW. Finally, the OTA is used to design a third‐order elliptic low‐pass filter in high‐frequency range. The cut‐off frequency of the operational transconductance amplifier‐capacitor (OTA‐C) filter is tunable in the range of 322.6 kHz–10 MHz using the feedforward linearized OTAs with the digitally programmable current mirrors. Copyright © 2009 John Wiley & Sons, Ltd.     

Circuit and system design for an 860–960 MHz RFID reader front‐ends with Tx leakage suppression in 0.18 − µm CMOS technology

This paper presents an RF Front‐END for an 860–960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front‐end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front‐END contains a power amplifier (PA) in transmit chain and receive front‐end with low‐noise amplifier, up/down mixer, LP filter and variable‐gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18‐µm technology. The chip area is 2.65 mm × 1.35 mm including the bonding pads. The PA delivers an output power of 29 dBm and a power‐added efficiency of 24% with a power gain of 20 dB, including the losses of the bond‐wires. Copyright © 2011 John Wiley & Sons, Ltd.     

Low‐voltage bulk‐driven input stage with improved transconductance

A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk‐driven structures. The proposed input stage offers also extended input common‐mode range under low supply voltage in relevant to a gate‐driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common‐mode voltage stabilization and a latch‐up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.     

Analysis and implementation of a fourth‐order bandpass filter for R‐wave detection of an implantable cardiac microstimulator

This paper presents an ultra‐low‐power fourth‐order bandpass operational transconductance amplifier‐C (OTA‐C) filter for an implantable cardiac microstimulator used to detect the R‐wave of intracardiac electrograms. The OTA‐C filter fabricated by TSMC 0.35‐µm complementary metal–oxide–semiconductor (CMOS) technology is operated in the subthreshold region to save power under a supply voltage of 1 V. The current cancellation technique is adopted to reduce the transconductance of the amplifier. Through this, the low‐frequency OTA‐C filter can be realized by ultra‐low transconductance with on‐chip capacitors. Direct comparison to conventional RLC ladders replaced by OTA‐C circuits shows that the method of reducing the number of OTAs further diminishes power consumption. Design issues, including ultra‐low transconductance, linearity, and noise, are also discussed. Measurement results show that the low‐voltage, low‐power filter has a bandwidth between 10 and 50 Hz, third inter‐modulation distortion of ?40 dB, dynamic range of 43 dB, and power consumption of only 12 nW. The real electrocardiography signal is fed into the bandpass filter to verify the function of signal processing with the distribution of the R‐wave. Copyright © 2012 John Wiley & Sons, Ltd.     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

±0.18‐V supply voltage gate‐driven PGA with 0.7‐Hz to 2‐kHz constant bandwidth and 0.15‐μW power dissipation

A simple gate‐driven scheme to reduce the minimum supply voltage of AC coupled amplifiers by close to a factor of two is introduced. The inclusion of a floating battery in the feedback loop allows both input terminals of the op‐amp to operate very close to a supply rail. This reduces essentially supply requirements. The scheme is verified experimentally with the example of a PGA that operates with ±0.18‐V supply voltages in 0.18‐μm CMOS technology and a power dissipation of about 0.15 μW. It has a 4‐bit digitally programmable gain and 0.7‐Hz to 2‐kHz true constant bandwidth that is independent on gain with a 25‐pF load capacitor. In addition, simulations of the same circuit in 0.13‐μm CMOS technology show that the proposed scheme allows operation with ±0.08‐V supplies, 7.5‐Hz to 8‐kHz true constant bandwidth with a 25‐pF load capacitor, and a total power dissipation of 0.07 μW.     

Multiple output differential OTA with linearizing bulk‐driven active‐error feedback loop for continuous‐time filter applications

A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

A 1.2 V 83 dB DR single‐ended input SC ΔΣ modulator including a large‐swing analog buffer for portable ECG applications

This study proposes a subsystem consisting of an analog buffer and a single‐ended input to a fully differential ΔΣ modulator to obtain low‐power consumption for portable electrocardiogram applications. With the proposed subsystem, the need for an inverting amplifier is avoided, and low‐power consumption is achieved. The ΔΣ modulator with a second order, 1 bit, and cascade of integrators feedforward structure consumes a low power, in which an inverting and a non‐inverting path implement a single‐ended input to fully‐differential signals. A double sampling technique is proposed for a digital‐to‐analog converter feedback circuit to reduce the effect of the reference voltage, reduce the amplifier requirements, and obtain low‐power consumption. Input‐bias and output‐bias transistors working in the weak‐inversion region are implemented to obtain an extremely large swing for the analog buffer. At a supply voltage of 1.2 V, signal bandwidth of 250 Hz, and sampling frequency of 128 kHz, the measurement results show that the modulator with a buffer achieves a 77 dB peak signal‐to‐noise‐distortion ratio, an effective‐number‐of‐bits of 12.5 bits, an 83 dB dynamic range, and a figure‐of‐merit of 156 dB. The total chip size is approximately 0.28 mm² with a standard 0.13 µm Complementary Metal‐Oxide‐Silicon (CMOS) process. Copyright © 2016 John Wiley & Sons, Ltd.     

Enhanced active‐feedback frequency compensation with on‐chip‐capacitor reduction feature for amplifiers with large capacitive load

A large capacitive load amplifier with enhanced active‐feedback frequency compensation is proposed in this paper. The enhancement is achieved through using a wide‐bandwidth scalar circuit to increase the transconductance of the output stage so that the overall bandwidth of the amplifier can be extended considerably. Implemented in a standard CMOS 130‐nm technology, with a supply of 0.7 V and consuming 27 μA of current, the amplifier drives a load capacitor of 15 nF. No on‐chip resistor is needed; only a 0.91‐pF compensation capacitor is used to maintain stability. The achieved gain‐bandwidth product and phase margin are 1.28 MHz and 66.9°, respectively. Moreover, the slew rate is 0.263 V/μs. The active chip area is 0.0056 mm². Copyright © 2017 John Wiley & Sons, Ltd.     

gm‐Extraction for rail‐to‐rail input stage linearization

Transconductance of rail‐to‐rail input stages in low‐voltage operational amplifiers depends on the presence of a large common mode input signal. Corrections must be implemented in order to correct it. Nevertheless, techniques actually used, based on switching or feedforward, still give relevant deviation from the constant transconductance condition. In this paper we present a new architecture based on extraction and feedback to the gain control, directly of the value of the transconductance of the amplifier to be controlled. This quantity does not contain the signal to be amplified, and thus once fed back, it does not affect the overall stage gain. A ‘reciprocal’ circuit, which performs the 1/x mathematical function, is introduced in order to achieve this extraction. Copyright © 2005 John Wiley & Sons, Ltd.     

Common‐mode gain reduction technique and its applications

This paper proposes a common‐mode gain reduction technique and a new approach for a balanced‐type system design. Two design examples of a balanced‐type operational transconductance amplifier and a balanced‐type filter are given. The proposed scheme employs the proposed common‐mode gain reduction technique together with the common‐mode feedback (CMFB) network, which is used only to set a bias, to meet requirements of common‐mode rejection. Compared with the conventional method, which uses the CMFB that has a higher gain than the one used in the proposed scheme, the proposed method shows reduction in design complexities and relaxation of the stability conditions. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Design of a 1‐GSample/s 9‐b double sampling track‐and‐hold amplifier in BiCMOS technology

This paper gives a detail presentation of a fully pseudo‐differential open‐loop BiCMOS track‐and‐hold amplifier (THA) for 9‐b operation up to 1 GSample/s. The proposed THA not only uses a double sampling technique to increase the achievable sampling frequency by a factor of two, but also employs a linearization technique to reduce the gain dependence of the THA input stage upon the input level. Moreover, timing mismatch between the clock signals of the two interleaved paths is minimized by means of a timing mismatch insensitive clock generator controlled by a common master sampling clock. The post‐layout simulation results using TSMC 75 GHz f_T, 0.35‐µm SiGe BiCMOS technology show that the proposed architecture achieve a signal to noise and distortion ratio of 53.92 dB, equivalent to the effective number of bits of 8.66‐b for 58.11 MHz input frequency at 1 GSample/s. The power dissipation of the whole THA is 161.1 mW. Copyright © 2012 John Wiley & Sons, Ltd.     

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

This paper presents an improved topology for ultra‐low‐power complementary metal oxide semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain cells. The proposed CMOS‐DA can be applicable in low‐supply‐voltage applications, because of the use of folded gain cell's structure. The proposed DA decreases power consumption by employing the forward body biasing network, while maintains high gain. By using a gain‐peaking inductor at the gate of the transistor, the proposed DA structure achieved to the gain flatness in high frequencies while the bandwidth is improved as well. In addition, employing RC network at the body terminal improves the noise performance of the proposed DA. The DA architecture consists of three amplification stages. Detailed analysis is provided for the proposed folded cascode DA. According to the post‐layout simulation results of the proposed amplifier using a 0.13‐µm CMOS process, DA achieves power gain of 17.3 ± 0.8 dB in bandwidth of 14.5 GHz, a good input third‐order intercept point (IIP3) of +5.5 dBm. The minimum noise figure is 1.8–5 dB, and input and output return losses are less than −11.5 dB and −10 dB, respectively, and the proposed structure consumes 12 mW from a 0.5 V voltage supply. Copyright © 2016 John Wiley & Sons, Ltd.     

Variation‐aware widely tunable nanoscale design of CMOS active inductor‐based RF bandpass filter

This paper presents a novel design methodology for realizing a variation‐aware widely tunable active inductor‐based RF bandpass filter (BPF). The inductor‐less filter is designed and implemented using voltage differencing transconductance amplifier (VDTA) as an active building block and a grounded capacitor, thereby validating its suitability for fully integrated circuit applications. Digital ‘coarse’ tuning and analog ‘fine’ tuning are employed to achieve better frequency coverage. The designed filter exhibits a tuning range of 1.65–3.015 GHz and a 3‐dB bandwidth of 1400–122 MHz which translates into a quality factor of 1.17–24.71. It offers a voltage gain of 0–22.91 dB, noise figure of 28.16–28.95 dB, has a 1‐dB compression point of 2.50–2.478 dBm and draws 0.065–0.232 mW power from 1‐V power supply. Our proposed design shows a figure‐of‐merit of 82.08–91.27 dB, which is higher as compared to its counterparts available in the literature. The filter is implemented in 45‐nm CMOS technology node using metal gate and strained silicon. Copyright © 2017 John Wiley & Sons, Ltd.     

A 1.9‐GHz silicon‐on‐insulator CMOS stacked‐FET power amplifier with uniformly distributed voltage stresses

A 1.9‐GHz single‐stage differential stacked‐FET power amplifier with uniformly distributed voltage stresses was implemented using 0.32‐μm 2.8‐V thick‐oxide MOSFETs in a 0.18‐μm silicon‐on‐insulator CMOS process. The input cross‐coupled stacked‐FET topology was proposed to evenly distribute the voltage stresses among the stacked transistors, alleviating the breakdown and reliability issues of the stacked‐FET power amplifier in sub‐micrometer CMOS technology. With a 4‐V supply voltage, the proposed power amplifier with an integrated output coupled‐resonator balun showed a small‐signal gain of 17 dB, a saturated output power of 26.1 dBm, and a maximum power‐added efficiency of 41.5% at the operating frequency. Copyright © 2017 John Wiley & Sons, Ltd.     

Design of a 75‐nW, 0.5‐V subthreshold complementary metal–oxide–semiconductor operational amplifier

This work focuses on the subthreshold design of ultra low‐voltage low‐power operational amplifiers. A well‐defined procedure for the systematic design of subthreshold operational amplifiers (op‐amps) is introduced. The design of a 0.5‐V two‐stage Miller‐compensated amplifier fabricated with a 0.18‐µm complementary metal–oxide–semiconductor process is presented. The op‐amp operates with all transistors in subthreshold region and achieves a DC gain of 70 dB and a gain–bandwidth product of 18 kHz, dissipating just 75 nW. The active area of the chip is ≈0.057 mm². Experimental results demonstrate that well‐designed subthreshold op‐amps are a very attractive solution to implement sub‐1‐V energy‐efficient applications for modern portable electronic systems. A comparative analysis with low‐voltage, low‐power op‐amp designs available in the literature highlights that subthreshold op‐amps designed according to the proposed design procedure achieve a better trade‐off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd.