High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.     

A reconfigurable high ultimate rejection inductorless band‐pass filter by the use of N‐path passive mixers

In this paper, a band‐pass filter with a tunable bandwidth and the center frequency is introduced, which employs N‐path and N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The center frequency of the proposed filter is tunable from 0.1 to 1 GHz, while its bandwidth is also adjustable from 6% to 34% of the center frequency at 100 MHz. The passband ripple is reduced by applying a Miller compensation technique, resulting in a worst‐case ripple of only 1.6 dB over the entire tuning range. An additional eight‐path filter is also utilized at the input of the circuit, which highly improves the out‐of‐band rejection of the filter as well as its out‐of‐band linearity. The noise figure and the input return loss are, respectively, better than 5 and 10 dB, and depending on the desired center frequency, the total power consumption of the proposed filter varies from 41 to 70 mW.     

Structure generation and performance comparison of elliptic Gm‐C filters

Starting from a set of matrices describing a general G_m‐C filter topology, a procedure is developed for generating structures of lowpass filters. As the matrices and the filter topologies have a one‐to‐one correspondence, an algebraic method is used to identify filter topologies with desired properties, here, transfer functions with finite jω‐axis transmission zeros, specifically elliptic filters. Sensitivity expressions for these structures are derived and a performance comparison based on a set of chosen criteria is made. For a specified elliptic transfer function, filters with only grounded capacitors and those containing also floating capacitors emerge as alternative realizations, as are filters with a single input and those with distributed inputs. For third‐order functions, a detailed comparison is performed of leapfrog (LF) and inverse follow‐the‐leader‐feedback (IFLF), the most popular special cases, and of topologies that have also floating capacitors (LF_f, IFLF_f), as well as of a novel configuration that uses also distributed inputs (DI_f) and leads to a reduced element count. Design guidelines and restrictions are given, which follow from the derived results with focus on the circuits' sensitivity performance and other properties important for IC implementation. Copyright © 2004 John Wiley & Sons, Ltd.     

Universal current‐mode filters and parasitic impedance effects on the filter performances

In this letter, two universal current‐mode (CM) filters for simultaneously realizing low‐pass, band‐pass and high‐pass characteristics are proposed. Both of the presented filters can also realize notch and all‐pass responses with interconnection of the relevant output currents. They employ second‐generation current‐controlled conveyors (CCCIIs) and only grounded capacitors. They also have low active and passive element sensitivities along with electronically adjustable angular resonance frequency (ω₀) and quality factor (Q). Based on the first developed filter, the parasitic impedance effects of the conveyors on the filter performances are investigated in detail. Simulation results using SPICE simulation program are included to verify the theory. Copyright © 2007 John Wiley & Sons, Ltd.     

Tunable selective receiver front end with impedance transformation filtering

A highly selective impedance transformation filtering technique suitable for tunable selective RF receivers is presented in this paper. To achieve blocker rejection comparable with surface acoustic wave (SAW) filters, we use a two‐stage architecture based on a low‐noise transconductance amplifier (LNTA). The filter rejection is captured by a linear periodically varying model that includes band limitation by the LNTA output impedance and the related parasitic capacitances of the impedance transformation circuit. This model is also used to estimate ‘back folding’ by interferers placed at harmonic frequencies. Discussed is also the effect of thermal noise folding and phase noise on the circuit noise figure. As a proof of concept, a chip design of a tunable RF front end using 65 nm complementary metal‐oxide‐semiconductor (CMOS) technology is presented. In measurements, the circuit achieves blocker rejection competitive to SAW filters with noise figure 3.2–5.2 dB, out of band IIP3 > +17 dBm, and blocker P_1dB > +5 dBm over frequency range of 0.5–3 GHz. Copyright © 2015 John Wiley & Sons, Ltd.     

Balanced Gm‐C filters with improved linearity and power efficiency

A novel G_m‐C filter design technique is presented. It is based on floating‐gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G_m‐C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all‐pole G_m‐C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low‐power second‐order Butterworth G_m‐C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5‐µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley & Sons, Ltd.     

A simulation study of high‐order CMOS hyperbolic‐sine filters

This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and f_o = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

Microstrip bandpass filter design using split‐path method and optimized curvature corrections

Bandpass filters with wide pass‐band are an essential requirement in various equipments of satellite and defence communication sectors. Here a method of split‐path interactions is proposed to approximately predict the resonant frequency and topology of bandpass filters which otherwise fall under the category of heuristic designs. Curved transmission lines are often required to make filter structures physically compact; however, curvature effects create errors in the theoretical (design) prediction of resonant or central frequencies for bandpass filter design. Earlier propositions on curvature corrections had been considerably precise, but recent design standards demand even higher accuracies. The prime feature of this work is the use of a meta‐heuristic optimization (i.e. Particle Swarm Optimization) technique in curvature corrections for the first time which brings accuracies of over 99% in the corrected results. The split paths used in this design are suitably curved, with the proposed optimized curvature correction technique, so as to attain a compact size of the filter. The resulting filter has a low insertion loss of around −1.00 dB and a sharp stopband cut‐off. Fabrication was done on a FR4 microstrip substrate with a good agreement between measured and simulated results. Copyright © 2015 John Wiley & Sons, Ltd.     

On the transposition of Gm–C filters to DC stabilized log‐domain filters

High‐order log‐domain filters could be designed by transposing the already known linear‐domain G_m–C filter topologies to the corresponding topologies in the log‐domain. This is achieved by using a non‐linear transconductor configuration, where the output current is exponentially related to its input and output voltages. A drawback of the non‐linear transconductor configuration already introduced in the literature is that a number of the transposed log‐domain filter topologies suffer from DC instability, while in some others a DC offset current appears at their output. In order to eliminate the aforementioned problems a modified non‐linear transconductor configuration for transposing G_m–C filter topologies to log‐domain filter topologies is introduced in this paper. The achieved improvements are demonstrated through a number of log‐domain filter configurations derived using the already introduced and the proposed transposition schemes. Copyright © 2006 John Wiley & Sons, Ltd.     

A DC stabilized log‐domain nth‐order multifunction filter based on the decomposition of nth‐order HP filter function to FLF topology

The design of high‐order log‐domain filters can be easily accomplished by transposing already known linear‐domain G_m‐C filter topologies to their counterparts in the log‐domain through the employment of a set of complementary operators. To achieve the G_m‐C filter topologies, the multiple feedback approach is widely used due to its accrued advantages. In this paper a synthesis approach for the development of an nth‐order multifunction log‐domain filter comprising lowpass (LP), highpass (HP) and bandpass (BP) filter functions is proposed. The approach is based on the decomposition of nth‐order HP filter function to follow‐the‐leader‐feedback (FLF) topology. The design is simple and simultaneously achieves nearly all of the chief advantages. The design offers superior performance factors vis‐à‐vis the ones recently reported. To verify the high‐order behavior of the topology, a 5th‐order multifunction filter was designed and the achieved simulated results verify the theory. Copyright © 2008 John Wiley & Sons, Ltd.     

A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

A new fast‐lock,low‐jitter,and all‐digital frequency synthesizer for DVB‐T receivers

Lock time and convergence time are the most important challenges in delay‐locked loops (DLLs). In this paper we cover French very high frequency band with a novel all‐digital fast‐lock DLL‐based frequency synthesizer. Because this new architecture uses a digital signal processing unit instead of using phase frequency detector, charge pump, and loop filter in conventional DLL, therefore, it shows better jitter performance, lock time, and convergence speed than previous related works. Optimization methods are used to make input and output signals of the proposed DLL in phase. The proposed architecture is designed to cover all channels of French very high frequency band by choosing number of delay cells in signal path. Simulation has been done for 22–27 delay cells, and f_REF = 16 MHz, which can produce output frequency in range of 176–216 MHz. Locking time is approximately 0.3 µs, which is equal to five clock cycles of reference clock. All of the simulation results show superiority of the proposed structure. Copyright © 2013 John Wiley & Sons, Ltd.     

A mathematical method to realize complex poles in a high-order passive switched-capacitor filter

A high-order discrete-time IIR low-pass with complex poles using charge sampling is presented in a single-stage structure by using a mathematical strategy. In comparison with the analog complex-poles G_m-C filters, the proposed filter consumes lower power and has good linearity, and all of the tunings are implemented only by capacitor sizes. The proposed filter is a seventh-order Butterworth, but this method can be generalized to implement other complex pole filters like Tchebyshev and Elliptic. Post-layout simulation results in 130-nm complementary metal-oxide-semiconductor (CMOS) show an IIP3 of +18 dBm and a noise figure of 5 dB. The filter has a rejection of more than 110 dB in its stop band and consumes 1.5 mW with a 1.6-V supply voltage, and circuit occupies an about 0.12 mm² of silicon.     

IC‐constrained optimization of continuous‐time Gm–C filters

This paper presents an automated synthesis procedure for integrated continuous‐time fully‐differential G_m?C filters. Such procedure builds up on a general extended state‐space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. The proposed technique not only addresses the dynamic range optimization under power dissipation constraints, but also accounts for other relevant integrated circuit related features, such as transconductor decomposition in unitary instances, spread of capacitances and estimated area occupation, among other characteristics. The proposed approach, implemented in the MATLAB^® framework, can be also used as an exploratory tool to compare different circuit implementations for a given set of filter specifications. Copyright © 2010 John Wiley & Sons, Ltd.     

Programmable feedforward linearized CMOS OTA for fully differential continuous‐time filter design

In this paper, a feedforward linearization method for programmable CMOS operational transconductance amplifier (OTA) is described. The proposed circuit technique is developed using simple source‐coupled differential pair transconductors, a feedback‐loop amplifier for self‐adjusting transcoductance (g_m) and a linear reference resistor (R). As a result, an efficient linearization of a transfer characteristic of the OTA is obtained. SPICE simulations show that for 0.35µm AMS CMOS process with a single +3V power supply, total harmonic distortion at 1 V_pp and temperature range from ?30 to +90°C is less than ?49.3 dB in comparison with ?35.8 dB without linearization. Moreover, the input voltage range of linear operation is increased. Power consumption of the linearized OTA circuit is 0.86 mW. Finally, the OTA is used to design a third‐order elliptic low‐pass filter in high‐frequency range. The cut‐off frequency of the operational transconductance amplifier‐capacitor (OTA‐C) filter is tunable in the range of 322.6 kHz–10 MHz using the feedforward linearized OTAs with the digitally programmable current mirrors. Copyright © 2009 John Wiley & Sons, Ltd.     

Proposal of over 100‐GHz band waveguide switch

A filter bank consisting of switches and band‐pass filters is one method for configuring a spectrum analyzer preselector. A long‐life switch with high isolation is key to this development. We propose a novel horizontal‐moving waveguide switch designed for easy addition of ports compared to commercial rotating switches. The switch has a small gap between the fixed and moving parts with the gap surrounded by chokes. This configuration offers high isolation and long life. It also reduces the size of the filter bank. This paper describes 2 proposed switch prototypes for frequency ranges from 90 to 140 GHz and from 255 to 315 GHz. The measured switch isolation is better than 50 dB and the insertion loss is less than 3 dB for both prototypes.     

A 0.8‐V supply bulk‐driven operational transconductance amplifier and Gm‐C filter in 0.18 µm CMOS process

A low voltage bulk‐driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm‐C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third‐order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than ?40 dB over the tuning range of the transconductance, by applying 800 mV_ppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third‐order low‐pass Gm‐C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from ?1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.     

Application of direct synthesis techniques to customize filters with complex frequency response

Recently, direct synthesis techniques (DSTs) have been presented for filter synthesis. Unlike conventional synthesis techniques, DSTs derive the filtering polynomials of the filters to be synthesized directly in their own frequency domain. These filtering polynomials are real coefficient so that they might find applications in various fields. Furthermore, DSTs might be used to customize filters with a more complex frequency response, such as asymmetric frequency response or multi‐band frequency response. In this paper, DSTs are compared with some well‐known filter synthesis techniques. Then, the application of DSTs in the design of lumped‐element LC filters, distributed‐element filters, active RC filters, and infinite impulse response digital filters with complex frequency response is discussed. Some examples are presented for demonstration. Copyright © 2015 John Wiley & Sons, Ltd.     

On the design of multi notch filters

A methodology for designing FIR multi notch filters (NFs) derived from second‐order prototype IIR NFs is suggested. Rejection bandwidth for the designed filter can be controlled by suitable choice of ‘r’, the pole radius of the IIR prototype NFs. The suggested multi NF can also be adapted to eliminate second‐, third‐ and fourth‐order harmonics of periodic noise besides the fundamental noise frequency component. A special case when two notch frequencies ω₁ and ω₂ are such that [(cosω₁)(cosω₂) = ? 1/2] has also been discussed. The IIR multi NF design for this special case results in reduction of the number of multipliers without affecting the response of the desired NF. For the aforereferred condition, the required coefficients of impulse response of FIR multi notch filter get reduced to almost half in number resulting in reduced computations. The number of zero coefficients further reduces with increase in ‘r’ value. In addition, the frequency response becomes better, with reduced ripples in the pass bands, when ‘r’ is increased and length ‘L’ of the FIR NF is chosen appropriately. Copyright © 2010 John Wiley & Sons, Ltd.