Low‐power,low‐noise,active‐RC band‐pass filters using a ‘lossy’ LP–BP transformation

A new and straightforward design procedure for simple canonical topologies of allpole, active‐RC, low‐selectivity band‐pass (BP) filters, with low sensitivity to component tolerances is presented. The procedure is primarily intended for discrete‐component, low‐power filter applications using just one amplifier for relatively high‐order filters. The design procedure starts out with an ‘optimized’ low‐pass (LP) prototype filter, yielding an ‘optimized’ BP filter, whereby the wealth of ‘optimized’ single‐amplifier LP filter designs can be exploited. Using a so‐called ‘lossy’ LP–BP transformation, closed‐form design equations for the design of second‐ to eighth‐order, single‐amplifier BP filters are presented. The low sensitivity, low power consumption, and low noise features of the resulting circuits, as well as the influence of the finite gain‐bandwidth product and component spread, are demonstrated for the case of a fourth‐order filter example. The optimized single‐opamp fourth‐order filter is compared with other designs, such as the cascade of optimized Biquads. Using PSpice with a TL081 opamp model, the filter performance is simulated and the results compared and verified with measurements of a discrete‐component breadboard filter using 1% resistors, 1% capacitors, and a TL081 opamp. Copyright © 2011 John Wiley & Sons, Ltd.     

Analytical synthesis of voltage‐mode even/odd‐nth‐order differential difference current conveyor and fully differential current conveyor II‐grounded resistor and capacitor universal filter structures

A complete definition of an odd/even‐nth‐order notch or band‐reject filter transfer function is presented. Based on the differences between the input voltage and (i) an nth‐order high‐pass; (ii) a traditional nth‐order notch; and (iii) an nth‐order all‐pass filtering transfer function, a systematic method has been proposed to derive a universal filter structure that can realize voltage‐mode odd/even‐nth‐order low‐pass, band‐pass, high‐pass, all‐pass and traditional notch filters. The intrinsic capability of voltage‐mode addition and subtraction of the two active elements, differential difference current conveyors and fully differential current conveyors, is used to advantage in the aforementioned synthesis procedure. Based upon the definition of an nth‐order notch or band‐reject filter transfer function proposed in this paper, the aforementioned universal one has been further extended to the newly defined nth‐order band rejection filter. The voltage and current tracking errors of the two active elements are compensated by varying the resistances of the proposed filter. Filtering feasibility, stability, component sensitivities, linear and dynamic ranges, power consumption, and noise are simulated using H‐Spice with 0.35 µm process. Compared to some of the recently reported universal biquads, the new one is shown to enjoy the lowest component sensitivities and the best output accuracy for all‐pass signals. Moreover, Monte Carlo and two‐tone tests for intermodulation linearity simulations are also investigated. Copyright © 2014 John Wiley & Sons, Ltd.     

A simulation study of high‐order CMOS hyperbolic‐sine filters

This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and f_o = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

Design of Sinh‐Domain filters using complementary operators

A new systematic method for designing Sinh‐Domain filters is introduced in this paper. This is achieved by employing an appropriate set of complementary operators, in order to transpose the conventional functional block diagram representation of each linear operation to the corresponding one into the Sinh‐Domain. The proposed method offers the benefits of facilitating the design procedure of high‐order Sinh‐Domain filters and of the absence of any restriction concerning the type and/or the order of the realized filter function. As an example, a third‐order Sinh‐Domain leapfrog filter is designed by employing the proposed set of operators. Two possible realizations are given and their performance has been evaluated and compared through simulation results. Copyright © 2011 John Wiley & Sons, Ltd.     

Multiple output differential OTA with linearizing bulk‐driven active‐error feedback loop for continuous‐time filter applications

A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

A methodology to design continuous‐time adaptive equalizers

Serial communications systems suffer from channel bandwidth limitations that result in eye closure and inter‐symbol interference. Adaptive equalization at the receiver is widely implemented to alleviate this, and a number of continuous‐time techniques aiming multi‐gigabit operation have been proposed. The operation of adaptive equalizers is based on signal filtering carried out by loop filters whose characteristics are usually given ad‐hoc after a trial and error process. This paper presents a unified analysis of the operation of continuous‐time adaptive equalizers that results in a general design methodology to select the frequency characteristics of the filters implemented in the adaptation loop. Using the proposed methodology, a novel adaptation loop filter combination incorporating two low‐pass filters is presented. Copyright © 2016 John Wiley & Sons, Ltd.     

MOS‐only reduced‐order ELIN cochlear channels: comparative performance evaluation

This paper introduces and applies practical area‐reduction techniques on the analogue, externally linear‐internally nonlinear, complementary metal‐oxide semiconductor (CMOS) implementation of a cochlear channel. This channel is constructed on the basis of the biomimetic auditory filter called One‐Zero Gammatone Filter, and it has been synthesised using ultra‐low power Class‐AB biquadratic filters, which employ MOS transistors that operate in their weak inversion regime. The realisation of linear capacitors with appropriately configured MOS transistors, the order reduction of the One‐Zero Gammatone Filter transfer function and the employment of hyperbolic sine companding filters can lead to area reductions that range from 61.8% up to 91.9% of the original size. Comparative simulation results highlight the trade‐offs between performance, linearity, noise and power consumption of the designs. Copyright © 2016 John Wiley & Sons, Ltd.     

A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

Ladder tuning‐block partitioned filters for simplified tuning

In this paper, we present a procedure for the design of low‐sensitivity, active‐RC filters that permits efficient functional tuning during the manufacturing process. Filters with finite zeros, such as elliptic (Chebyshev–Cauer) low‐pass filters are primarily considered, although the method can be applied to the design of other filters, e.g. allpole filters, as well. We show how to partition a given ladder filter into two parts. The first is a ladder filter of reduced order compared to the original; the second is a second‐ or third‐order active‐RC filter section, the ‘tuning block’, which, alone is used to tune the overall filter. The ladder, the components of which are fixed, provides most of the selectivity, while the cascaded tuning block determines the band‐edge characteristics and can be tuned relatively easily. A detailed design procedure for the filter partitioning is given. By obtaining a doubly terminated ladder filter, which is cascaded with a tuning block, both the inherent low sensitivity of the ladder and the tunability of the tuning block, are maintained. A Monte Carlo analysis of the partitioned filter demonstrates that the low sensitivity with respect to component tolerances, achievable by maintaining a doubly terminated ladder structure for the larger partitioned part of the filter, is preserved. Copyright © 2012 John Wiley & Sons, Ltd.     

Balanced Gm‐C filters with improved linearity and power efficiency

A novel G_m‐C filter design technique is presented. It is based on floating‐gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G_m‐C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all‐pole G_m‐C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low‐power second‐order Butterworth G_m‐C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5‐µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley & Sons, Ltd.     

Explicit design formulas for current‐mode leap‐frog OTA‐C filters and 300 MHz CMOS seventh‐order linear phase filter

The leap‐frog (LF) configuration is an important structure in analogue filter design. Voltage‐mode LF OTA‐C filters have recently been studied in the literature; however, general explicit formulas do not exist for current‐mode LF OTA‐C filters and there is also need for current‐mode LF‐based OTA‐C structures for realization of arbitrary transmission zeros. Three current‐mode OTA‐C structures are presented, including the basic LF structure and LF filters with an input distributor or an output summer. They can realize all‐pole characteristics and functions with arbitrary transmission zeros. Explicit design formulas are derived directly from these structures for the synthesis of, respectively, all‐pole and arbitrary zero filter characteristics of up to the sixth order. The filter structures are regular and the design formulas are straightforward to use. As an illustrative example, a 300 MHz seventh‐order linear phase low‐pass filter with zeros is presented. The filter is implemented using a fully differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. Simulations in a standard TSMC 0.18µm CMOS process with 2.5 V power supply have shown that the cutoff frequency of the filter ranges from 260 to 320 MHz, group delay ripple is about 4.5% over the whole tuning range, noise of the filter is 420nA/√Hz, dynamic range is 66 dB and power consumption is 200 mW. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐noise,low‐sensitivity,active‐RC allpole filters using impedance tapering

In this paper it is shown that active‐RC filters whose sensitivity to component tolerances can be minimized by impedance tapering, will also have low output thermal noise. It is shown that impedance tapering will also reduce output thermal noise in OTA‐C filters. Copyright © 2010 John Wiley & Sons, Ltd.     

IC‐constrained optimization of continuous‐time Gm–C filters

This paper presents an automated synthesis procedure for integrated continuous‐time fully‐differential G_m?C filters. Such procedure builds up on a general extended state‐space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. The proposed technique not only addresses the dynamic range optimization under power dissipation constraints, but also accounts for other relevant integrated circuit related features, such as transconductor decomposition in unitary instances, spread of capacitances and estimated area occupation, among other characteristics. The proposed approach, implemented in the MATLAB^® framework, can be also used as an exploratory tool to compare different circuit implementations for a given set of filter specifications. Copyright © 2010 John Wiley & Sons, Ltd.     

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f₀) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f₀ = 70 MHz with more than 39‐dB attenuation at f₀/2 and 2f₀. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mV_rms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm². Copyright © 2014 John Wiley & Sons, Ltd.     

Realization of log‐domain high‐order transfer functions using first‐order building blocks and complementary operators

High‐order log‐domain filters could be easily designed by using the functional block diagram (FBD) representation of the corresponding linear prototype and a set of complementary operators. For this purpose, lossy and lossless integrator blocks have been already introduced in the literature. Novel first‐order log‐domain highpass and allpass filter configurations, which are fully compatible with the already published integrator blocks, are introduced in this paper. These are realized using integration and subtraction blocks or a novel differentiation configuration. As a result, a complete set of first‐order building blocks would be available for synthesizing any arbitrary high‐order transfer function. In order to verify the correct operation of the proposed structures, the performance of the introduced highpass filters was evaluated through simulation results. In addition, a fifth‐order log‐domain bandpass filter was designed and simulated using one of the introduced first‐order highpass filter configurations. Copyright © 2006 John Wiley & Sons, Ltd.     

A proposal of a 3.3‐kV/6.6‐kV transformerless hybrid filter,and experimental verification based on a 200‐V laboratory system

This paper proposes a transformerless shunt hybrid filter for harmonic compensation of a three‐phase six‐pulse diode rectifier, where the AC line‐to‐line voltage is 3.3 or 6.6 kV. The hybrid filter consists of a single tuned LC filter per phase and an active filter with a DC capacitor voltage as low as 300 or 600 V. The two filters are directly connected in series with each other without a transformer. The passive filter absorbs harmonic currents produced by the rectifier, whereas the active filter improves the filtering characteristics of the passive filter. The required rating of the active filter is much smaller than that of a conventional shunt active filter used alone. Another advantage is that no additional switching‐ripple filter is required for the active filter because the LC filter acts not only as a tuned LC filter around the seventh‐harmonic frequency but also as a switching‐ripple filter around 10 kHz. A feedforward control scheme is also proposed to improve the active filter performance. Experimental results obtained from a 200‐V, 5‐kW laboratory system and simulation results of a 3.3‐kV, 300‐kW system confirm the validity and effectiveness of the system. The hybrid filter gives satisfactory compensation performance, thus allowing us to put it into practical use. © 2003 Wiley Periodicals, Inc. Electr Eng Jpn, 146(2): 54–65, 2004; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10236     

Current‐mode filters based on current mirror arrays

A technique is proposed for obtaining current‐mode filters based on current mirror arrays that operate as unity gain current amplifiers. These amplifiers by properly driving capacitors realize active lossless integrators which are the basic active elements for the derivation of filters according to the leapfrog method. Due to the fact that both the structure of the amplifiers and the adapted method for filter design are simple, the proposed technique is attractive for filter design and implementation. A design and the implementation of two third‐order low‐pass filters are presented. The array of the amplifiers has been implemented in a 0.8 µm CMOS technology. Copyright © 2007 John Wiley & Sons, Ltd.     

On oscillation‐based test structures of active RC filters

The recently proposed oscillation‐based test structures of active RC filters assume ideal opamps and test switches. In this letter, feasibility case study of the oscillation‐based test structure of the resonant bandpass filter is presented in which non‐ideal characteristics of the employed opamps and MOS switches are considered. Based on the dominant pole model for the opamps, we derive expression for the minimum value of the resistance required to put the filter stage into oscillation and expression for the frequency of the undamped pole. Derived expressions describe the conditions for the implementation of the oscillation‐based test in practice. Copyright © 2001 John Wiley & Sons, Ltd.     

A New Control Method of Suppressing the DC‐Capacitor Voltage Ripple Caused by Third‐Order Harmonic Compensation in Three‐Phase Active Power Filters

This paper proposes a new control method suitable for active power filters, which can reduce the dc capacitor voltage ripple associated with the third‐order harmonic current compensation. The proposed method superimposes a negative‐sequence fundamental current on the compensating current to cancel out the active power ripple caused by the third‐order harmonic current. As a result, the proposed method has the capability to eliminate the dc capacitor voltage ripple oscillating at double the source frequency. Experimental results obtained by a 10‐kW three‐phase diode rectifier load verify the validity of the proposed method. The proposed method exhibits a small dc capacitor voltage ripple reduced to 43% of that using the conventional method.     

Square‐root domain linear transformation filters

A new systematic method for designing square‐root domain (SRD) linear transformation (LT) filter is introduced in this paper. For this purpose, a substitution table containing the SRD LT equivalent of each passive element has been introduced. The proposed equivalents have been realized by employing appropriate SRD building blocks with low‐voltage operation capability. As a design example, a 3rd‐order SRD LT filter has been realized and its performance has been evaluated through simulation results. In addition, the most important performance factors of the SRD filter have been compared with those achieved by the SRD filters derived according to the leapfrog, wave, and topological emulation methods. Copyright © 2010 John Wiley & Sons, Ltd.