A 4.8–6.8 GHz low phase noise LC VCO in 0.13‐µm CMOS technology

This letter presents a novel LC voltage controlled oscillator (VCO) supporting the high‐speed serial transmission standard of RapidIO in 0.13‐µm complementary metal‐oxide semiconductor technology. The low phase noise is achieved through several techniques including current source switching, parallel coupled negative transconductance cell, and varactor bias combination scheme. Measured results of proposed circuit show a low phase noise of ?120 dBc/Hz at 1 MHz offset from 6.25 GHz carrier and tuning range of 4.8 ~ 6.8 GHz (34.48%) while consuming 7.4 mW under the supply voltage of 1.2 V. Copyright © 2015 John Wiley & Sons, Ltd.     

Increasing power efficiency in the design of a low power and low phase noise CMOS LC oscillator

This study developed a local oscillator (LO) with low phase noise and low power consumption. The proposed oscillator core comprises a pair of cross‐coupled transistors, which are fed by another pair of transistors that injects current at moments close to the peak of output voltage. The position of the current injection transistors, which are inserted in series with the cross‐coupled transistors, affects the waveform of current injected into an inductive–capacitive (LC) tank. Installing a capacitor on the source node of the cross‐coupled transistors increases the current injected into the LC tank and thereby augments the output voltage amplitude and power efficiency of the LO. The resonator phase shift and Q can be corrected by adjusting the source capacitance, which filters noise. These changes reduce the phase noise to ?123.4 dBc/Hz at a frequency offset of 1 MHz and improve oscillator performance with a figure of merit equal to ?193.5 dBc/Hz. To evaluate the LC tank, a 5 GHz LO was simulated at 1.8 V power supply and 2.5 mW power consumption. The simulation was conducted using a practical 0.18 complementary metal–oxide–semiconductor model manufactured by the Taiwan Semiconductor Manufacturing Company. The simulation results confirmed the analytical findings.     

便携式场强测试仪参考环的低噪声设计

本文主要介绍了根据便携式场强测试仪第一本振要求对其参考环进行低噪声设计。首先介绍了环路滤波器带宽的设计;然后介绍了提高参考环输出频率再分频以降低相位噪声的方法。参考环工作时,采用频谱分析仪测试,电路的频带,单边带相位噪声和频率分辨率等指标完全满足第一本振的要求,并且稳定可靠,功耗低,取得了预期的效果。     

Towards minimum achievable phase noise of relaxation oscillators

A relaxation oscillator design is described, which has a phase noise rivaling ring oscillators, while also featuring linear frequency tuning. We show that the comparator in a relaxation‐oscillator loop can be prevented from contributing to 1/f² colored phase noise and degrading control linearity. The resulting oscillator is implemented in a power efficient way with a switched‐capacitor circuit. The design results from a thorough analysis of the fundamental phase noise contributions. Simple expressions modeling the theoretical phase noise performance limit are presented, as well as a design strategy to approach this limit. To verify theoretical predictions, a relaxation oscillator is implemented in a baseline 65 nm CMOS process, occupying 200 µm × 150 µm. Its frequency tuning range is 1–12 MHz, and its phase noise is L(100kHz) = ?109dBc/Hz at f_osc = 12MHz, while consuming 90 μW. A figure of merit of ?161dBc/Hz is achieved, which is only 4 dB from the theoretical limit. Copyright © 2012 John Wiley & Sons, Ltd.     

宽带低相噪分立VCO的设计

压控振荡器(VCO)在通信、雷达、测试仪器等领域中的应用非常广泛,但宽带调谐、低相噪一直是VcO设计的瓶颈.通过对负阻原理的分析,根据三极管的等效电路参数采用准线性法对最佳谐振元件进行了估算,从而提高了对VCO设计的准确性和时效性.由变容二极管对和PC电感组成的并联谐振网络,实现了宽带调谐、低相噪,并对三次谐波分量有所...     

Analysis and design of LC oscillators associated with frequency multipliers: a phase noise perspective

When a local oscillator signal generation system is based on an LC oscillator and a frequency multiplier, the question of determining the optimal multiplication factor is a key issue. In this paper, the problem is addressed in order to minimize the 1/f ² phase noise within a tuning range constraint. The analysis, with a practical graphical representation, reveals the oscillator phase noise dependence on the oscillating frequency in the transition from two different regimes, named the inductor‐limited quality factor and the capacitor‐limited quality factor. The results obtained enable the evaluation of the phase noise performance of systems based on a sub‐harmonic and super‐harmonic oscillators and how they compare with an oscillator in the fundamental mode. Crucial questions like the phase noise improvement that these systems can achieve are analytically answered. A design methodology is thus proposed and verified through measurements on a frequency source at 31 GHz, composed by a sub‐harmonic voltage‐controlled oscillator followed by an injection‐locked frequency tripler, dedicated to backhauling applications, designed on a BiCMOS process technology. The tuning range is 10%, and the phase noise at a 1‐MHz offset is −112 dBc/Hz. Copyright © 2017 John Wiley & Sons, Ltd.     

一种恒压输出的高功率因数开关电源设计

基于具有PFC功能的SA7527控制芯片,设计了一款恒压输出的高功率因数开关电源。在阐述系统工作原理的基础上,重点对单端反激拓扑结构中兼具储能电感作用的高频变压器这一核心部件进行了设计。实验研究结果表明该开关电源在输入电压宽范围变化的情况下,可实现稳定的电压输出,最高功率因数可达0.95。     

Survey of integrated‐circuit‐oscillator phase‐noise analysis

This tutorial distills the salient phase‐noise analysis concepts and key equations developed over the last 75 years relevant to integrated circuit oscillators. Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker–Planck equations for the phase/amplitude distributions of a resonant oscillator. The principal contribution of this work is the organized, unified presentation of eclectic phase‐noise analysis techniques, facilitating their application to integrated circuit oscillator design. Furthermore, we demonstrate that all these methods boil down to obtaining three things: (1) noise modulation function; (2) noise transfer function; and (3) current‐controlled oscillator gain. For each method, this paper provides a short background explanation of the technique, a step‐by‐step procedure of how to apply the method to hand calculation/computer simulation, and a worked example to demonstrate how to analyze a practical oscillator circuit with that method. This survey article chiefly deals with phase‐noise analysis methods, so to restrict its scope, we limit our discussion to the following: (1) analyzing integrated circuit metal–oxide–semiconductor/bipolar junction transistor‐based LC, delay, and ring oscillator topologies; (2) considering a few oscillator harmonics in our analysis; (3) analyzing thermal/flicker intrinsic device‐noise sources rather than environmental/parametric noise/wander; (4) providing mainly qualitative amplitude‐noise discussions; and (5) omitting measurement methods/phase‐noise reduction techniques. Copyright © 2013 John Wiley & Sons, Ltd.     

A linear,ultra wideband,low‐power, 2.1–5 GHz,VCO

A linear, Ultra Wideband, low‐power VCO, suitable for UWB‐FM applications is proposed, forming the main part of a UWB‐FM transmitter. The VCO is designed in TSMC 90thinspacenm digital CMOS process and includes a Source‐Coupled Multivibrator, used as current‐controlled oscillator (CCO) which generates output frequencies between 2.1 and 5 GHz and a voltage‐to‐current (V‐to‐I) converter which translates the VCO input voltage modulation signal to current. Two single‐ended inverter buffers are employed to drive either a differential or a single‐ended UWB antenna. The presented VCO is designed for 1 V power supply and exhibits a linear tuning range of 2.1–5 GHz, a differential output power of ?7.83 dBm±0.78 dB and low power consumption of 8.26 mW, including the output buffers, at the maximum oscillation frequency. It is optimized for a very high ratio of tuning range (81.69%) over power consumption equal to 9.95 dB. The desired frequency band of 3.1–5 GHz for UWB‐FM applications is covered for the entire industrial temperature range (?40 to 125^°C). Copyright © 2010 John Wiley & Sons, Ltd.     

具有功率约束的逆变器电源电压/功率统一控制模型研究

为了更有效和协调地控制逆变器,降低控制系统对参考电压的依赖,提出了基于电压相位控制的电源逆变器的统一控制方法。将逆变器控制为电压源,并控制逆变器输出电压的幅值以控制其输出功率不大于极限功率,同时控制逆变器输出电压的相位以控制逆变器的工作模式。电压相位控制为固定相位时,逆变器则工作于电压参考模式;电压相位随功率需要的变化而变化时,逆变器的工作模式则为功率跟踪模式。同时,逆变器两种模式间的转换过程平滑,这样消除了模式切换对电力系统的冲击。在Matlab/Simulink建立了仿真模型,并通过仿真验证了该模型的正确性。     

A new single‐phase high‐power‐factor converter with buck and buck–boost hybrid operation

In recent years, a wide variety of high‐power‐factor converter schemes have been proposed to solve the harmonic problem. The schemes are based on conventional boost, buck, or buck–boost topology, and their performance, such as output voltage control range in the boost and buck topology or efficiency in the buck–boost topology, is limited. To solve this, the authors propose a single‐phase high‐power‐factor converter with a new topology obtained from a combination of buck and buck–boost topology. The power stage performs the buck and buck–boost operations by a compact single‐stage converter circuit while the simple controller/modulator appropriately controls the alternation of the buck and buck–boost operation and maintains a high‐quality input current during both the buck and buck–boost operations. The proposed scheme results in a high‐performance rectifier with no limitation of output voltage control range and a high efficiency. In this paper, the principle and operation of the proposed converter scheme are described in detail and the theory is confirmed through experimental results obtained from 2‐kW prototype converter. © 2000 Scripta Technica, Electr Eng Jpn, 131(3): 91–100, 2000     

Design and implementation of switched coil LC‐VCOs in the GHz range using the self‐inductance technique

This paper presents the design and implementation of dual‐band LC‐VCOs in the GHz‐range featuring a switched coil LC‐tank. The proposed design exploits the self‐inductance technique. The design of the coil starts from simple considerations and back‐of‐the‐envelope calculations, then electromagnetic simulations are used to optimize the coil layout. The sizing of the switch and its impact on the VCO performance are addressed as well. The VCOs have been implemented in 65 nm CMOS technology. Good correlation between simulated and measured tuning range and phase noise is obtained for all designs, thus confirming the validity and robustness of the design methodology and coil models. Copyright © 2013 John Wiley & Sons, Ltd.     

Iron Loss Characteristics of Electrical Steel Sheet under Inverter Excitation by Power Semiconductor with Extremely Low On‐Voltage Property

In this study, it is demonstrated that the iron loss from the SiC‐MOSFET, which represents a new power semiconductor with an extremely low on‐voltage for electric machine drives, is almost the same as that from an Si‐IGBT, which is a conventional power semiconductor. In order to evaluate the iron loss characteristics when an SiC device is used, two single‐phase pulse width modulation inverters were built and used for the excitation of a ring made up of electrical steel sheet. One of the inverter employed an SiC‐MOSFET, and the other inverter employed an Si‐IGBT. The iron losses for the two inverters are compared.     

高渗透率下兼顾光伏出力和网损的配电网运行优化方法

针对高渗透率光伏接入的配电网电压越限和经济运行问题,提出了有功无功协调优化的方法。分析了电压约束条件下的光伏有功出力限值,研究了高渗透率光伏接入的配电网电压越限机理,提出了综合考虑光伏有功出力和网损差值的净出力指标,以最大净出力为目标函数,计及敏感节点电压约束,建立了光伏有功出力和网损的综合优化模型。算例分析验证了该方法的电压控制能力和优越经济性,且其经济性随光伏有功出力增大呈现“先增后减”变化特征;一般场景下优化模型运行于最大功率点的最小网损方式,极端场景下则调整少量光伏有功出力满足电压约束。     

A novel three‐phase soft‐switched converter with high power factor using a lossless snubber

Recently, three‐phase converters with high power factor, especially using the discontinuous current mode (DCM), have been studied as novel rectifier circuits instead of conventional converters. In this circuit, the current of reactor is zero at turn on because of operating on DCM. Then ZCS (Zero Current Switching) is achieved. However it is necessary to turn off the switch at the maximum current. Then the switching losses increase at higher switching frequency. Therefore, soft‐switching method using the lossless snubber is proposed. In this method, ZVS (Zero Voltage Switching) at the turn off can be achieved by a lossless snubber and ZCS at the turn on can be obtained by operating under the DCM. In this paper, the theoretical analysis, numerical analysis using PSPICE, and results of the experiments show the verification of the proposed converter. © 1999 Scripta Technica. Electr Eng Jpn, 129(3): 69–76, 1999     

A high step‐up half‐bridge DC/DC converter with a special coupled inductor for input current ripple cancelation and extended voltage doubler circuit for power conditioning of fuel cell systems

This paper presents a high step‐up soft switched dc–dc converter having the feature of current ripple cancelation in the input stage that is specialized for power conditioning of fuel cell systems. The converter comprises a special half‐bridge converter and a rectifier stage based upon the voltage‐doubler circuit, in which the coupled‐inductor technology is amalgamated with switched‐capacitor circuit. The input current with no ripple is the principal characteristics of this topology that is achieved by utilizing a small coupled inductor. In addition, the low clamped voltage stress across both power switches and output diodes is another advantage of the proposed converter, which allows employing the metal–oxide–semiconductor field‐effect transistors with minuscule on‐state resistance and diodes with lower forward voltage‐drop, and thereby, the semiconductors' conduction losses diminish considerably. The inherent nature of this topology handles the switching scheme based on the asymmetrical pulse width modulation in order for switches to establish the zero voltage switching, leading to lower switching losses. Besides, because of the absence of the reverse‐recovery phenomenon, all diodes turn off with zero current switching. At last, a 250‐W laboratory prototype with the input voltage 24 V and output voltage 380 V is implemented to verify the especial features of the proposed converter. Copyright © 2015 John Wiley & Sons, Ltd. Copyright © 2015 John Wiley & Sons, Ltd.     

Design and performance study of phase‐locked loop using fractional‐order loop filter

The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

A faster phase frequency detector using transmission gate–based latch for the reduced response time of the PLL

In this paper, we present a new design of phase frequency detector (PFD) without reset, such that the blind zone and dead zone issues in the phase locked loop are annihilated. The PFD is designed using transmission gate–based latches, which produce UP and DOWN pulses only when there is a distinct phase difference between the reference and divided frequencies. Thus, the continuous pulses that get produced by the conventional NAND gate–based latches are avoided, leading to reduced power consumption of the PFD. The charge pump makes use of an op‐amp used as a buffer, to reduce the current mismatch. The loop filter used is of second order, and the voltage‐controlled oscillator is of conventional current–starved type. The divider makes use of true single‐phase clock latches. It was found that the phase locked loop with new design of PFD, compared with the conventional design, consumes 27% lesser power, and the lock time is decreased by 79%. In addition, it was found that the control voltage swing is reduced by 71%, which leads to much lesser spur content at the output of the voltage‐controlled oscillator.     

基于基相量循环移位的基波相位和频率高精度快速检测方法

基于基相量循环移位性质,指出采样序列由DFT新算法得到的基波幅角就是信号基波初相角,从而较简捷地获得了所要检测的含谐波电参量的基波分量的初相角,提高了基波相位的跟踪能力.基于等角度间隔采样原理,提出以前述所获得的基波初相角为反馈,构成相位跟踪闭环控制,以自适应调整采样间隔,实现了对被测信号频率的自动跟踪,并达到了减少频谱泄漏,提高基波检测精度的目的.DFT新算法具有递推特性,减少了计算量,实时性较好.上述结果用于有源电力滤波器中,可以精确检测出谐波及无功电流.仿真结果表明,所提出方法的正确性和有效性.