A common‐gate common‐source low noise amplifier based RF front end with selective input impedance matching for blocker‐resilient receivers

This paper presents an integrated wideband radio frequency front end with improved blocker resilience achieved through selective voltage attenuation at both input and output nodes of the low noise amplifier (LNA). The architecture differs from traditional LNA architectures where blockers are only attenuated at LNA output node. The proposed dual attenuation is attained by designing a low intrinsic input impedance common‐gate common‐source LNA with capacitive feedback, together with an N‐path filtering load. The capacitive feedback across the LNA ensures that the selective N‐path filtering profile at the LNA output is transferred to the LNA input nodes creating a selective input impedance. Consequently, the achieved front‐end input impedance is low at blocker frequencies and matched to the source impedance at the desired frequencies, creating the desired voltage attenuation for blockers. Further, a detailed theoretical analysis of proposed architecture is presented, which leads to clear design guidelines. Evaluated in a 28‐nm fully depleted silicon‐on‐insulator complementary metal oxide semiconductor (CMOS) process, front end is designed for wideband operation from 0.7 to 2.7 GHz. It consumes 11‐mA current from a 1‐V supply (excluding local oscillator (LO) buffering) and possesses a maximum noise figure of 5.1 dB. The front end demonstrates an out‐of‐band blocker compression point of ?1.5 dBm and out‐of‐band IIP3 of +14 dBm at a 100‐MHz offset from LO frequency. In comparison with a traditional common‐gate common‐source LNA‐based front end with wideband input impedance matching, the proposed front end achieves 3.5‐dB improvement in the blocker compression point at a 100‐MHz offset from LO.     

A novel low‐power receiver topology for RF and microwave applications

A novel low‐power receiver topology for radio‐frequency and microwave applications is presented. The proposed solution exploits a simple connection between the low‐noise amplifier and the subsequent mixer, which is realized by means of a high‐value resistor and a current mirror, achieving low noise and high linearity performance with an extremely low power consumption. The criteria for its optimal design are derived in order to accomplish the main trade‐offs among noise figure (NF), linearity, and current consumption performance. As a case of study, the new topology has been designed in the case of I/Q direct conversion receiver for IEEE 802.15.4 standard (ZigBee) applications at 2.45 GHz. The receiver exhibits a NF of 8.7 dB, 50Ω input impedance, a voltage gain of 26 dB, an input‐referred third‐order intercept point of ?13 dBm, and a power consumption of 8.6 mW, which represent one of the best performance trade‐offs obtained in the literature. Copyright © 2008 John Wiley & Sons, Ltd.     

Low‐Noise Fully Differential Amplifiers Using JFET‐CMOS Integration Technology for Smart Sensors

In this paper, CMOS‐based low‐noise amplifiers with JFET‐CMOS technology for high‐resolution sensor interface circuits are presented. A differential difference amplifier (DDA) configuration is employed to realize differential signal amplification with very high input impedance, which is required for the front‐end circuit in many sensor applications. Low‐noise JFET devices are used as input pair of the input differential stages or source‐grounded output load devices, which are dominant in the total noise floor of DDA circuits. A fully differential amplifier circuit with pure CMOS DDA and three types of JFET‐CMOS DDAs were fabricated and their noise performances were compared. The results show that the total noise floor of the JFET‐CMOS amplifier was much lower compared to that of the pure CMOS configuration. The noise‐reduction effect of JFET replacement depends on the circuit configuration. The noise reduction effect by JFET device was maximum of about − 18 dB at 2.5 Hz. JFET‐CMOS technology is very effective in improving the signal‐to‐noise ratio (SNR) of a sensor interface circuit with CMOS‐based sensing systems. © 2008 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

Ultra‐low‐noise large‐bandwidth transimpedance amplifier

Equivalent input current noise and bandwidth are the most relevant parameters qualifying a low‐noise transimpedance amplifier. In the conventional topology consisting of an operational amplifier in a shunt‐shunt configuration, the equivalent input noise decreases as the feedback resistor (R_F), which also sets the gain, increases. Unfortunately, as R_F increases above a few MΩ, as it is required for obtaining high sensitivity, the bandwidth of the system is set by the parasitic capacitance of R_F and reduces as R_F increases. In this paper, we propose a new topology that allows overcoming this limitation by employing a large‐bandwidth voltage amplifier together with a proper modified feedback network for compensating the effect of the parasitic capacitance of the feedback resistance. We experimentally demonstrate, on a prototype circuit, that the proposed approach allows to obtain a bandwidth in excess of 100 kHz and an equivalent input noise of about 4 fA/ , corresponding to the current noise of the 1 GΩ resistor that is part of the feedback network. The new approach allows obtaining larger bandwidth with respect to those obtained in previously proposed configurations with comparable background noise. Copyright © 2014 John Wiley & Sons, Ltd.     

Measurement of the source impedance of conducted emission using mode separable LISN: Conducted emission of a switching power supply

In the procedure for reducing conducted emissions, it is helpful to know the noise source impedance. This paper presents a method of measuring noise source complex impedances of common and differential mode separately. We propose a line impedance stabilization network (LISN) to measure common and differential mode noise separately without changing LISN impedances of each mode. With this LISN, conducted emissions of each mode are measured inserting appropriate impedances at the equipment under test (EUT) terminal of the LISN. Noise source complex impedances of switching power supply are well calculated from measured results. © 2002 Scripta Technica, Electr Eng Jpn, 139(2): 72–78, 2002; DOI 10.1002/eej1154     

Base coupled differential amplifier: a new topology for RF integrated LNA

A new topology of bipolar low noise amplifier (LNA) for RF applications, named base coupled differential (BCD), is presented. The proposed approach is compared by simulation against most classical topologies. The BCD configuration has the key advantage to join an integrated matching on a single‐ended input with a differential output. This is done by using down‐bond wiring, so that no integrated inductors are needed. The main advantages of this new topology are a drastic area reduction and an increased linearity range (or a reduced biasing current with the same linearity) together with a noise figure (NF) and voltage supply reduction. Particularly, the BCD LNA presented in this paper has been designed for 2.44GHz frequency operation. It is characterized by a NF of 1.93dB, a voltage gain (Av) of 19.5dB, an input impedance of 50Ωa third Input‐referred Intercept Point (IIP3) of ‐7.25dBm and a dissipated power (PD) equal to 19mW. Copyright © 2003 John Wiley & Sons, Ltd.     

Cross‐correlation‐based trans‐impedance amplifier for current noise measurements

This work proposes a cross‐correlation‐based trans‐impedance amplifier for current noise measurements in the low‐frequency range. The proposed solution is compared with the classical cross‐correlation trans‐impedance amplifier showing a lower background noise. Furthermore, a three‐step measurement method, based on the new trans‐impedance amplifier, is proposed to cancel the residual background noise. SPICE simulations and noise measurements performed on prototype circuits demonstrate the validity of the proposed approach. Copyright © 2008 John Wiley & Sons, Ltd.     

Competitive evolutionary algorithms for building performance database of a microwave transistor

In this work, the simultaneous trade‐off relations among the noise figure F, gain G_T, input V_in, and output V_out VSWRs of a microwave transistor operated at a certain (V_DS, I_DS, f) condition are obtained fast and as accurate as the corresponding analytical results using multiobjective optimization process without any need for expertise on the microwave device, circuit, and noise. Three powerful evolutionary algorithms, cuckoo search, firefly, and differential evolution, are implemented comparatively as a study case to obtain the trade‐off relations of a typical low‐noise amplifier transistor NE3511S02 for its operation between 9 and 17 GHz at V_DS = 2 V and I_DS = 10 mA. Finally, differential evolution is found as the most successful algorithm to demonstrate the typical trade‐off relations of NE3511S02. It can be concluded that these trade‐off relations being obtained by using a signal and noise model of the transistor enable performance database covering all the (F ≥ F_min, G_T, V_in ≥ 1, V_out ≥ 1) quadruples with their (Z_S, Z_L) termination pairs using solely an evolutionary optimization process. Thus, a small signal transistor can be identified by its performance database to be used in the design optimization of high‐performance low‐noise amplifiers with the full device capacity.     

Adaptive impedance matching system for downlink of passive semi‐ultra wideband ultra‐high frequency radio frequency identification tag

The input impedance of ultra‐high frequency radio frequency identification tag varies with the received power on the chip. It will induce impedance mismatch between the receiver antenna and microchip, thus drastically affect the performance of communication. In this paper, a low cost and fully integrated automatic impedance matching system was presented to solve this problem. It consists of two control loops for independent control of the real and imaginary parts of impedance. The first control loop realizes resistance correction using a parallel LC tuning network, whereas the second control loop achieves reactance compensation using a series LC tuning network. In both loops, the mismatch information is detected for direct control of the variable elements, varactors, which are tuned in a sequential manner. For unambiguous control of the resistance correction, the sign of the intermediate reactance is used as a secondary control criterion to enforce operation into a stable region. The functionality of the proposed automatic matching system was verified for different input impedances of a specifically semi‐ultra wideband ultra‐high frequency radio frequency identification tag as the available input power varies. The results indicate that all matched impedances are clustered around the target impedance 50 + j0 Ω after acquisition of both loops. Copyright © 2012 John Wiley & Sons, Ltd.     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.     

Synthesis‐oriented double‐loop feedback model

This paper presents a new feedback model that focuses on the synthesis rather than the analysis of feedback amplifiers. First, a single‐loop synthesis‐oriented feedback model is developed that enables the full synthesis of such amplifiers in a hierarchical and systematic way. This model is subsequently extended to a double‐loop synthesis model, so that also feedback amplifiers with a characteristic input or output impedance—employing two feedback loops—can be synthesized through the same systematic approach. That these new models are suitable for synthesis lies in the fact that they map directly to the circuit level, such that the intended, asymptotic behavior as well as the various individual contributors to the deviation from this intended behavior, like finite loop gain, non‐ideal input and output impedances of the forward gain block, direct feed‐through and attenuations outside the feedback loop(s), are clearly distinguished and can be assigned to the responsible sections of the network. For this purpose, the double‐loop synthesis model makes the transfers of the two feedback networks explicitly visible, so that it gives immediate insight in how to design these networks to get the required signal transfer and characteristic impedance. Copyright © 2017 John Wiley & Sons, Ltd.     

Integrated deterministic and stochastic simulation of electronic circuits: Application to large signal–noise analysis

The ability to model the effect of non‐negligible levels of white noise superimposed on a carrier is investigated when this signal–noise combination is fed to the input of an MMIC power amplifier. Transient simulation using stochastic differential equations is introduced here to handle large levels of noise of arbitrary frequency characteristics. The effectiveness of the modelling is ascertained by looking at measured gain‐compression plots at the output of the amplifier and comparing these with simulated results. It is found that increasing levels of noise introduce increased compression of the output power characteristic. Copyright © 2008 John Wiley & Sons, Ltd.     

Figures‐of‐merit genetic extraction for InGaAs lasers,SiGe low‐noise amplifiers,and ZnSe/Ge/GaAs HBTs

In this paper, we have successfully developed an intellectual parameter‐extraction methodology on the basis of a genetic algorithm (GA), involving the efficient search‐space separation and local‐minima‐convergence prevention schemes. Via an evolutionary simulation tool complemented with appropriate analytic equations, the enhanced approach has been applied to determine the significant figures‐of‐merit (FoMs), including internal quantum efficiency (η_i) as well as transparency current density (J_tr) of semiconductor lasers, minimum noise figure (NF_min) as well as associated available gain (G_A,assoc) of low‐noise amplifiers (LNAs), and DC as well as AC characteristics of heterojunction bipolar transistors (HBTs). For the first time, demonstrated FoM‐extraction results, which coincide well with the actually measured data, for state‐of‐the‐art InGaAs quantum‐well lasers, advanced SiGe LNAs, and abrupt ZnSe/Ge/GaAs HBTs are simultaneously presented to validate this multi‐parameter analysis and robust optimization. Copyright © 2011 John Wiley & Sons, Ltd.     

On the two‐port network analysis of common amplifier topologies

Using two‐port network transmission parameters, we derive exact expressions for the voltage/current gains and the input/output impedances of common amplifier topologies. The derived expressions are valid both for BJT and MOS‐based amplifiers and are independent of any particular small signal transistor model. Copyright © 2009 John Wiley & Sons, Ltd.     

A 14b 150 MS/s 140 mW 2.0 mm2 0.13µm CMOS A/D converter for software‐defined radio systems

This work proposes a 14 b 150 MS/s CMOS A/D converters (ADC) for software‐defined radio systems requiring simultaneously high‐resolution, low‐power, and small chip area at high speed. The proposed calibration‐free ADC employs a wide‐band low‐noise input sample‐and‐hold amplifier (SHA) along with a four‐stage pipelined architecture optimizing scaling‐down factors for the sampling capacitance and the input trans‐conductance of amplifiers in each stage to minimize thermal noise effect and power consumption. A signal‐insensitive 3‐D fully symmetric layout achieves a 14 b level resolution by reducing a capacitor mismatch of three MDACs. The prototype ADC in a 0.13µm 1P8M CMOS technology demonstrates a measured differential nonlinearity (DNL) and integral nonlinearity within 0.81LSB and 2.83LSB at 14 b, respectively. The ADC shows a maximum signal‐to‐noise‐and‐distortion ratio of 64 and 61 dB and a maximum spurious‐free dynamic range of 71 and 70 dB at 120 and 150 MS/s, respectively. The ADC with an active die area of 2.0mm² consumes 140 mW at 150 MS/s and 1.2 V. Copyright © 2010 John Wiley & Sons, Ltd.     

Design of 3.1 to 10.6 GHz ultra‐wideband flat gain LNA

In this paper, a new ultra‐wideband low‐noise amplifier (LNA) is proposed. The proposed LNA has flat gain and low noise figure (NF) in the frequency range of 3.1 to 10.6 GHz. To obtain higher gain, cascode architecture is used. In this design, to have a lower NF, the noise cancellation technique applies to the cascode architecture. In addition, to have better matching at the input and output, active feedback and matching transistors are used, which also leads to better NF. To have flat gain, RLC load is used. In the proposed LNA, only one inductor is used, which leads to the smaller chip area. The proposed circuit is designed in 90 nm CMOS technology. The simulation shows NF of between 1.62 and 2.1 dB, flat gain between 11.9 and 12 dB and power consumption of 11.72 mW in the frequency range of 3.1 to 10.6 GHz. The simulation results support the theoretical predictions. Copyright © 2017 John Wiley & Sons, Ltd.     

基于矢量网络分析仪的表贴式放大器噪声系数测试

传统的微波放大器噪声系数测试方法为基于噪声系数分析仪的Y因子测试法,在进行放大器的测试时需单独一次连接噪声系数分析仪测试其噪声系数.而表贴式放大器由于其引脚为非同轴结构,无法直接与测试仪器相连,其测试一直是微波器件的难题之一.以MINI公司ERA-1SM+表贴式放大器为例,从ZVA24矢量网络分析的噪声系数测试原理出发,设计出了合适的测试夹具和外围测试线路,实现了基于矢量网路分析的表贴式放大器噪声系数测试.     

DC–3 GHz low‐noise,flat‐gain‐response,and high‐linearity amplifier

This paper describes the design, fabrication, and testing of a DC–3 GHz ultra‐wideband low‐noise amplifier (LNA) using Avago ATF‐54143 enhanced‐mode pseudomorphic high‐electron mobility transistor. Negative feedback network is introduced to ensure unconditional stability of the LNA over the full waveband. Simulation results show that the LNA provides a gain varying between 14.872 and 14.052 dB, a noise figure (NF) of less than 2.2 dB, and voltage standing wave ratios (VSWRs) approaching 2. A high simulated output third‐order intercept point (OIP₃) of >30.2 dBm is achieved. In contrast, in 1‐dB bandwidth of DC–3 GHz, the measured gain is nominal at 13.10 dB. The obtained NF changes in a small range of 2–2.178 dB, and the measured VSWRs are no more than 1.64, which are better than obtained from simulation results. At the same time, OIP₃ at 1, 2, and 3 GHz is 30.3, 29.13, and 29.34 dBm, respectively, while the output at the 1‐dB compression point (P _1dB ) is 15.43, 14.83, and 14.33 dBm, respectively. © 2016 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A duplex current‐reused CMOS LNA with complementary derivative superposition technique

A duplex current‐reused complementary metal–oxide–semiconductor low‐noise amplifier (LNA) is proposed for 2.5‐GHz application. The duplex current‐reused topology with equivalent three common‐source gain stages cascaded is utilized to fulfil the low‐power consumption and high gain simultaneously. The complementary derivative superposition linearization technique with bulk‐bias control is employed to improve the linearity performance with large‐signal swing and to extend the auxiliary transistors bias‐control range. The proposed LNA is fabricated in a 0.18‐um 1P5M complementary metal–oxide–semiconductor process and consumes a 3.13‐mA quiescent current from a 1.5 V voltage supply. The measurement results show that the proposed LNA achieves power gain of 28.1 dB, noise figure of 1.64 dB, input P1dB and IIP3 of −19.6 dBm and 3.2 dBm, respectively, while the input and output return loss is 19.2 dB and 18.4 dB. Copyright © 2016 John Wiley & Sons, Ltd.     

Performance characterization of a microwave transistor subject to the noise and matching requirements

In this paper, the gain G_T of a microwave transistor is expressed analytically in terms of the mismatchings (V_in ≥ 1, V_out ≥ 1) at the ports, noise figure F ≥ F_min and the [z]‐parameter and noise parameters. Firstly, because the input termination Z_S determines the noise F ≥ F_min, thus the input termination Z_S is pre‐determined to lie on the tangent constant noise and available gain circles so that the maximum power delivery is ensured for the given noise. Then, a design configuration is constructed in the input impedance Z_in‐ plane covering the gain and the required input and output mismatch circles within the Unconditionally Stable Working Area for the predetermined input termination Z_S. Finally, the compatible (F ≥ F_min, G_T, V_in ≥ 1, V_out ≥ 1) quadrates for either required or optimum (V_in ≥ 1, V_out ≥ 1) couples are obtained with their (Z_S, Z_L) couples from the analysis of the design configuration. Furthermore, a case study is also presented for the full flexible performance characterization of a selected microwave transistor. It can be concluded that the near future microwave transistor is expected to be identified by performance data base built by its compatible (F ≥ F_min, G_T, V_in ≥ 1, V_out ≥ 1) quadrates and the (Z_S, Z_L) terminations within the device operation domain to overview all the possible low‐noise amplifier designs using the full device capacity. Copyright © 2015 John Wiley & Sons, Ltd.