Write Disturbance Modeling and Testing for MRAM

The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with the conventional March C-test algorithm. We also present a March 17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM chip has been designed and fabricated using a CMOS-based 0.18-mum technology. The proposed WDF model is justified by chip measurement results, with the march test results reported. Finally, specific MRAM fault behavior and test issues are discussed.     

A fully operational 1 kb variable threshold Josephson RAM

The first fully operational Josephson RAM in LSI level integration is described. The chip is designed as a 4 b× 256-word data RAM unit for a 4 b Josephson computer. A variable-threshold memory cell and the related memory architecture are used. They are so simple in structure that the fabrication can be accomplished using current Josephson junction technology. A directly coupled driver gate for a resistive bit line applies an accurate and stable driving current to the memory cell array. The RAM chip is fabricated with a 3 μm Nb/Al-oxide/Nb junction technology. For obtaining reliable RAM chips, a plasma-enhanced CVD (chemical-vapor-deposited) silicon dioxide layer is introduced for insulation between the ground plane and the base electrode. The thermal uniformity of the wafer is improved during the oxidation process for making a tunnel barrier. Installing this RAM chip together with a Josephson processor permitted the functions of a computer, including a memory access, to be successfully demonstrated. The access time was found to be 500-520 ps by measuring a test chip     

一种基于大容量数据记录仪的坏块管理设计

总结了目前基于FPGA的NAND Flash芯片数据记录仪常用的坏块处理方法,提出了一种基于FPGA的大容量数据记录仪的坏块管理方案.该方案利用FPGA内部RAM空间建立坏块地址信息存储区,通过坏块查询模块来查询存储区中的坏块信息,来确定当前存储块是否为坏块,若是坏块则跳过,从而避免对坏块的操作,实现了对Flash存储空间的有效管理.该方案只占用FPGA较少的内存资源,在大容量数据记录仪的坏块管理方面具有较大的优势.仿真分析表明,该方案可行,并取得了预期结果.     

A 0.5-GHz CMOS digital RF memory chip

In the application of digital RF memory (DRFM) chips for radar jamming, an RF signal is sampled, stored in random access memory (RAM) and later recreated from the stored data. A CMOS (l/SUB eff/=1 /spl mu/m) DRFM chip is described that integrates static RAM, control circuitry, and two channels of shift registers on a single chip. The sample rate achieved was 0.5 GHz. VLSI density was made possible by the low-power dissipation of quiescent CMOS circuits. An 8K RAM prototype chip has been built and tested.     

0.5-μm 2 M-transistor BiPNMOS channelless gate array

A channelless gate array has been realized using 0.5-μm BiCMOS technology integrating more than two million transistors on a 14-mm×14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to form the BiPNMOS gate. The gate is suitable for 3.3-V supply and achieves 230-ps gate delay for a two-input NAND with full-swing output. Added small-size MOS transistors in the BiPNMOS basic cell can also be used for memory macros effectively. A test chip with four memory macros-a high-speed RAM, a high-density RAM, a ROM, and a CAM macro-was fabricated. The high-speed memory macros utilize bipolar transistors in bipolar middle buffers and in sense amplifiers. The high-speed RAM macro achieves an access time of 2.7 ns at 16-kb capacity. The high-density RAM macro is rather slow but the memory cell occupies only a half of the BiPNMOS basic cell using a single-port memory cell     

A 126.6-mm2 AND-type 512-Mb flash memory with 1.8-Vpower supply

A 512-Mb flash memory, which is applicable to removable flash media of portable equipment such as audio players, has been developed. The chip is fabricated with a 0.18-μm CMOS process on a 126.6-mm² die, and uses a multilevel technique (2 bit/1 cell). The memory cell is AND-type, which is suitable for multilevel operation. This paper reports new techniques adopted in the 512-Mb flash memory. First, techniques for low voltage operation are described. The charge pump, control of pumps, and the reference voltage generator are improved to generate internal voltage stably for multilevel flash memory. Next, a method for reducing total memory cost in the removable flash media is described. A new operation mode named read-modify-write is introduced on the chip. This feature makes the memory system simple, because the controller does not have to track sector-erase information     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.     

An 8K/spl times/8 bit static MOS RAM fabricated by n-MOS/n-well CMOS technology

A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively.     

Design of a scalable pipelined RAM system

This paper describes a scalable pipelined RAM system (SPRAMS) for packet switching. The SPRAMS consists of a two-dimensional array of small memory blocks which are fully pipelined and communicate with adjacent blocks in three directions. The maximum delay of a small memory block becomes the cycle time of the chip. The array configuration is scalable for large memory size without the cycle time variation. It has an initial latency of N+3 cycles with an N×N array configuration. We have designed an experimental 200 MHz 4 kbit static RAM chip with the 4×4 array configuration of 256 bit SRAM blocks. It was fabricated in 0.8 μm single-poly double-metal CMOS technology. Experimental results describe the advantages of SPRAMS     

Board-level built-in self-repair method of RAM

This paper describes the method of built-in self-repairing of RAM on board, designs hardware circuit, and logic for the RAM’s faults self-repairing system based on FPGA. The key technology is that it utilizes FPGA to test RAM according to some algorithm to find out failure memory units and replace the faulty units with FPGA. Then it can build a memory that has no fault concern to external controller, and realizes the logic binding between external controller and RAM. Micro Controller Unit (MCU) can operate external RAM correctly even if RAM has some fault address units. Conventional MCS-51 is used to simulate the operation of MCU operating external memory. Simulation shows FPGA can complete the faulty address units’ mapping and MCU can normally read and write external RAM. This design realizes the RAM’s built-in self-repairing on board.     

Flash memory complexity

Driven by the demand for more versatile personal electronic devices such as cellular phones and handheld computers, flash memory has advanced rapidly to higher volume density and performance levels. Today, semiconductor manufacturers find a growing opportunity for more advanced flash memories delivered either as standalone flash devices; embedded as cores with logic in single-chip devices; or packaged as stacked dice with microcontrollers, logic, or static RAM. For flash manufacturers, however, success in these highly competitive markets requires tight control over the cost of test, despite rising device complexity. As flash memory grows in size, speed, and complexity, manufacturers are seeking more cost-effective, single-insertion test solutions capable of addressing resulting test challenges. With the development of new test architectures, manufacturers can more efficiently address emerging flash complexity using cost-effective, next-generation test platforms.     

A novel memory cell for multiport RAM on 0.5 μm CMOSSea-of-Gates

A novel memory cell circuit for multiport RAM on CMOS Sea-of-Gates (SOG) has been proposed. It contributes to the operation both at high speed and at low voltage. In addition, a fourfold read bit line technique is also proposed to reduce the access time. A multiport RAM generator with the novel memory cell has been developed. 2-port or 3-port RAM's with flexible bit-word configurations are available. Test chips containing seven generated RAM's were designed and fabricated on 0.5 μm CMOS SOG. The experimental results of the chip show that each RAM operates at over 1.4 V and that the address access time of the 3-port RAM (16b×256w) is 4.8 ns at 3.3 V     

Quadruply self-aligned stacked high-capacitance RAM using Ta2O5high-density VLSI dynamic memory

A new one-transistor, one-capacitor RAM cell structure called a Quadruply Self-Aligned Stacked High Capacitance (QSA SHC) RAM is proposed as a basic cell for a future one-million-bit VLSI memory. This cell consists of a QSA MOSFET and a Ta2O5capacitor stacked on it. By this cell, the ultimate cell area3F times 2Fcan be realized with sufficient operating margin. Here,Fis the minimum feature size. The basic cell was fabricated and its operation was experimentally verified. The leakage current of Ta2O5film was small enough for the storage capacitor dielectric. Using a3F times 4Fcell and a4Fpitch sense amplifier, a one-million-bit memory was designed with a 2-µm rule. A cell size of 6.5 × 8 µm², and a chip size of 9.2 × 9.5 mm²were obtained. The access time, neglecting the RC time constant of the word line, was estimated to be about 170 ns. Based on this design, it is argued that a future one-million-bit memory can be realized by QSA SHC technology with a 2-1-µm process. The mask set of the 1-Mbit RAM was actually fabricated by an electron-beam mask maker. A photomicrograph of the 1-Mbit RAM chip patterned by the mask set is shown. This chip was patterned not to get an operating sample but to show an actual chip image of the future 1- Mbit RAM. The area of each circuit block including storage array can be seen in this chip image.     

基于MSP430F149数字语音记录仪设计

介绍了一种基于单片机MSP430F149、语音信号处理DSP芯片D6571E11及大容量闪存进行语音编码压缩存储的数字语音记录系统。采用低功耗单片机及大容量存储器使系统可连续记录14h以上的语音信息,并且可自动存储语音记录起始时间信息,便于用户查阅和管理。     

A 1024-bit MNOS RAM using avalanche-tunnel injection

MNOS memory cells which consist of one MNOS transistor and two MOS transistors are incorporated into a fully decoded 1024-word by 1-bit random access memory (RAM) with nonvolatility. The features of the present nonvolatile RAM are: 1) by introducing a novel mode of write operation, electrical isolators, such as p-n junction isolation between the memory cells and the other circuits are not required, 2) stored data can last more than one year without any kind of external power supply, 3) the chip size of the memory is 3.60/spl times/3.61 mm/SUP 2/, 4) the read-access time is 600 ns and the write cycle time is 10 /spl mu/s-100 /spl mu/s.     

Design and application of a GaAs digital RF memory chip

The design and performance of a GaAs integrated memory/logic chip designed for digital RF memory (DRFM) applications is described. This chip, called a programmable delay-line element (PDLE), implements the basic DRFM storage and delay functions. The RAM-with-logic configuration combines a 4-kb static RAM with 750 logic gates, providing on a single chip the components for storage, address generation, demultiplexing, multiplexing, and control functions normally provided by a variety of separate chips. A distributed control organization, where the chip is configured to provide as outputs all the signals required as inputs to another identical chip, is used. Chips cascaded into strings implement the programmable delay lines required for DRFM systems. Problems associated with complex signal distribution networks are avoided since, within a string, signal distribution requires only local interconnections between adjacent chips. Correct operation of all functions was demonstrated in a four-chip string which provides a total memory capacity of 16 kb. The maximum sampling rate was 800 MHz, and power dissipation was approximately 2 W per chip     

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

A 1.8 V 2 Mb SPin-transfer torque RAM (SPRAM) chip using a 0.2 mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power nonvolatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bi-directional current writing to achieve proper spin-transfer torque writing of 100 ns, and parallelizing-direction current reading with a low-voltage bit-line for preventing read disturbances that lead to 40 ns access time.     

内存条的结构与应用研究

采用大容量的存储器扩大单片机数据空间，常用的器件有：RAM、FLASH RAM、NVRAM以及DRAM。其中，DRAM具有容量特点大、价格低的优点。介绍了内存条的刷新原理和工作时序，详细讨论了89C51单片机与内存条接口设计的方法。最后采用ispLSI1032进行了集成处理，简单可靠，可使单片机系统拥有大容量的数据存储空间。     

双口RAM在图像处理系统中的应用研究

基于图像处理系统实时性和大数据量冲突的问题,提出了在图像处理系统中使用双口RAM的方法。介绍了双口RAM的功能和特点,以IDT70V09芯片为例给出了图像处理系统中应用双口RAM的系统架构设计、硬件接口设计、系统软件设计以及FPGA和DSP对双口RAM操作软件的详细设计,并针对双口RAM的端口争用问题与解决方法进行了详细讨论,对系统的印制板设计和电路调试提出了建议。最后对图像处理系统进了功能测试,证明了采用双口RAM设计的系统的稳定性和可行性。