A 10-bit 200-MHz CMOS video DAC for HDTV applications

This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB’s, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm². When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.     

A power-efficient 10-bit 40-MS/s sub-sampling pipelined CMOS analog-to-digital converter

This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step.     

An efficient power reduction technique for CMOS flash analog-to-digital converters

An efficient power reduction technique for CMOS flash analog-to-digital converter (ADC) is presented. The presented technique adopts the procedure with a simple coarse comparison first followed by a finer comparison later. Our ADC design does not decrease the total number of comparators, though it is able to reduce the power consumption. Subject to time signal controlling, the manipulation is to interchangeably shut down the comparator sections for the coarse comparison function. Experimental results show that this new method consumes about 48.14 mW at 400 MHz with 3.3 V supply voltage in TSMC 0.35 μm 2P4 M process. Compared with the traditional flash ADC, our low power method can reduce up to 47.8% in power consumption. The DNL of our proposed flash ADC is 0.5 LSB, the INL is 0.7 LSB, and the ENOB is 5.75 bits. The chip area occupies 0.4 × 0.9 mm² without I/O pads.     

A 10 bit Current-Mode CMOS A/D Converter with a Current Predictor and a Modular Current Reference

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 m n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16–528 A, DNL and INL of ±0.5 LSB and ±1.0 LSB, conversion rate of 10 M samples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm×2.4 mm.     

An 8-bit 200-MSample/s Folding and Interpolating ADC in 0.25 mm2

This article is presented to describe an area-efficient CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application, which is fully compatible with standard digital CMOS technology. A modified MOS-transistor-only folding block contributes to a small chip area. At the input stage, offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio (SNDR). An INL/DNL of 0.77 LSB/0.6 LSB was measured. An SNDR figure of 43.7 dB is achieved at 4 MHz input frequencies when operated at full speed of 200 MHz. The chip is realized in a standard digital 0.18 μm CMOS technology and consumes a total power of 181 mW from 3.3 V power supply. The active area is 0.25 mm².     

A Fully Integrated Current-Steering 10-b CMOS D/A Converter with a Self-Calibrated Current Bias Circuit

A fully integrated current-steering 10-b CMOS Digital-to-Analog Converter with internal termination resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. For the purpose of reducing glitch noises, further, a novel current switch based on a deglitching circuit is proposed. The prototype circuit has been fabricated with a 3 V 0.35 μm 2-poly 3-metal CMOS technology, and it occupies 1350 × 750 μm silicon area with 45 mW power consumption. The measured INL and DNL are within 0.5 LSB, respectively. The measured SFDR is about 65 dB, when an input signal is about 8 MHz at 100 MHz clock frequency.     

A low power 10-bit CMOS cyclic D/A converter with an improved Johnson counter and a capacitor swapping technique

A 10-bit CMOS cyclic D/A converter based on an improved Johnson counter and a capacitor swapping technique is described. In order to reduce the capacitor mismatching errors, we propose that two capacitors are alternately swapped depending on the input data. Further, a half differential architecture to reduce offset errors and an improved Johnson counter are also discussed. With a 0.35 µm Samsung CMOS technology, the measured SFDR is about 65 dB, when the input frequency is 1 MHz at a clock frequency of 2 MHz. The power consumption is only 240 µW at 3.3 V power supply. The measured INL and DNL are within ±0.7 and ±0.7 LSB, respectively.     

A 10-bit 1.8 V 45 mW 100 MHz CMOS transmitter chip for use in an XDSL modem in a home network

This paper describes a 10-bit 1.8 V 45 mW 100 MHz transmitter chip (TX chip) that is fabricated using 0.18 μm 1P6 M CMOS technology for use in an xDSL modem in a home network. The chip is composed of a 10-bit segmented digital-to-analog converter (DAC) and a fully differential adaptive line driver (LD). In designing the DAC, the switched-current method is used to increase the conversion speed; the anti-process-variation current cell with threshold-voltage compensation is used to reduce the linearity error, and the current cell, with differential input and gain boosting, is used to minimize the feedthrough error and tapered error distribution. The circuit layout of the current source has four-phase symmetry, not only to increase the linearity but also to eliminate the gradient error. To design a fully differential adaptive LD, the feed-forward capacitor and quiescent current control circuit are used to reduce the zero-crossing distortion and to minimize the second-order harmonic. Additionally, the power efficiency is increased using an output-impedance matching circuit. Measurements reveal that, for a TX chip at a differential load of 100 Ω and a supplied voltage of 1.8 V, the efficient number of bits, operating frequency, output voltage, output current, power consumption, differential nonlinearity error and integral nonlinearity error are 9 bits, 100 MHz, ± 0.874 V, ± 10 mA, 45.8 mW, ?0.80 to +0.62 LSB, and ?0.92 to +0.82 LSB, respectively.     

Power efficient high-speed DAC for wideband communication applications

This paper demonstrates a power efficient design of high-speed Digital-to-Analog Converters (DACs) for wideband communication systems. For Wireless personal area network applications with a 250 MHz signal bandwidth, a 6 bit DAC capable of two times the Nyquist rate sampling is implemented in a current steering segmented 2 + 4 architecture optimized for power efficiency. Along with a proposed master-slave deglitch circuit, several circuit techniques are investigated to improve dynamic performances such as linearity. Implemented in a 0.18 um CMOS process, our DAC achieved a superior conversion performance over the state-of-the-arts, exhibiting integral nonlinearity of less than 0.27 LSB and differential nonlinearity of less than 0.15 LSB. Measured spurious free dynamic range for 251 MHz output signal is 40.92 dB, with total power consumption at 1 GS/s of 6mW, yielding a figure-of-merits of 78.3 pJ/(conversion step*W).     

High efficiency,high switching speed,AlGaAs/GaAs P-HEMT DC–DC converter for integrated power amplifier modules

This paper presents a high efficiency, high switching frequency DC–DC buck converter in AlGaAs/GaAs technology, targeting integrated power amplifier modules for wireless communications. The switch mode, inductor load DC–DC converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of negative coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency under a given duty cycle with a minimum penalty on the current ripple performance. The DC–DC converter is implemented in 0.5 μm GaAs p-HEMT process and occupies 2 × 2.1 mm² without the output network. An 8.7 nH filter inductor is implemented in 65 μm thick top copper metal layer, and flip chip bonded to the DC–DC converter board. The integrated inductor achieves a quality factor of 26 at 150 MHz. The proposed converter converts 4.5 V input to 3.3 V output for 1 A load current under 150 MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings.     

A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference

This paper proposes a 10 b 120 MS/s CMOS ADC with a PVT-insensitive current reference. The designed current reference shows a mean temperature drift of 35.2 ppm/°C in the temperature range from −25 to 100°C and a supply rejection of 1.1%/V between 1.6 and 2.0 V. The prototype ADC fabricated in a 0.18 μm 1P6M CMOS technology demonstrates a measured DNL and INL of 0.18LSB and 0.53LSB with a maximum SNDR and SFDR of 53 and 68 dB at 120 MS/s. The ADC with an active chip area of 1.8 mm² consumes 108 mW at 120 MS/s and 1.8 V while the proposed on-chip current reference consumes 0.35 mW with a die area of 0.02 mm².     

A 1.5 V 12-bit 16 MSPS CMOS Pipelined ADC with 68 dB Dynamic Range

A 1.5 V, 12-bit, 16 MSPS analog-to-digital converter was implemented in 0.25 μm 1P5 M standard CMOS process with MIM capacitors. The converter achieves a peak SNDR of 66.5 dB with 5.12 MSPS and that of 63.0 dB with 16.384 MSPS. The dynamic range is 68 dB under both sampling rates. The maximum INL of ±0.8 LSB and DNL of ±0.5 LSB were measured under 5.12 MSPS, while those of 16.384 MSPS decreased to ±3.1 and ±1.0 LSB, respectively. An embedded bandgap reference circuit that provides the conversion voltage range is also presented with 1.5 V supply voltage. The total power consumption of this converter was 138 mW under 16.384 MSPS or 97 mW under 5.12 MSPS. The total area of this chip is 2.8 × 2.5 mm. This chip was implemented without calibration or trimming approaches.     

Design of a 12-bit high-speed CMOS D/A converter using a new 3D digital decoder structure useful for wireless transmitter applications

In this paper a 12-bit Nyquist current-steering digital-to-analog converter (DAC) is implemented using TSMC 0.35 μm standard CMOS process technology. The proposed DAC is an essential part in baseband section of wireless transmitter circuits. Using oversampling ratio (OSR) for it leads to avoid use of an active analog reconstruction filter. The optimum segmentation (75%) has been used to get the best DNL and reduce glitch energy. This segmentation ratio guarantees the monotonicity. Higher performance is achieved using a new 3D thermometer decoding method which reduces the area, power consumption and the number of control signals of the digital section. Using two digital channels in parallel, helps reach 1 GHz sampling frequency. Simulations indicate that the DAC has an accuracy better than 10.7-bit for upcoming higher data rate standards (IEEE 802.16 and 802.11n), and a spurious-free-dynamic-range (SFDR) higher than 64 dB in whole Nyquist frequency band. The post layout four corner Monte-Carlo simulated INL is better than 0.74 LSB while simulated DNL is better than 0.49 LSB. The analog voltage supply is 3.3 V while the digital part of the chip operates with only 2.4 V. Total power consumption in Nyquist rate measurement is 144.9 mW. Active area of chip is 1.37 mm².     

A new pipelined analog-to-digital converter using current conveyors

A new pipelined analog-to-digital converter (ADC) using second-generation current conveyor (CCII) is presented. Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifier (OA). Experimental results show that the proposed CCII-based pipelined ADC can work at 12.5 MHz with a 7.3-bit resolution. The DNL is within −0.4 LSB and 0.4 LSB and INL is within −0.8 LSB and 0.8 LSB, respectively. The pipelined ADC is realized in TSMC 0.35 μm CMOS technology and consumes 29 mW under a 3.3 V power supply. The core size is 0.85×0.85 mm². Sing-Yen Wu received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2005. His current research interests include CMOS pipelined analog-to-digital converters and mixed-signal integrated circuit. Lu-Po Liao received the M.S. degree in the Department of Electronic Engineering from National Taipei University of Technology, Taipei, Taiwan, in 2003. His current research interests include analog integrated circuit design and mixed-signal integrated circuit design. Chia-Chun Tsai received the Ph.D. degrees in Electrical Engineering from National Taiwan University, Taipei, Taiwan, 1991. From 1989 to 2005, he served at the Department of Electronic Engineering, National Taipei University of Technology, Taipei, Taiwan. Since 2005 he has been with the Department of Computer Science and Information Engineering, Nanhua University, Chiayi, Taiwan, where he is a Full Professor. His current research interests include VLSI design automation and mixed-signal IC designs.     

An 80-MS/s 14-bit pipelined ADC featuring 83 dB SFDR

An 80-MS/s 14-bit pipelined analog-to-digital converter (ADC) is presented in this paper. After gain error and offset extraction from prototype measurement, the improved circuit achieves spurious free dynamic range (SFDR) of 82.9 dB and signal-to-noise-and-distortion ratio (SINAD) of 64.1 dB for a 30.5 MHz input, maintained within 6 dB performance deterioration up to 170 MHz input. Differential nonlinearity (DNL) is 0.66 LSB and integral nonlinearity (INL) is 2.5 LSB. Low-jitter clock amplifier and buffers with balanced loads are used to reduce the jitter and skew between different stages. An on-chip voltage reference generator is schemed with low impedance to reduce noise and spurs of reference signals. The ADC is fabricated in a 0.18-μm CMOS process with core area of 3.86 mm², and consumes 518 mW at 1.8 V supply.     

Low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range

A new technique for improving the performance of low-voltage folding ADC’s by extending the input range is presented. It is shown that by using both PMOS and NMOS differential pairs in the folding blocks, the overall input voltage range of the ADC can be increased to rail-to-rail. A novel self-adjustment method is also introduced to compensate for the different input–output characteristics of PMOS and NMOS differential pairs. A low voltage 8-bit 80 MSample/s folding/interpolating ADC is then designed and fabricated in a 0.18 μm CMOS process. Operating with a supply voltage as low as 1.2 V, measurements show an INL below ±0.55 LSB, SNDR of 43.5 dB at 80 MHz Sampling Frequency and power dissipation of only 30 mW.     

一种用于数模转换器的电流-电压转换电路

介绍了一种用于数模转换器的电流 电压转换电路。在数模转换器的负载电阻片内集成的情况下 ,利用文中提出的电流 电压转换电路 ,数模转换器实现了要求的宽摆幅电平输出 (全“0”输入时 ,输出低电平 - 3V ;全“1”输入时 ,输出高电平 3 5V)。整个数模转换器电路用 1 2 μm双层金属双层多晶硅n阱CMOS工艺实现。其积分非线性误差为 0 4 5个最低有效位 (LSB) ,微分非线性误差为 0 2LSB ,满摆幅输出的建立时间小于 1μs。该数模转换器使用± 5V电源 ,功耗约为 30mW ,电路芯片面积为 0 4 2mm2 。     

A novel ±0.5 V,high current drive,and rail to rail current operational amplifier

A current operational amplifier (COA) with very high current drive capability is presented in this paper. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3, and Level49 technology. Owing to the elaborately arranged components, the proposed circuit demonstrates very high frequency bandwidth, extremely high CMRR, high output impedance, and true rail to rail output voltage swing range while operating at very low power supply of ±0.5 V. The interesting results such as current drive capability of ±1 mA, high output impedance of 5 GΩ, wide gain bandwidth of 220 MHz, extremely high output voltage swing of ±0.45 V, which interestingly provides the highest yet reported output voltage compliance for current mode building blocks implemented by regular CMOS technology, low static power consumption of 159 μW, and very high CMRR of 155 dB is achieved utilizing standard CMOS technology. Full process, voltage, and temperature variation analysis of the circuit is also investigated in order to approve the well robustness of the structure. The transient stepwise and sinusoidal response analysis is also done to verify the proposed COA stability.     

A 14-bit intrinsic accuracy Q2 random walk CMOS DAC

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q² random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-μm CMOS process. The die area is 13.1 mm²     

A 12-b, 150 MHz Sample/s CMOS Current Steering D/A Converter with Gradient Error Compensation

This paper discusses a circuit of 12-b, 150 MHz Sample/s current steering DAC with hierarchical symmetrical switching sequences which will compensate gradient error. The circuit of 12-b DAC employs segmented architecture, the least significant bits (LSB's) steer a binary weighted array, while the most significant bits (MSB's) are thermometer decoded and steer a unary array. The measured differential nonlinearity and integral nonlinearity are ± 0.6 least significant bit (LSB) and ±0.9 LSB, respectively. The output spectrum of the DAC is −63 dB with an input frequency of 30 MHz at 150 MHz conversion rate. The circuit is fabricated in 0.5 μ μm, two-poly two-metal, 5.0 V, mixed-signal CMOS process and occupies 1.27 × 0.96 mm, when operating at 150 MHz Sample/s, it dissipates 91.6 mW from 5.0 V power supply which is much lower than those of [1]. Jinguang Jiang received the M.Sc. degree from Hunan University, Hunan, China, in 1998 and the PhD degree from Hunan University, Hunan, China, in 2003, all in Electrical Engineering. He is currently a Postdoctoral fellow of Control Science and Engineering in the Faculty of Electrical and Information Engineering at the University of Hunan. His interests are mode distinguish and intelligent system, intelligent signal process, low-power and low-voltage analog integrated circuits design. Bo Wang received the M.Sc. degree from Southeast University, China, in 1998. He is currently as a senior analog design engineer working at Caretta Integrated Circuits, Shanghai, China. His interests are high-speed analog IC design and analog system modeling and analysis. Yaonan Wang received the M.Sc. degree from Hunan University, Hunan, China, in 1991 and the Ph.D. degree from Hunan University, Hunan, China, in 1994, all in Control Theory and Control Engineering. He is currently a Professor and dean of school of Electrical and Information Engineering at the University of Hunan. He is engaged in research of intelligent control, intelligent signal process, image distinguish and its application.