FPGA动态可重构技术及其应用

本文介绍了ＦＰＧＡ动态可重构技术原理,探讨了其应用前景,并讨论了影响其实用化的有关技术难点。     

A 2-D motion detection model for low-cost embedded reconfigurable I/O devices

A low-cost reconfigurable embedded apparatus for two-dimensional (2-D) motion detection has been developed. This paper briefly outlines the embedded reconfigurable system architecture, and presents in-depth the 2-D motion detection model, which is directly mapped to reconfigurable hardware. Emphasis is placed on the hardware ability to adapt to individual needs of kinetically challenged persons by altering detection thresholds and delays, thus resulting into an efficient low-cost reconfigurable hardware implementation of the model. This paper also presents how the model detects complex motions through a vocabulary of simple motions, and how the system is trained to individual users' needs. Experimental results and integrated applications of the model for text processing are also presented.     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.     

高带宽I/O总线解决方案支持新一代嵌入式系统

随着通信与联网技术的飞速发展,每个组件对系统中其他组件的依赖程度日益明显。当每个组件的新性能稳定之后,其他系统组件必须同步前进,否则,组件性能的提高对于系统设计者而言就失去了意义。例如,当前I/O总线体系结构的滞后性能实际上正限制着目前微处理器性能的发挥。 HyperTransport　I/O技术是一种可扩展的体系结构,可大大增加现有总线体系结构上的带宽,并可通过替代传统总线和网桥来简化现有箱内连接。HyperTransport技术具有方便易用、扩展自如、速度迅速,以及经济高效等特     

FPGA集成高速I/O、SERDES和结构化ASIC

莱迪思半导体公司最近推出针对高端应用的LatticeSC系统芯片FPGA系列。莱迪思称,该产品具备理想的整体性能。LatticeSC FPGA采用了富士通的90纳米CMOS工艺技术和300毫米硅片制造,能够加速芯片至芯片、芯片至存储器、高速串行、背板及网络数据通道的连通性。     

I/O扩展电路GM8166在嵌入式锅炉系统中的应用

介绍了I/O扩展电路GM8166的功能和特点,结合该器件在嵌入式锅炉系统中的应用,侧重说明它通过串行输入并行输出、并行输入串行输出两种转换模式来完成锅炉32路数字输入和32路数字输出控制的I/O口扩展.     

基于嵌入式处理器指纹识别系统的设计和实现

研究采用嵌入式处理器实现指纹识别系统的软硬件设计方法,通过构造以微处理器AT91SAM7X256和MBF200指纹传感器模块为平台的硬件环境,实现了嵌入式指纹识别硬件系统的设计.微处理器选用内含丰富外设的AT91SAM7X256,降低了硬件成本.指纹识别系统选用μC/OS-Ⅱ作为嵌入式操作系统,指纹识别算法中主要介绍了基于图像匹配的指纹识别算法、基于Gabor函数的指纹图像增强算法和基于方向图滤波指纹特征提取算法等,实现了低成本,高可靠性多节点指纹识别系统的设计.     

基于嵌入式处理器指纹识别系统的设计和实现

研究采用嵌入式处理器实现指纹识别系统的软硬件设计方法．通过构造以微处理器AT91SAM7X256和MBF200指纹传感器模块为平台的硬件环境,实现了嵌入式指纹识别硬件系统的设计。微处理器选用内含丰富外设的AT91SAM7X256,降低了硬件成本。指纹识别系统选用μC／OS-Ⅱ作为嵌入式操作系统,指纹识别算法中主要介绍了基于图像匹配的指纹识别算法、基于Gabor函数的指纹图像增强算法和基于方向图滤波指纹特征提取算法等．实现了低成本,高可靠性多节点指纹识别系统的设计。     

基于DeviceNet的嵌入式I/O模块设计

DeviceNet与ModBus协议转换系统由DeviceNet主站,嵌入式I/O模块,ModBus从站三部分组成,实现DeviceNet与ModBus之间的数据交互。嵌入式I/O模块采用ARM7控制器LPC2129实现DeviceNet与ModBus之间的通信,同时以软件的形式实现了一个仅限组2的DeviceNet从站和一个ModBus主站。DeviceNet从站用来解码从DeviceNet主站端接收到的数据,解码后的数据由MCU通过另一个UART接口发送给ModBus从站。UART接口旨在向ModBus从站发送读/写指令。结果表明,基于DeviceNet总线的嵌入式I/O模块可以很好地与基于ModBus总线的设备进行通信。     

免费的I/O:改进FPGA时钟分配控制

同步数字系统中的时钟信号（如远程通信中使用的）为系统中的数据传送定义了时间基准。一个时钟分配网络由多个时钟信号组成,由一个点将所有信号分配给需要时钟信号的所有组件。因为时钟信号执行关键的系统功能,很显然应给予更多的关注,不仅在时钟的特性（即偏移和抖动）方面,还有那些组成时钟分配网络的组件。     

FPGA中的I/O时序优化设计

在数字系统的同步接口设计中，可编程逻辑器件的输入输出往往需要和周围新片对接，些时I/O接口的时序问题显得尤为重要。介绍了几种FPGA中的I／O时序优化设计的方案，切实有效的解决了I／O接口中的时序同步问题。     

65nm CMOS工艺中的高速多标准FPGA I/O接口设计

设计了一种现场可编程门阵列(FPGA)中使用的高速可配置的输入输出(I/O)接口电路。通过使用电平移位电路、互补自偏置差分放大电路(CSDA)等,该电路实现了包括低压差分信号(LVDS)在内的多种常见的接口协议标准。该电路同时具备可编程配置压摆率和可编程配置输出驱动电流的功能,同时为保证信号完整性,设计了数字阻抗匹配(DCI)模块。芯片使用SMIC 1P10M65nm CMOS工艺流片。测试结果表明,芯片核心电路在1.2V电压下能保证各种协议工作正常,输入输出信号延时、最大输出电流、最高工作速率等与仿真结果吻合,均达到设计指标要求。     

用Cyclone FPGA实现双倍数据率输入/输出接口

Cyclone系列芯片是美国Altera公司推出的低价格、高容量现场可编程门阵列器件(FPGA)，本文概速了他的主要特点，给出了其在与外部存储器接口时用到的双倍数据率输入／输出接口的设计方法和仿真结果，仿真结果表明，Cyclone系列芯片可有效的完成两倍数据率接口的功能．     

应用于抗辐照FPGA的多标准I/O电路设计

针对工业控制、航空航天等多种复杂的电磁辐射环境中对大规模FPGA器件及高速数据传输的迫切需求,设计了一种可应用于抗辐照FPGA的多标准I/O电路。该I/O电路中输入/输出寄存器均采用三模冗余(TMR)技术进行了抗辐照加固,能够支持14种电平标准,实现宽电压范围调节。该抗辐照FPGA抗单粒子翻转(SEU)大于37 MeV·cm2/mg。仿真及测试结果表明,该I/O电路满足设计要求。     

A dynamic partial reconfigurable system with combined task allocation method to improve the reliability of FPGA

Currently most FPGAs use SRAM-based technology, which are susceptible to faults from external electromagnetic radiation or produced by long-time internal overload operation. The dynamic partial reconfigurable (DPR) system, as an emerging technology, provides a promising way to solve this problem by reallocating the tasks in damaged resource areas to non-faulty regions at runtime. Based on such idea, an infrastructure for coordinately executing specialized hardware tasks on a reconfigurable FPGA is presented to achieve the flexibility for tolerating the occurring faults at runtime. Moreover, a method named MER-3D-Contact that combines the maximum empty rectangles (MER) technique with the adjacency heuristic is proposed to allocate tasks in the dynamical partial reconfiguration system for higher resource utilization, higher task acceptance ratio and lower fragmentation ratio. At last, experiments are carried out to evaluate the performance of the proposed system, results show that the proposed system can make the highest improvement 36% without damaged areas and the highest improvement 58% with damaged resources in terms of task acceptance ratio. Thus, the proposed system is expected a wide application in the field of more reliable FPGAs.     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

基于FPGA的嵌入式系统FLASH接口设计与实现

介绍了嵌入式系统中FPGA与FLASH接口的设计过程。利用Verilog HDL语言设计有限状态机完成对FLASH的编程操作,并在Modelsim中对设计结果进行仿真。实验证明该方法简单可靠。