Worst‐case execution time analysis for a Java processor

In this paper, we propose a solution for a worst‐case execution time (WCET) analyzable Java system: a combination of a time‐predictable Java processor and a tool that performs WCET analysis at Java bytecode level. We present a Java processor, called JOP, designed for time‐predictable execution of real‐time tasks. The execution time of bytecodes, the instructions of the Java virtual machine, is known to cycle accuracy for JOP. Therefore, JOP simplifies the low‐level WCET analysis. A method cache, which fills whole Java methods into the cache, simplifies cache analysis. The WCET analysis tool is based on integer linear programming. The tool performs the low‐level analysis at the bytecode level and integrates the method cache analysis. An integrated data‐flow analysis performs receiver‐type analysis for dynamic method dispatches and loop‐bound analysis. Furthermore, a model checking approach to WCET analysis is presented where the method cache can be exactly simulated. The combination of the time‐predictable Java processor and the WCET analysis tool is evaluated with standard WCET benchmarks and three real‐time applications. The WCET friendly architecture of JOP and the integrated method cache analysis yield tight WCET bounds. Comparing the exact, but expensive, model checking‐based analysis of the method cache with the static approach demonstrates that the static approximation of the method cache is sufficiently tight for practical purposes. Copyright © 2010 John Wiley & Sons, Ltd.     

用于WCET静态分析的MIPS处理器建模方法研究

为获得安全而紧致的WCET估计,需要考虑执行程序的目标处理器的体系结构特征．Cache、流水线等用于提高性能的技术已经广泛地应用于现代处理器中,如果在静态分析过程中不考虑它们带来的影响,必然会导致WCET过估计．以Petri网作为模型工具,以WCET分析为应用目标构造MIPS处理器的体系结构模型,该方法讨论了各种RISC处理器中常见的体系结构特征的抽象以及它们在Petri网模型中的表示方法．通过实验验证,指令序列在Petri网模型上的模拟执行时间与指令序列在DLXView模拟器上的测试结果具有一致性,表明构建处理器的体系结构Petri网模型是一种有效的指令序列执行时间的静态分析方法．     

嵌入式Java处理器的方法调用机制

Java语言和Java处理器在实时嵌入式系统开发中的应用受到广泛关注。传统Java虚拟机的方法调用机制采用动态装载迟解析的执行方式,使得最坏情况执行时间(WCET)难以预测。针对该问题,提出一种提前解析-微程序执行的改进方法。将传统方法调用中的符号引用转化为直接调用,以微程序的方式运行在硬件处理器上,使执行限制在可预知的时钟周期内。实验结果证明,改进方法调用机制在执行时间上满足线性关系,具备良好的WCET可预测性。     

一种基于抽象解释的WCET自动分析工具

利用基于抽象解释的变量值范围传播技术,提出了一种自动分析高级语言程序流信息的方法;并在白盒测试工具NPCA的基础上,利用该方法实现了WCET分析工具NPCA-WCET。     

基于简单反馈的混合静态/动态节能弱硬实时调度算法

随着能耗问题目益显著,节能实时调度成为实时调度领域研究的热点.由于混合静态/动态节能弱硬实时调度算法基于最坏情况执行时间计算任务的执行速度,因此限制了节能效果,文中针对这一问题,提出一种新算法,通过引入简单反馈机制,估计任务的实际执行时间,通过任务划分,降低任务的整体执行速度,延长执行时间,进而达到高效节能的目的.实验表明,当平均情况执行时间低于最坏情况执行时间较多时,新算法优于原始算法,最多可节能60%～70%,最少可节能约10%.算法的不足之处在于当平均情况执行时间接近最坏情况执行时间时,新算法比原算法更耗能.     

基于分布函数的程序执行时间的静态预估

CPU体系结构越来越复杂,令传统的程序最大执行时间分析（worse case execution time,WCET）方法越来越难准确估计出程序运行时间.而基于分布函数的WCET就是从概率角度,宏观上把握程序运行时间区间,绕过复杂的底层硬件特性.分别用贝塔分布和正态分布模拟8087指令的运行时间,进行指令叠加后用正态分布模拟整个程序的运行时间;实验结果表明,基于分布函数的程序执行时间预估方法是可行的;最后对估计出来的时间区间作了调整.     

Reducing the Upper Bound Delay by Optimizing Bank-to-Core Mapping

Nowadays, inter-task interferences are the main difficulty in analyzing the timing behavior of multicores. The timing predictable embedded multicore architecture MERASA, which allows safe worst-case execution time (WCET) estimations, has emerged as an attractive solution. In the architecture, WCET can be estimated by the upper bound delay (UBD) which can be bounded by the interference-aware bus arbiter (IABA) and the dynamic cache partitioning such as columnization or bankization. However, this architecture faces a dilemma between decreasing UBD and efficient shared cache utilization. To obtain tighter WCET estimation, we propose a novel approach that reduces UBD by optimizing bank-to-core mapping on the multicore system with IABA and the two-level partitioned cache. For this, we first present a new UBD computation model based on the analysis of inter-task interference delay, and then put forward the core-sequence optimization method of bank-to-core mapping and the optimizing algorithms with the minimum UBD. Experimental results demonstrate that our approach can reduce WCET from 4% to 37%.     

Scalable and precise refinement of cache timing analysis via path-sensitive verification

Hard real-time systems require absolute guarantees in their execution times. Worst case execution time (WCET) of a program has therefore become an important problem to address. However, performance enhancing features of a processor (e.g. cache) make WCET analysis a difficult problem. In this paper, we propose a novel analysis framework by combining abstract interpretation and program verification for different varieties of cache analysis ranging from single to multi-core platforms. Our framework can be instantiated with different program verification techniques, such as model checking and symbolic execution. Our modeling is used to develop a precise yet scalable timing analysis method on top of the Chronos WCET analysis tool. Experimental results demonstrate that we can obtain significant improvement in precision with reasonable analysis time overhead.     

面向AADL模型的存储资源约束可调度性分析

嵌入式实时系统在安全关键领域变得越来越重要,其广泛应用于航空航天.汽车电子等具有严格时间约束的实时系统中.随着嵌入式系统的复杂度越来越高,在系统开发的早期设计阶段就需要对其可调度性进行分析评估.系统中的存储资源会对可调度性产生一定影响,在抢占式实时嵌入式系统引入缓存后,任务的最坏执行时间可能发生变化.因此,分析缓存相关...     

On Schedulability Analysis of AADL Architecture with Storage Resource Constraint

Embedded systems have been widely applied in real-time automatic control systems, and most of these systems are safety-critical, for example, the engine control systems in an automobile and the avionics in an airplane. It is very important to verify the schedulability of such a real-time embedded system in its early design stages, so as to avoid unexpected loss for the debugging of architecture design problems. However, it has been proved to be a tough challenge to evaluate the schedulability of a Preemptive-Scheduling Real-Time (PSRT) system, especially when the constraints of system resources are taken into consideration. The cache memory built inside the processor is an exclusive-accessing resource shared by all the tasks deployed on the processor. In addition, the Cache-Related Preemption Delay (CRPD) caused by preemptive task scheduling will bring extra time to the execution time for all the tasks. Thus, the CRPD should be taken into consideration when the Worst-Case Execution Time (WCET) of tasks is estimated in a real-time system. A model-based evaluation and verification method of architecture schedulability, which is designed for priority-based PSRT systems, is proposed in this study to make cache resource constrained and CRPD related schedulability evaluation based on the AADL system architecture model. In the first step, the study enhances the property set of AADL storage elements to make it compatible with cache memory properties in a system architecture model. Secondly, the study proposes a set of algorithms to estimate the CRPDs of a task before it is completed; run system schedule simulation and construct the schedule sequence with the constraint of cache resources and CRPDs involved; and make WCET estimation of the tasks in such a CRPD considered, preemptive-scheduling execution sequence. Finally, the methods mentioned above are implemented within a prototype software toolkit, which is designed to make evaluation and verification of system schedulability within CRPD constraints. The toolkit is tested with a use case of aircraft airborne open-architecture intelligent information system. The result shows that, compared with the schedule sequence constructed without cache memory resource constraints, the WCET estimated for most tasks is extended, and the sequence order is changed. In some extreme cases, when CRPD is taken into consideration, some tasks are evaluated to be incompletable. The test shows that the method and algorithms proposed in this study are feasible.     

同步语言的时间可预测多线程代码生成方法

能够提供更强计算能力的多核处理器将在安全关键系统中得到广泛应用.但是,由于现代处理器所使用的流水线、乱序执行、动态分支预测、Cache等性能提高机制以及多核之间的资源共享,使得系统的最坏执行时间分析变得非常困难.为此,国际学术界提出时间可预测系统设计的思想,以降低系统的最坏执行时间分析难度.已有研究主要关注硬件层次及其编译方法的调整和优化,而较少关注软件层次,即时间可预测多线程代码的构造方法以及到多核硬件平台的映射.本文提出一种基于同步语言模型驱动的时间可预测多线程代码生成方法,并对代码生成器的语义保持进行证明;提出一种基于AADL(Architecture Analysis and Design Language)的时间可预测多核体系结构模型,作为本文研究的目标平台;最后,给出多线程代码到多核体系结构模型的映射方法,并给出系统性质的分析框架.     

An accurate worst case timing analysis for RISC processors

An accurate and safe estimation of a task's worst case execution time (WCET) is crucial for reasoning about the timing properties of real time systems. In RISC processors, the execution time of a program construct (e.g., a statement) is affected by various factors such as cache hits/misses and pipeline hazards, and these factors impose serious problems in analyzing the WCETs of tasks. To analyze the timing effects of RISC's pipelined execution and cache memory, we propose extensions to the original timing schema where the timing information associated with each program construct is a simple time bound. In our approach, associated with each program construct is worst case timing abstraction, (WCTA), which contains detailed timing information of every execution path that might be the worst case execution path of the program construct. This extension leads to a revised timing schema that is similar to the original timing schema except that concatenation and pruning operations on WCTAs are newly defined to replace the add and max operations on time bounds in the original timing schema. Our revised timing schema accurately accounts for the timing effects of pipelined execution and cache memory not only within but also across program constructs. The paper also reports on preliminary results of WCET analysis for a RISC processor. Our results show that tight WCET bounds (within a maximum of about 30% overestimation) can be obtained by using the revised timing schema approach     

A comparison of instruction memories from the WCET perspective

Hard real-time systems demand high performance in combination with a timing predictable program execution. The performance of a system in the worst-case, represented by its worst case execution time (WCET), highly depends on the design of the memory subsystem. In this paper we focus on the instruction memory hierarchy and quantify the impact of different on-chip instruction memories on the worst-case timing of the system. A function-based dynamic instruction scratchpad (D-ISP), an instruction cache, and static instruction scratchpads using basic-block-based and function-based assignment algorithms are compared. Therefore, we provide WCET bounds for systems with different on-chip instruction memories and different off-chip memory timings.We show that for small memory sizes a static instruction scratchpad usually outperforms the other memories in terms of the WCET estimate. However, with increasing memory sizes the D-ISP is able to reach lower WCET bounds. An instruction cache can only provide lower WCET bounds than the other memories, if no suitable assignment for the static instruction scratchpads is found or if the D-ISP suffers from thrashing or frequently loads unused code.     

一种实时Java处理器''''区域''''内存实现模型

Java实时规范（RTSJ）提出的‘区域’内存（Scoped Memory）既避免了垃圾回收对系统实时性的影响，又能充分利用内存空间，引起了众多研究人员的重视．本文讨论了‘区域’内存的实现及影响最坏情况下执行时间（WCET）的因素，并提出一种针对嵌入式实时Java处理器的‘区域’内存实现模型．该模型中非实时处理在字节码被执行之前完成，消除了运行时管理‘区域’内存对WCET的影响，在简化处理器实现的同时保证了运行时WCET的可预测性．     

Design and analysis of SIC: a provably timing-predictable pipelined processor core

We introduce the strictly in-order core (SIC), a timing-predictable pipelined processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC’s key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. We present a formal proof framework based on satisfiability modulo theories that is able to automatically verify SIC’s timing predictability. SIC preserves most of the benefits of pipelining: it is only about 6–7% slower than a conventional non-strict in-order pipelined processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

     

Worst-case execution-time analysis for embedded real-time systems

In this article we give an overview of the worst-case execution time (WCET) analysis research performed by the WCET group of the ASTEC Competence Centre at Uppsala University. Knowing the WCET of a program is necessary when designing and verifying real-time systems. The WCET depends both on the program flow, such as loop iterations and function calls, and on hardware factors, such as caches and pipelines. WCET estimates should be both safe (no underestimation allowed) and tight (as little overestimation as possible). We have defined a modular architecture for a WCET tool, used both to identify the components of the overall WCET analysis problem, and as a starting point for the development of a WCET tool prototype. Within this framework we have proposed solutions to several key problems in WCET analysis, including representation and analysis of the control flow of programs, modeling of the behavior and timing of pipelines and other low-level timing aspects, integration of control flow information and low-level timing to obtain a safe and tight WCET estimate, and validation of our tools and methods. We have focussed on the needs of embedded real-time systems in designing our tools and directing our research. Our long-term goal is to provide WCET analysis as a part of the standard tool chain for embedded development (together with compilers, debuggers, and simulators). This is facilitated by our cooperation with the embedded systems programming-tools vendor IAR Systems.     

The explicit token store

This paper presents an unusually simple approach to dynamic dataflow execution, called the Explicit Token Store (ETS) architecture, and its current realization in Monsoon. The essence of dynamic dataflow execution is captured by a simple transition on state bits associated with storage local to a processor. Low-level storage management is performed by the compiler in assigning nodes to slots in an activation frame, rather than dynamically in hardware. The processor is simple, highly pipelined, and quite general. There is exactly one instruction executed for each action on the dataflow graph. Thus, the machine-oriented ETS model provides new insight into the real cost of direct execution of dataflow graphs.     

服务体执行流模型中消息通信的时间可预测性分析

Minicore是基于服务体执行流模型的新型微内核,它有效的将操作系统中的存储模型和运行模型相分离.微内核的高度模块化的设计使Minicore对服务体(Minicore的基本单元)间的消息通信的依赖度极高.于是对于Minicore操作系统的时间可预测性分析也无可避免的依赖于通信模块的时间可预测性.本文的工作即是通过计算Minicore通信模块的WCET,分析消息通信的时间可预测性,为未来实现时间可预测的通信机制并分析Minicore的时间可预测性提供基础.对通信模块的WCET分析计算采用静态WCET分析中的基于路径的算法,应用到Minicore系统的通信模块,包括四个阶段:提取目标代码片段,程序控制流分析,处理器特征分析和WCET计算.基于WCET计算结果本文定义配置相关的时间可预测性(CIPr)作为评估消息通信时间可预测性的指标.     

An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications

Low power consumption and high computational performance are two important processor design goals for IoT applications. Achieving both design goals in one processor architecture is challenging due to their conflicting requirements. This paper introduces a reconfigurable micro-architectural level technique that allows a Reduced Instruction Set Computing (RISC) processor to support IoT applications with different performance and energy trade-off requirements. The processor can be reconfigured into either multi-cycle execution mode (low computational speed with low dynamic power consumption) or pipeline execution mode (high computational speed at the expense of high dynamic power), based on dynamic workload characteristics in IoT applications. Switching between modes is accomplished by exploiting the partial reconfiguration (PR) feature offered by the recent advancements in modern FPGAs. A RISC processor was designed based on the proposed micro-architectural level technique and implemented on FPGA as IoT sensor node. Experimental results demonstrate that the proposed technique with reconfigurable micro-architecture is able to significantly reduce the dynamic energy consumption, compared to conventional multi-cycle and pipeline only micro-architectures, while allowing better performance-energy trade-off in IoT applications.     

一种基于PID的实时控制与调度协同设计方法

针对实时控制领域中由于资源共享引起的控制系统性能下降问题，提出一种对延迟和抖动进行补偿的协同设计方法．讨论了协同设计中的周期分配问题，对一些变结构任务或混杂任务，采用任务周期动态调整的方法以适应其最坏执行时间的变化，并通过查询宏周期实例表，改进PID算法对延迟和抖动进行补偿．