可靠的防抖动电路

可靠的防抖动电路田凌生（山东省科学院自动化研究所，济南，２５００１４）图１示出了常见的用Ｄ触发器消除方波上升沿和下降沿有抖动的电路及其工作波形。电路中第一个Ｄ触发器和倒相门Ｇ、电容器Ｃ、电阻器Ｒ构成单稳延时器，只要它的延迟时间大于抖动的持续时间，则其...     

基于FPGA控制VGA显示的多通道数字示波器的设计

为了实现对O～1MHz的信号进行测量以及显示的目的,制作了基于SOPC技术的VGA显示数字存储示波器。采用硬件与软件相配合的设计方法,主要模块有基于FPGA的最小系统模块、信号调理电路模块、AD采样模块、触发电路模块、VGA显示模块、4×4矩阵键盘模块和RAM存储以及FLASH存储模块。具有模拟信号可进行任意电平触发、数字信号可使用上升沿和下降沿触发、存储回放、垂直灵敏度档位设置、扫描速度档位设置、VGA显示多个界面等特点。通过波形测量实验,得到较好的显示波形。     

瑞利散射多普勒测风激光雷达频率动态跟踪系统

基于瑞利散射的多普勒测风激光雷达在利用频率差分技术测量风场的过程中,激光脉冲频率随室温和谐振腔温度变化而产生抖动和漂移,给系统测量精度带来极大影响.为了解决激光频率长期漂移给风场测量带来的影响,设计了一种频率实时动态跟踪硬件电路.介绍了该硬件电路的设计思想、关键技术和核心器件的选取,并利用该硬件电路与米散射测风激光锁频...     

通用汽车公司GMW 3172-2018瞬态中断试验设备设计

目前实验室的瞬态中断试验设备无法满足通用汽车公司GMW 3172-2018对上升沿和下降沿的要求,为此研发了一种高速开关电路及开关瞬态中断的测试设备,通过分别在设备驱动电路的输入端和输出端三极管的位置增加滤波电路,提高了输出波形速度,且输出波形基本无过冲。当前设备最主要的功能包括:可编程通断、调制波形输出、单线中断测试、GMW 3172-2018中9.2.18节要求的测试、雷达波调制测试。测试设备体积小、重量轻、成本低,可用于汽车电子电器零部件涉及到的电性能测试,以及用来确定零部件的稳定性。     

开关线性复合式功率放大器波形发生电路设计

波形发生电路为开关线性复合式功率放大器的功率放大单元提供所需频率范围的柔性波形信号.介绍了一种基于直接数字频率合成技术的波形发生电路的设计方案.给出了系统设计的整体思路、主要功能模块电路的硬件电路设计及软件设计.设计中充分利用了单片机的控制管理功能和DSP快速处理能力,采用单片机作为波形发生电路的控制核心,DSP作为波形生成核心.通过对系统输出进行测试证明,该系统输出的波形信号具有较高的精度,可以满足开关线性复合式功率放大器对柔性信号的要求.     

2.5Gb/s/ch 0.18μm CMOS数据恢复电路

设计了一个应用于SFI-5接口的2.5Gb/s/ch数据恢复电路.应用一个延迟锁相环,将数据的眼图中心调整为与参考时钟的上升沿对准,因而同步了并行恢复数据,并降低了误码率.采用TSMC标准的0.18μm CMOS工艺制作了一个单通道的2.5Gb/s/ch数据恢复电路,其面积为0.46mm2.输入231-1伪随机序列,恢复出2.5Gb/s数据的均方抖动为3.3ps.在误码率为10-12的条件下,电路的灵敏度小于20mV.     

2.5Gb/s/ch 0.18μm CMOS数据恢复电路

设计了一个应用于SFI-5接口的2.5Gb/s/ch数据恢复电路.应用一个延迟锁相环,将数据的眼图中心调整为与参考时钟的上升沿对准,因而同步了并行恢复数据,并降低了误码率.采用TSMC标准的0.18μm CMOS工艺制作了一个单通道的2.5Gb/s/ch数据恢复电路,其面积为0.46mm^2.输入231-1伪随机序列,恢复出2.5Gb/s数据的均方抖动为3.3ps.在误码率为10-12的条件下,电路的灵敏度小于20mV.     

按键消抖电路瞬态分析和设计

分析了软件消抖存在输出信号下冲电平超出后续数字芯片输入电平范围容,易危害数字芯片,且按键闭合时信号下降速度过快易引起容性串扰等缺点。针对软件消抖电路的不足,分析了硬件消抖电路,建立了数学模型,仿真并实测了按键消抖电路的时域响应。针对硬件消抖电路中仅使用滤波电容消除按键抖动的方法,通过仿真和实测阐述了该方法反而会导致下冲持续时间更长,对后续电路危害性大。分析计算了在按键导线中串接电阻以消除下冲,仿真并实测了整个硬件消抖电路的瞬时响应,实测了硬件消抖电路按键按下和释放整个过程的时域波形,消除了按键抖动和下冲。     

一种新型低抖动快速锁定时钟稳定电路

介绍了一种新型低抖动快速锁定时钟稳定电路.该电路通过检测输入时钟信号的上升沿,产生一个尖峰脉冲和一个精确延迟半个周期的尖峰脉冲,共同组成一个稳定的低抖动时钟.该电路采用0.35 μm标准CMOS工艺库,在Cadence环境下进行仿真,在100 MHz输入时钟频率下,输出时钟抖动为56 fs,电路的功耗仅有35 mW.     

波形存贮器

在科学技术研究中往往需要对单次非周期和随机瞬态过程进行测试。例如:测量爆炸过程中的冲击波、应力波;声纳,超声波等冲击音响及残响;生物体的生理反应;物理化学的瞬态反应;电路的暂态特性;电器开关的浪涌电流;继电器触点的延迟抖动特性;材料的应变断裂试验等,这些被测信号都不能用普通示波器及记录仪所观测记录。为了测量上述各种单次非周期和随机的瞬态信号,六十年代末就开始研制和生产了一种新型的测量仪器——波形存贮器,亦称瞬态波形记录仪。特点波形存贮器的主要特点如下:1.能存贮捕获各种单次随机的瞬态波形。在传     

Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs

Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in SPICE simulations, however, results in long simulation time. Innovative simulation techniques based on a statistical simulation framework have been recently introduced to cosimulate deterministic and random jitter effects efficiently. This paper presents new improvements on this statistical simulation framework. In particular, we introduce an accurate jitter modeling technique which accounts for bounded jitter with arbitrary spectrum in addition to Gaussian jitter. We also present a rigorous approach to model duty cycle distortion (DCD). A number of I/O systems are considered as examples to validate the proposed modeling methodology.      

Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits

In this paper, we analyze the occurrence of jitter due to random and deterministic disturbances in nonautonomous current-mode logic circuits. First, we present an analytical model that explains the transformation of noise into jitter as a linear time-variant process, with its time-domain impulse response function and a frequency-domain system function. The model is then used to analyze jitter in two different circuits, with different sources of noise. In the first example, we use the model to predict jitter due to device noise in a frequency divider, and identify devices that are the main contributors to the jitter. In the second example, we examine jitter of a buffer with deterministic ground noise. Jitter predictions are compared to the results obtained through exhaustive simulation. According to the comparison, the method predicts jitter with an error of up to 3.4%.      

Transient ion disturbances in traveling wave tubes

It is well known that the presence of ions in the electron beam of a traveling wave tube (TWT) can lead to periodic variations in the output power, phase and the body (or helix) current. This has been referred to as ion noise or jitter. Recently, we have observed a different form of jitter, and while it is still observed as a small variation in the TWT output (typically <0.5 dB in power and 2° in phase), it is not periodic. We refer to this phenomenon as random jitter, since its random nature in time is a defining characteristic, Other characteristics include a relatively fast onset (~1 ms) and slow (~500 ms) recovery. It was found that random jitter was due to the spurious release of extremely small amounts of trapped gas inside the TWT. The source of the gas was identified and the problem was resolved. The observed level of fluctuations in power and phase had no effect on digital traffic and the small quantity of gas was found to have no measurable impact on cathode life     

相干合成系统的抖动对远场的影响

摘要：运用傅里叶光学分析法推导出系统抖动造成单个光源引入相位差时的远场光强表达式,以正六边形列阵为例分析了系统抖动对远场的影响,描绘了中心光斑能量与总能量的比值以及峰值光强随相差的变化曲线,考查了列阵中某个光源位相随即抖动的影响。研究表明系统抖动不但会引起了远场中心光斑的能量以及峰值光强的减小,而且还能使远场的对称性遭到破坏。     

Jitter Accumulation for Periodic Pattern Signals

It is important to accurately evaluate and reduce jitter accumulation in long-haul digital repeatered lines. Jitter accumulation caused by random pattern signals has already been analyzed. However, periodic pattern signals such as pseudorandom signals are usually used to measure jitter accumulation. This paper describes the difference between the jitter accumulation for both signals and the necessary conditions to accurately estimate jitter accumulation for random pattern signals by using periodic pattern signals. First, it is shown theoretically that systematic jitter for periodic signals saturates, showing a ripple pattern. The limit of increase is determined by the ratio of tank bandwidth and pattern repetition frequency. Up to a certain number of regenerators determined by the ratio, systematic jitter increases in rough proportion to thesqrt{N}slope. It is also shown that the equation to estimate random pattern jitter accumulation is determined by the measured value for periodic pattern signals. Second, jitter characteristics are simulated by optical signal circulating experiments. The results are in agreement with the analysis. In addition, the reduction effects on periodic signal jitter accumulation caused by timing signal delay and nonlinearity of the limiter in the timing circuit are shown.     

Spread spectrum clock Generator with delay cell array to reduce electromagnetic interference

In high-speed digital systems, most of the electromagnetic interference (EMI) from the system is caused by high-speed digital clock drivers and synchronized circuits. To reduce the EMI from the system clocks, spread spectrum clock (SSC) techniques that modulate the system clock frequency have been proposed. A conventional SSC generator (SSCG) has been implemented with a phase locked loop (PLL) by controlling a period jitter. However, the conventional SSCG with PLL becomes more difficult to implement at higher clock frequencies, in the gigahertz range, because of the random period jitter of the PLL. Furthermore, the attenuation of EMI is decreased due to the random period jitter of the PLL. To overcome the problems associated with the random period jitter, we propose an SSCG with a delay cell array (DCA), which controls the position of clock transitions with a triangular modulation profile. Measurement and simulation have demonstrated that the proposed SSCG with DCA is easier to implement and more effective in attenuating the EMI compared with the conventional SSCG with PLL. The proposed SSCG with DCA was implemented on a chip using a 0.35-/spl mu/m CMOS process and achieved a 9-dB attenuation of the EMI at 390 MHz.     

Practical measurement of timing jitter contributed by a clock-and-data recovery circuit

This paper describes a measurement of high-frequency jitter contributed by a clock-and-data recovery circuit. The contributed jitter is expressed with deterministic and random jitter terms and is given for a specific bit sequence. The measurement is illustrated on two multichannel CMOS serializer/deserializer chips applicable to 10-G Ethernet, 10-G Fibre Channel, and InfiniBand at per-channel rates of 2.5 and 3.125 GBaud.     

A Better Method than Tail-fitting Algorithm for Jitter Separation Based on Gaussian Mixture Model

Jitter is roughly defined as the timing shaking of the square waveforms output from phase locked loops. It consists of two parts: deterministic jitter and random jitter. Separating and identifying each jitter component are important in understanding the root cause of jitter and further in improving on phase locked loop design. A popular method for jitter separation is so-called Tail-fitting Algorithm. A better method than Tail-fitting Algorithm for separating deterministic jitter (DJ) and random jitter (RJ) from total jitter (TJ) is presented in this Letter. The new method targets directly on the original total jitter series, instead of the histogram. Histogram is dependent on bin number and is uncertain, but is inappropriately selected as the starting point of Tail-Fitting algorithm. Our method is based on Gaussian mixture model (GMM). The mathematical relationship between this model and the quantities of DJ and RJ is established. The concept of kurtosis is used to determine the order of GMM, thereby rendering our method fully automatic, highly efficient. Our method circumvents the most cumbersome difficulty in tail identification of Tail-Fitting Algorithm, because tails and peaks of the histogram, even after being filtered, are fundamentally ambiguously defined, both theoretically and practically. Our method also bypasses the problem of initial value selection.     

Spectral correlation of a digital pulse stream modulated by a cyclostationary sequence in the presence of timing jitter

Cyclostationarity is an inherent characteristic of many communication signals, which can be exploited for performing various signal processing tasks. Imperfections in the signal generation that affect the cyclic statistics of a signal may lead to a degradation in the performance of signal processing algorithms which make use of this cyclostationary behaviour. One typical source of imperfection encountered in digital signalling techniques is random jitter in the pulse timing. In this work, we systematically derive analytical expressions for the cyclic statistics of digital baseband signalling schemes in the presence of timing jitter, under the assumption that the generating wide sense cyclostationary data sequence and the stationary jitter process are statistically independent.     

Clock jitter generator with picoseconds resolution

The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220?MHz, a jitter with 4?ps resolution can be injected.