A novel area efficient on-chip RO-Sensor for recycled IC detection

Out of different types of counterfeit integrated circuits (ICs) present in the supply chain, recycled ICs are major threat to security and reliability of electronic components. Recycled ICs possess shorter lifetime and it is extremely difficult to distinguish a recycled IC in a group of fresh IC with similar functionality. Out of several recycled IC detection methodology, Ring Oscillator (RO) sensor based detection approach is most efficient, because of its simple design and can detect ICs used only for few days. In this paper, we proposed two different types of modified RO sensor with lower area overhead. First RO sensor accelerates the aging to improve the detection of recycled ICs which are used for few days. The second architecture uses current controlled configurable RO (C-CRO) to further improve the detection of recycled IC. The RO in both the proposed sensor is designed by using modified pseudo NMOS logic based inverter. The proposed inverter accelerates the aging caused by negative bias temperature instability (NBTI) and lower the impact of process variation (PV) to improve the rate of detection. Both the proposed RO sensors are simulated in 90 nm CMOS technology. The simulation result shows both the proposed sensor improves the rate of detection as compared to the conventional sensor.     

基于多项式拟合频率重构的物理不可克隆函数优化

近年来硬件安全不断受到挑战,具有不可预测性、随机性等特性的环形振荡器物理不可克隆函数(Ring Oscillator Physical Unclonable Function,RO PUF)可作为硬件安全重要的加密密钥方式,但通常原始RO PUF不满足加密密钥对随机性的要求。因此,提出了基于多项式拟合频率重构的PUF优化方法。首先,实现RO电路的硬宏设计并在现场可编程门阵列(Field Programmable Gate Array,FPGA)上进行实例化,从而获得RO阵列的频率数据;其次,针对原始响应的随机性较差的情况,通过统计分析其分布特征,利用多项式拟合法优化重构RO阵列频率;最后,采用熵密度值评估RO PUF响应的随机性。选用型号为Xilinx Artix 7103的FPGA板进行实验测试评估,结果表明所提方法不仅比原始RO PUF响应的随机性强,而且与随机补丁混合法(Random Patch Mixer,RPM)和基于回归的熵蒸馏法相比也具备更好的随机性。     

Improved Ring Oscillator PUF: An FPGA-friendly Secure Primitive

In this paper, we analyze ring oscillator (RO) based physical unclonable function (PUF) on FPGAs. We show that the systematic process variation adversely affects the ability of the RO-PUF to generate unique chip-signatures, and propose a compensation method to mitigate it. Moreover, a configurable ring oscillator (CRO) technique is proposed to reduce noise in PUF responses. Our compensation method could improve the uniqueness of the PUF by an amount as high as 18%. The CRO technique could produce nearly 100% error-free PUF outputs over varying environmental conditions without post-processing while consuming minimum area.     

强物理不可克隆函数的侧信道混合攻击

物理不可克隆函数（Physical Unclonable Function,PUF）凭借其固有的防篡改、轻量级等特性,在资源受限的物联网安全领域拥有广阔的应用前景,其自身的安全问题也日益受到关注.多数强PUF可通过机器学习方法建模,抗机器学习的非线性结构PUF难以抵御侧信道攻击.本文在研究强PUF建模的基础上,基于统一符号规则分类介绍了现有的强PUF侧信道攻击方法如可靠性分析、功耗分析和故障注入等,重点论述了各类侧信道/机器学习混合攻击方法的原理、适用范围和攻击效果,文章最后讨论了PUF侧信道攻击面临的困境和宜采取的对策.     

基于序列密码的强PUF抗机器学习攻击方法

物理不可克隆函数(Physical Unclonable Function, PUF)在信息安全领域具有极其重要的应用前景,然而也存在其自身安全受机器学习攻击等方面的不足。该文通过对PUF电路和密码算法的研究,提出一种基于序列密码的强PUF抗机器学习攻击方法。首先,通过构造滚动密钥生成器产生随机密钥,并与输入激励进行混淆;然后,将混淆后的激励通过串并转换电路作用于强PUF,产生输出响应;最后,利用Python软件仿真和FPGA硬件实现,并分析其安全性和统计特性。实验结果表明,当建模所用激励响应对(Challenge Response Pairs, CRPs)高达106组时,基于逻辑回归、人工神经网络和支持向量机的攻击预测率接近50%的理想值。此外,该方法通用性强、硬件开销小,且不影响PUF的随机性、唯一性以及可靠性。     

基于亚阈值电流阵列的低成本物理不可克隆电路设计

物理不可克隆函数(PUF)能够提取出集成电路在加工过程中的工艺误差并将其转化为安全认证的密钥。由于常用于资源及功耗都受限的场合,实用化的PUF电路需要极高的硬件利用效率及较强的抗攻击性能。该文提出一种基于亚阈值电流阵列放电方案的低成本PUF电路设计方案。亚阈值电流阵列的电流具有极高的非线性特点,通过引入栅控开关和交叉耦合的结构,能够显著提升PUF电路的唯一性和稳定性。此外,通过引入亚阈值电流的设计可以极大地提高PUF的安全性,降低传统攻击手段的建模攻击。为了提升芯片的资源利用率,通过详细紧凑的版图设计和优化,该文提出的PUF单元面积仅为377.4 μm2,使得其特别适合物联网等低功耗低成本应用场景。仿真结果表明,该文所提亚阈值电路放电阵列PUF具有良好的唯一性和稳定性,无需校准电路的标准温度电压下唯一性为48.85%;在温度范围–20～80°C,电压变动范围为0.9～1.3V情况下,其可靠性达到了99.47%。     

一种基于FPGA进位逻辑的RO PUF设计

物理不可克隆函数(PUF)作为一种可有效地应对硬件安全问题的电路结构,在近些年得到了广泛的关注.环形振荡器(RO)PUF由于不需要完全对称的布线方式,因此被认为是最理想的PUF结构之一.现有的ROPUF设计愈加复杂且需要"硬宏"来固定电路,这导致PUF的移植性很差.文章利用FPGA中固有的进位逻辑资源实现RO PUF,...     

PUF‐based solutions for secure communications in Advanced Metering Infrastructure (AMI)

Advanced metering infrastructure (AMI) provides 2‐way communications between the utility and the smart meters. Developing authenticated key exchange (AKE) and broadcast authentication (BA) protocols is essential to provide secure communications in AMI. The security of all existing cryptographic protocols is based on the assumption that secret information is stored in the nonvolatile memories. In the AMI, the attackers can obtain some or all of the stored secret information from memories by a great variety of inexpensive and fast side‐channel attacks. Thus, all existing AKE and BA protocols are no longer secure. In this paper, we investigate how to develop secure AKE and BA protocols in the presence of memory attacks. As a solution, we propose to embed a physical unclonable function (PUF) in each party, which generates the secret values as required without the need to store them. By combining PUFs and 2 well‐known and secure protocols, we propose PUF‐based AKE and BA protocols. We show that our proposed protocols are memory leakage resilient. In addition, we prove their security in the standard model. Performance analysis of both protocols shows their efficiency for AMI applications. The proposed protocols can be easily implemented.     

多频率段物理不可克隆函数

物理不可克隆函数(Physical Unclonable Functions, PUF)是一种用于保护集成电路芯片安全的新方法。传统的基于振荡器的PUF在产生响应过程中振荡器的振荡频率固定不变,因此存在着被攻击的隐患。该文提出一种新的利用多频率段的PUF(Multiple Frequency Slots based PUF, MFS-PUF)来解决这个问题,通过可配置的振荡器,每产生一位响应,振荡器的振荡频率便发生转移。在每一种振荡频率下,由于不可避免地制造差异,振荡器之间的频率会有微小差别,这些略有差异的频率组成了一个频率段(frequency slot),整个系统中则存在着多个频率段。各个频率段之间随机转变,相比于传统的基于振荡器的PUF,系统输入输出响应对(Challenge-Response Pairs, CRPs)的值更大,也更加不可预测,这使得攻击者使用建模攻击的复杂度大大增加,在保证了自身性能的同时增强了本身的安全性。     

基于人工神经网络特征向量提取的FF-APUF攻击方法

为评估物理不可克隆函数(PUF)的安全性,需针对不同的PUF结构设计相应的攻击方法。该文通过对强PUF电路结构和工作机理的研究,利用人工神经网络(ANN)提出一种针对触发器-仲裁器物理不可克隆函数(FF-APUF)的有效攻击方法。首先,根据FF-APUF电路结构,利用多维数组构建电路延时模型;然后,对FF-APUF的二进制激励进行邻位划分,将划分后的激励转换为十进制并表示为行向量,实现特征向量提取;最后,基于提取的特征向量利用ANN构建攻击模型并通过后向传播算法获得最优参数。实验结果表明,相同条件下攻击预测率均高于其他3种常用的机器学习方法,尤其当激励响应对(CRP)数量较少、激励位数较多时,优势更加明显。当激励位数为128、CRP个数为100和500时,平均攻击预测率分别提高36.0%和16.1%。此外,该方法具有良好的鲁棒性和可扩展性,不同噪声系数下攻击预测率与可靠性相差最大仅0.32%。     

Design of ultra low power current mode logic gates using magnetic cells

Non-volatile logic is a viable solution to overcome the leakage power issue which has become a major obstacle to CMOS technology scaling. Magnetic tunnel junction (MTJ)-based logic is a promising approach because of the non-volatility, less occupied area, almost zero static power consumption, programmability. This paper presents current mode logic gates using MTJ elements without any intermediate electronic circuitry. This efficient solution reduces the performance overheads of the spintronic logic circuits while simplifying fabrication. Hspice based simulations have been carried out to verify the performance of different logic gates. The simulation results reveal that the SBEG based gates provide less area, power consumption, and energy while also offering less design complexity as compared to mLogic (previously proposed magnetic logic) and CMOS gates.     

Analysis of High-Performance Fast Feedthrough Logic Families in CMOS

This brief presents a new CMOS logic family using the feedthrough evaluation concept and analyzes its sensitivity against technology parameters for practical applications. The feedthrough logic (FTL) allows for a partial evaluation in a computational block before its input signals are valid, and does a quick final evaluation as soon as the inputs arrive. The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low-power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (35.6%), and similar combined delay, power consumption and active area product (0.7% worst), while providing lower sensitivity to power supply, temperature, capacitive load and process variations than the standard CMOS technologies.     

基于敏感度混淆机制的控制型物理不可克隆函数研究

为了克服物理不可克隆函数(PUF)面对建模攻击的脆弱性,该文提出一种基于敏感度混淆机制的控制型PUF架构。根据PUF的布尔函数定义及Walsh谱理论,推导出各个激励位具有不同敏感度,分析并归纳了与混淆值位宽奇偶性有关的位置选取规则。利用该规则指导了多位宽混淆算法(MWCA)的设计,构建了具有高安全性的控制型PUF架构。将基础PUF结构作为控制型PUF的防护对象进行实验评估,发现基于敏感度混淆机制的控制型PUF所产生的响应具有较好的随机性。采用逻辑回归算法对不同PUF结构进行建模攻击,实验结果表明,相比基本ROPUF、仲裁器PUF以及基于随机混淆机制的OB-PUF,基于敏感度混淆机制的控制型PUF能够显著提高PUF的抗建模攻击能力。     

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

基于信号传输理论的Glitch物理不可克隆函数电路设计

通过对信号传输理论、竞争-冒险现象和物理不可克隆函数(Physical Unclonable Functions, PUF)电路的研究,论文提出一种基于信号传输理论的毛刺型物理不可克隆函数电路(Glitch Physical Unclonable Functions, Glitch-PUF)方案。该方案首先根据偏差延迟的信号传输理论,推导出获得稳定毛刺输出的电路级数;然后利用组合逻辑电路的传播延迟差异,结合1冒险和0冒险获得具有毛刺的输出波形,采用多级延迟采样电路实现Glitch-PUF的输出响应。由于毛刺信号具有显著的非线性特性,将其应用于PUF电路可有效解决模型攻击等问题。最后在TSMC 65 nm CMOS工艺下,设计128位数据输出的电路结构,Monte Carlo仿真结果表明Glitch-PUF电路具有良好的随机性。     

基于65 nm工艺的多端口可配置PUF电路设计

物理不可克隆函数(Physical Unclonable Function, PUF)电路利用结构完全相同的电路在制造过程中存在的随机工艺偏差,产生具有唯一性、随机性和不可克隆性的密钥。该文通过对共源共栅电流镜的研究,提出一种基于电流镜工艺偏差的多端口可配置PUF电路。该PUF电路由输入寄存器、偏差电压源、复用网络、判决器阵列和扰乱模块构成,通过激励信号配置偏差电压源,无需更换硬件便可实现输出密钥的变化,且可在一个时钟周期内输出多位密钥。在SMIC 65 nm CMOS工艺下,采用全定制方式设计具有36个输出端口的PUF电路,版图面积为24.8 m77.4 m。实验结果表明,该PUF电路具有良好的唯一性和随机性,且工作在不同温度(-40~125C)和电压(1.08~1.32 V)下的可靠性均大于97.4%,可应用于信息安全领域。     

Probabilistic clone-resend attack strategy in quantum key distribution

A kind of attack strategy based on a probabilistic cloning machine is proposed in this letter. The security of BB84 and the six-state quantum key distribution protocols under this attack is studied by theoretic analyses and corroborated by simulations. It is concluded that the quantum key distribution protocols still have an asymptotic perfect security even if the eavesdropper adopts the proposed attack strategy.     

Fast feedthrough logic: a high performance logic family for GaAs

A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.     

DDoS attack detection and defense based on hybrid deep learning model in SDN

Software defined network (SDN) is a new kind of network technology,and the security problems are the hot topics in SDN field,such as SDN control channel security,forged service deployment and external distributed denial of service (DDoS) attacks.Aiming at DDoS attack problem of security in SDN,a DDoS attack detection method called DCNN-DSAE based on deep learning hybrid model in SDN was proposed.In this method,when a deep learning model was constructed,the input feature included 21 different types of fields extracted from the data plane and 5 extra self-designed features of distinguishing flow types.The experimental results show that the method has high accuracy,it’s better than the traditional support vector machine (SVM) and deep neural network (DNN) and other machine learning methods.At the same time,the proposed method can also shorten the processing time of classification detection.The detection model is deployed in SDN controller,and the new security policy is sent to the OpenFlow switch to achieve the defense against specific DDoS attack.     

QSERL: quasi-static energy recovery logic

A new quasi-static energy recovery logic family (QSERL) using the principle of adiabatic switching is proposed in this paper. Most of the previously proposed adiabatic logic styles are dynamic and require complex clocking schemes. The proposed QSERL uses two complementary sinusoidal supply clocks and resembles the behavior of static CMOS. Thus, switching activity is significantly lower than dynamic logic. In addition, QSERL circuits can be directly derived from static CMOS circuits. A high-efficiency clock generation circuitry, which generates two complementary sinusoidal clocks compatible to QSERL, is also presented in this paper. The adiabatic clock circuitry locks the frequency of clock signals, which makes it possible to integrate adiabatic modules into a VLSI system. We have designed an 8×8 carry-save multiplier using QSERL logic and two phase sinusoidal clocks. SPICE simulation shows that the QSERL multiplier can save 34% of energy over static CMOS multiplier at 100 MHz