A formulation for analog behavioral-level sensitivity and steady-state analysis

The synthesis and verification of larger analog systems in the context of mixed signal ASICs requires formulation of simulation and analysis methods at the analog behavioral level. In this paper we present a formulation for sensitivity and steady state analysis of analog systems at the behavioral level. This formulation is useful for analysis and design space exploration of higher-level analog architectures synthesized from behavioral specifications. Conventional methods are formulated within the context of circuit level simulators such as SPICE, forcing the designer to model systems in terms of primitive circuit-level equivalent circuits thereby taking away advantages of higher level system modeling and simulation.     

Using Stochastic Differential Equation for Verification of Noise in Analog/RF Circuits

Today’s analog/RF design and verification face significant challenges due to circuit complexity, process variations and short market windows. In particular, the influence of technology parameters on circuits, and the issues related to noise modeling and verification still remain a priority for many applications. Noise could be due to unwanted interaction between the circuit elements or it could be inherited from the circuit elements. In addition, manufacturing disparity influence the characteristic behavior of the manufactured circuits. In this paper, we propose a methodology for modeling and verification of analog/RF designs in the presence of noise and process variations. Our approach is based on modeling the designs using stochastic differential equations (SDE) that will allow us to incorporate the statistical nature of noise. We also integrate the device variation due to 0.18μ m fabrication process in an SDE based simulation framework for monitoring properties of interest in order to quickly detect errors. Our approach is illustrated on nonlinear Tunnel-Diode and a Colpitts oscillator circuits.     

Causal reasoning mining approach to analog circuit verification

Functional errors in analog portion of mixed signal circuits become more severe and improvements in verification methods are increasingly important. Current verification methods fall into two categories, simulation-based verification and formal verification (Barke et al. [1]), focusing on verifying analog circuit function/performance. This paper proposes a novel approach verifying analog circuit design using causal reasoning. Causal reasoning is the inductive reasoning process to create a new design. The flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justifications (Jiao et al., 2015 [2]). Then, topological features corresponding to the starting ideas and design step sequence are verified individually by replacing the related devices with ideal behavior model. Performance is evaluated through Cadence Spectre simulation. Comparison with new circuit performance reveals incorrect functional issues and/or performance potentials for improvement. They are negative causes of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-μm CMOS technology to illustrate the verification approach.     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

Verification and revision of the power-down mode for hierarchical analog circuits

Specialized power-down circuitry can switch off an analog circuit when not required for system operation. When interconnecting sub-circuits with power-down functionality, new design errors, i.e. short-circuit paths, floating nodes and asymmetrical voltages at matched structures, may emerge in the power-down mode of the resulting hierarchical circuit. This paper presents a new method for the verification of the power-down mode of hierarchical analog circuits. In contrast to flat verification approaches, intermediate results are reused during computation. The obtained verification results can be used to revise and correct detected errors. Experimental results for a high input impedance differential amplifier are given.     

Frequency-domain bivariate generalized power series analysis ofnonlinear analog circuits

Bivariate generalized power series analysis is introduced for the analysis and behavioral modeling of nonlinear analog circuits and systems. It can be used to model analog subsystems and is compatible with circuit simulation, thereby allowing full circuits and behaviorally modeled analog subcircuits to be simulated together in an analog circuit/system simulator. The entire analysis is performed in the frequency domain, and arbitrary nonlinear circuits and any number of noncommensurable input frequencies can be accommodated. A diode ring demodulator is analyzed as an example     

一种分析模拟电路中互连线的新方法

互连线在高性能模拟集成电路中的影响已变得越来越不可忽视,部分元等效电路法（Partial Element Circuit,PEEC）是一种分析互连线的有效模型,常用方法是再用SPICE等数值模拟软件对PEEC模型进行分析。文中提出的用符号分析法模拟PEEC模型以及其它电路元器件,具有大大降低运算量等优点。基于这一点开发出一套交互式程序,使得包括考虑互连线影响的模拟电路的设计、验证和优化变得更容易、更有效率。     

Behavioral simulation for analog system design verification

Synthesis of analog circuits is an emergent field, with efforts focused at the cell level. With the growing trend of mixed ASIC designs that contain significant portions of analog sections, compatible design methodologies in the analog domain are necessary to complement those in the digital domain. The synthesis process requires an associated verification process to ensure that the designs meet performance specifications at the onset. In this paper we present a behavioral simulation methodology for analog system design verification and design space exploration. The verification task integrates with analog system-level synthesis for an integrated synthesis-verification process that avoids expensive post synthesis simulation by invoking external simulators. Thus rapid redesign at the architectural level can be undertaken for design parameter variation and during optimization. The verification suite is composed of a repertoire of analysis modes that include time and frequency domain analysis, sensitivity analysis and distortion analysis. Besides verification of design specifications, these analysis modes are also used to generate metrics for comparison of various architectural choices that could realize a given set of specifications. The implementation is in the form of a behavioral simulator, ARCHSIM     

Fault Modeling and Simulation Using VHDL-AMS

Fault simulation is an accepted part of the test generation procedure for digital circuits. With complex analog and mixed-signal integrated circuits, such techniques must now be extended. Analog simulation is slow and fault simulation can be prohibitively expensive because of the large number of potential faults. We describe how the number of faults to be simulated in an analog circuit can be reduced by fault collapsing, and how the simulation time can be reduced by behavioral modeling of fault-free and faulty circuit blocks. These behavioral models can be implemented in SPICE or in VHDL-AMS and we discuss the merits of each approach. VHDL-AMS does potentially offer advantages in tackling this problem, but there are a number of computational difficulties to be overcome.     

一种基于多频灵敏度分析的模拟电路K故障诊断方法

在模拟电路灵敏度分析的基础上，提出了多频灵敏度K故障诊断方法，详细说明了多频灵敏度K故障诊断方法的原理和步骤。针对模拟电路中最常见的双故障进行了电路仿真，仿真结果说明了该方法的有效性。     

基于Hammerstein模型的模拟电路结构级行为模型建模方法研究

 本文提出了一种适用于较大规模模拟电路行为级的建模方法.首先,将任何一个模拟电路等效为由电源(Source)、放大器(Amplifier,也可以看作为一个有增益的滤波器)、开关(Switch)、阻抗(Impedance)、等基本单元组成的网络.本文把这种网络称为模拟电路的SASI结构.其次,根据此种划分下的网络结构和Hammerstein模型结构的等价性,基于Hammerstein模型对模拟电路的宏模块进行建模.最后,采用硬件描述语言(Verilog-A,VHDL-AMS等)来描述这种SASI结构,从而完成整个模拟电路的行为级建模.采用该方法建立的模拟电路行为模型是一个参数化非线性动态模型,有利于模拟电路系统级整体设计.以采用"Top-Down"法设计红外遥控接收器、建立其行为模型为例,结果表明了该建模方法的有效性.     

Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

一种频率合成器的建模优化与电路设计

根据数模混合集成电路系统级和行为级快速验证的需求,设计了一种卫星导航系统射频接收机前端的频率合成器。传统行为级模型一般是基于理想环路进行参数提取,误差较大。为此,首先,分别利用MATLAB和Verilog-AMS对频率合成器建立理想行为级模型与非理想行为级模型,并根据行为级模型提取与优化的环路参数,采用SMIC 180 nm CMOS工艺设计仿真电路级频率合成器;其次,建立MATLAB噪声模型,对电路级各个模块的噪声进行拟合,评估频率合成器系统的整体噪声性能。所提出的频率合成器设计方法对电路级设计具有前瞻性的指导,并有助于电路级的设计优化。     

Hierarchical yield estimation of large analog integrated circuits

A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive     

Verification of the power-down mode of analog circuits by structural voltage propagation

In this paper, a new method for the verification of the power-down mode of analog circuits is presented. In power-down mode, internal nodes of the circuit can be floating. These nodes can cause short-circuit paths and reliability problems due to stress. However, automatic and reliable detection of floating nodes is not straightforward, because numerical simulation is often not trustworthy in the presence of floating nodes. The presented method estimates the node voltages in power-down mode by using a voltage propagation approach based on the circuit structure. No numerical simulation is needed. The circuit is transformed to a propagation graph which models the static behavior of the circuit. The propagation graph is scanned for short-circuit paths. Experimental results demonstrate the effectiveness and efficiency of the presented method as well as common pitfalls of numerical simulation.     

Nullor Equivalents of Active Devices for Symbolic Circuit Analysis

The new pathological elements, the voltage mirror (VM) and current mirror (CM), have shown advantages in analog behavioral modeling and circuit synthesis. Recently, the floating mirror elements have been used to derive pathological sections to ideally represent various popular analog signal processing properties that involve differential or multiple single-ended signals. In order to take advantage of the symbolic nodal analysis (NA) of nullor-mirror networks, we present the nullor equivalents of a differential voltage cell, a differential voltage conveying cell, and a current replication cell in this paper. The proposed nullor equivalents can be used to represent many popular active devices in performing symbolic NA. Two representative filter circuits containing differential characteristics of active devices are given to verify the feasibility. We expect them to be used within an analog design automation environment to enhance circuit analysis and modeling.     

Power consumption of analog circuits: a tutorial

A systematic approach to the power consumption of analog circuits is presented. The power consumption is related to basic circuit requirements, as dynamic range, bandwidth, noise figure and sampling speed and is considering basic device and device scaling behavior. Several kinds of circuits are treated, as samplers, amplifiers, filters and oscillators. The objective is to derive lower bounds to power consumption in analog circuits, to be used as design targets when designing power-constrained analog systems.     

Analog Computation Using Single-Electron Circuits

Analog computation is a processing method that solves a given problem by utilizing an analogy of a physical system to the problem. An idea is presented here for relating the behavior of single-electron circuits to analog computation. As an instance, a method is proposed for solving a combinatorial problem, the three-colorability problem, by using the properties of single-electron circuits. In problem solving, a single-electron circuit is constructed that is analogous to a given problem; then, through an annealing procedure, the circuit is made to settle down to its minimun energy state. The correct solution to the problem can be obtained by checking the final arrangement of electrons in the circuit. Analog computation is a promising architecture for single-electron computing systems.     

Keeping chaos at bay

The use of electronic circuits in studying chaotic dynamics and control are reviewed. Since all chaotic systems have several properties in common, simple circuits are analogous to much more complicated ones, such as lasers. Consequently, the methods developed to control chaos in electronic circuits are applicable to many diverse physical systems. The controlling device itself is a high-speed analog circuit. In applying perturbations, no calculations are made; instead, trial-and-error adjustments are used to locate the desired behavior. The initial observations of chaos in electronics, the development of the Ott-Grebogi-Yorke method for calculating the perturbations needed to stabilize a periodic orbit in a chaotic system and the occasional proportional feedback method, and their applications are discussed     

An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase.The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.