Partial evaluation based triple modular redundancy for single event upset mitigation

We present a design technique, Partial evaluation-based Triple Modular Redundancy (PTMR), for hardening combinational circuits against Single Event Upsets (SEU). The basic ideas of partial redundancy and temporal TMR are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. We have designed a fault insertion simulator to evaluate partial redundancy technique on the designs from MCNC′91 benchmark. Experimental results demonstrate that we can reduce the area overhead by up to 39.18% and on average 17.23% of the hardened circuit when compared with the traditional TMR. For circuits with a large number of gates and less number of outputs, there is a significant savings in area. Smaller circuits or circuits with a large number of outputs also show improvement in area savings for increased rounding range.     

A practical metric for soft error vulnerability analysis of combinational circuits

Besides the advantages brought by technology scaling, soft errors have emerged as an important reliability challenge for nanoscale combinational circuits. Hence, it is important for vulnerability analysis of digital circuits due to soft errors to take advantage of practical metrics to achieve cost-effective and reliable designs. In this paper, a new metric called Triple Constraint Satisfaction probability (TCS) is proposed to evaluate the soft error vulnerability of combinational circuits. TCS is based on a concept called Probabilistic Vulnerability Window (PVW) which is an inference of the necessary conditions for soft-error occurrence in the circuit. We propose a computation model to calculate the PVW’s for all circuit gate outputs. In order to show the efficiency of the proposed metric, TCS is used in the vulnerability ranking of the circuit gates as the basic step of the vulnerability reduction techniques. The experimental results show that TCS provides a distribution of soft error vulnerability similar to that obtained with fault injections performed with HSPICE or with an event driven simulator while it is more than three orders of magnitude faster. Also, the results show that using the proposed metric in the well-known filter insertion technique achieves up to 19.4%, 34.1%, and 55% in soft error vulnerability reduction of benchmark circuits with the cost of increasing the area overhead by 5%, 10%, and 20%, respectively.     

Time redundancy and gate sizing soft error-tolerant based adder design

In this paper, we propose an efficient and promising soft error tolerance approach for arithmetic circuits with high performance and low area overhead. The technique is applied for designing soft error tolerant adders and is based on the use of a fault tolerant C-element connecting a given adder output to one input of the C-element while connecting a delayed version of that output to the second input. It exploits the variability of the delay of the adder output bits, in which the most significant bits (MSBs) have longer delay than the least significant bits (LSBs), by adding larger delay to the LSBs and smaller delay to the MSBs to guarantee full fault tolerance against the largest pulse width of transient error (soft error) for the available technology with minimum impact on performance. To guarantee fault protections for transistors feeding outputs with smaller added delay, the technique utilizes transistor scaling to ensure that the injected fault pulse width is less than the added delay of the second output of the C-element. Simulation results reveal that the proposed technique takes precedence over other techniques in terms of failure rate, area overhead, and delay overhead. The evaluation experiments have been done based on simulations at the transistor level using HSPICE to take care of temporal masking combined with electrical masking. In comparison to TMR, the technique achieves 100% reliability with 31% reduction in area overhead without impacting performance in the case of a 32-bit adder, and 42% reduction in area overhead and 5% reduction in performance overhead in the case of a 64-bit adder. While our proposed technique achieves area reduction of 4.95% and 9.23% in comparison to CE-based DMR and Feedback-based DMR techniques in the case of a 32-bit adder, it achieves area reduction of 19.58% and 23.24% in the case of a 64-bit adder.     

Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates

Soft errors caused by particles strike in combinational parts of digital circuits are a major concern in the design of reliable circuits. Several techniques have been presented to protect combinational logic and reduce the overall circuit Soft Error Rate (SER). Such techniques, however, typically come at the cost of significant area and performance overheads. This paper presents a low area and zero-delay overhead method to protect digital circuits’ combinational parts against particles strike. This method is made up of a combination of two sub-methods: (1) a SER estimation method based on signal probability, called Estimation by Characterizing Input Patterns (ECIP) and (2) a protection method based on gate sizing, called Weighted and Timing Aware Gate Sizing (WTAGS). Unlike the previous techniques that either overlook internal nodes signal probability or exploit fault injection, ECIP computes the sensitivity of each gate by analytical calculations of both the probability of transient pulse generation and the probability of transient pulse propagation; these calculations are based on signal probability of the whole circuit nodes which make ECIP much more accurate as well as practical for large circuits. Using the results of ECIP, WTAGS characterizes the most sensitive gates to efficiently allocate the redundancy budget. The simulation results show the SER reduction of about 40% by applying the proposed method to ISCAS’89 benchmark circuits while imposing no delay overhead and 5% area overhead.     

基于时序优先的电路容错混合加固方案

为了有效降低容忍软错误设计的硬件和时序开销,该文提出一种时序优先的电路容错混合加固方案。该方案使用两阶段加固策略,综合运用触发器替换和复制门法。第1阶段,基于时序优先的原则,在电路时序松弛的路径上使用高可靠性时空冗余触发器来加固电路;第2阶段,在时序紧张的路径使用复制门法进行加固。和传统方案相比,该方案既有效屏蔽单粒子瞬态(SET)和单粒子翻转(SEU),又减少了面积开销。ISCAS89电路在45 nm工艺下的实验表明,平均面积开销为36.84%,电路平均软错误率降低99%以上。     

Designing robust threshold gates against soft errors

In applications where issues like power efficiency, high performance, and more noise tolerance are important, asynchronous design methodology can play a significant role. However, as a result of technology shrinkage, combinational asynchronous circuits have become vulnerable in presence of particle strikes. In this paper, we design robust quasi-delay insensitive (QDI) asynchronous circuits against soft errors. Null Convention Logic (NCL) gates used as one of the basic techniques in asynchronous circuits, are redesigned to increase their robustness against Single Event Upset (SEU). We analyze our design for various NCL structures and compare them with another design in Kuang et al. (2007) [4], and show that our proposed approach is more robust against SEU. The effect of some parameters such as power consumption, delay, and the influence of transistor sizing on soft error tolerance are discussed.     

Low-power scan design using first-level supply gating

Reduction in test power is important to improve battery lifetime in portable electronic devices employing periodic self-test, to increase reliability of testing, and to reduce test cost. In scan-based testing, a significant fraction of total test power is dissipated in the combinational block. In this paper, we present a novel circuit technique to virtually eliminate test power dissipation in combinational logic by masking signal transitions at the logic inputs during scan shifting. We implement the masking effect by inserting an extra supply gating transistor in the supply to ground path for the first-level gates at the outputs of the scan flip-flops. The supply gating transistor is turned off in the scan-in mode, essentially gating the supply. Adding an extra transistor in only one logic level renders significant advantages with respect to area, delay, and power overhead compared to existing methods, which use gating logic at the output of scan flip-flops. Moreover, the proposed gating technique allows a reduction in leakage power by input vector control during scan shifting. Simulation results on ISCAS89 benchmarks show an average improvement of 62% in area overhead, 101% in power overhead (in normal mode), and 94% in delay overhead, compared to the lowest cost existing method.     

Soft error modeling and remediation techniques in ASIC designs

Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain uncertainty bounds on estimated error propagation probability (EPP) values used in our SER modeling framework. Comparison of this method with the Monte-Carlo fault injection and simulation approach confirms the accuracy and speed-up of the presented technique for both the computed EPP values and uncertainty bounds.Based on our SER estimation framework, we also present efficient soft error hardening techniques based on selective gate resizing to maximize soft error suppression for the entire logic-level design while minimizing area and delay penalties. Experimental results confirm that these techniques are able to significantly reduce soft error rate with modest area and delay overhead.     

Statistical lifetime reliability optimization considering joint effect of process variation and aging

Aging effect degrades circuit performance in the runtime, interacts with fabrication-induced device parameter variation, and thus posing significant impact on circuit lifetime reliability. In this work, a statistical circuit optimization flow is proposed to ensure lifetime reliability of the manufactured chip in the presence of process variation and aging effects. It exploits a variation-aware gate-level statistical aging degradation model to characterize circuit lifetime reliability, identifies a set of worst duty cycles on the inputs of statistically critical gates to estimate the worst delay degradations on these gates. Based on the delay degradation information, statistical gate sizing is performed which enables the manufactured chip to satisfy lifetime reliability constraint in term of low area overhead.     

Modeling and testing for stuck faults in pseudo nMOS combinational circuits

In this paper, a new transistor model is developed. This model employs the logic transistor function (LTF) to examine the behavior of pseudo nMOS logic circuits. The LTF is a Boolean representation of the circuit output in terms of its input variables and its transistor topology. The LTF is automatically generated using the path algebra technique. The faulty behavior of the circuit can be obtained from the fault free LTF by using a systematic procedure. The model assumes the following logic values (0, 1, I, M). I and M imply an intermediate logical value and a memory element, respectively. Both classical stuck-at faults and non classical transistor stuck faults are analyzed in the model. An algorithm that is based on a modified version of the Boolean difference technique is applied to obtain test vectors. Primitive D-cubes of the fault are extracted for a specified sub circuit. To generate test for single or multiple faults, a variant of the D-algorithm may be used.     

Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology

As a consequence of technology scaling down, gate capacitances and stored charge in sensitive nodes are decreasing rapidly, which makes CMOS circuits more vulnerable to radiation induced soft errors. In this paper, a low cost and highly reliable radiation hardened latch is proposed using 65 nm CMOS commercial technology. The proposed latch can fully tolerate the single event upset (SEU) when particles strike on any one of its single node. Furthermore, it can efficiently mask the input single event transient (SET). A set of HSPICE post-layout simulations are done to evaluate the proposed latch circuit and previous latch circuits designed in the literatures, and the comparison results among the latches of type 4 show that the proposed latch reduces at least 39% power consumption and 67.6% power delay product. Moreover, the proposed latch has a second lowest area overhead and a comparable ability of the single event multiple upsets (SEMUs) tolerance among the latches of type 4. Finally, the impacts of process, supply voltage and temperature variations on our proposed latch and previous latches are investigated.     

Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits

Sleep transistor (ST) insertion is a valuable leakage reduction technique in circuit standby mode. Fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improve circuit noise margins. In this paper, we introduce a novel two-phase FGSTI technique which consists of ST placement and ST sizing. These two phases are formally modeled using mixed integer linear programming (MILP) models. When the circuit timing relaxation is not large enough to assign ST everywhere, leakage feedback (LF) gates, which are used to avoid floating states, induce large area and dynamic power overhead. An extended multi-object ST placement model is further proposed to reduce the leakage current and the LF gate number simultaneously. Finally, heuristic algorithms are developed to speed up the ST placement phase. Our experimental results on the ISCAS'85 benchmarks reveal that: 1) the two-phase FGSTI technique achieves better results than the simultaneous ST placement and sizing method; 2) when the circuit timing relaxation varies from 0% to 5%, the multi-object ST placement model can achieve on average 4 $times$-9 $times$ LF gate number reduction, while the leakage difference is only about 8% of original circuit leakage; 3) our heuristic algorithm is 1000 $times$ faster than the MILP method within an acceptable loss of accuracy.      

Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance

The conventional sleep transistor sizing schemes do not consider the resonant supply noise which represents the worst-case supply disturbance. This paper investigates the impact of sleep transistor sizing on different on-chip noise components and shows that, contrary to the conventional wisdom, a larger sleep transistor is not always favored in term of performance when the resonant supply noise is taken into account. To minimize the worst-case supply noise, an optimal sizing scheme using an explicit noise and impedance model is developed and verified by benchmark circuits. Employing the proposed technique results in a reduction of the worst-case noise by 19%, as well as a saving of standby leakage and area overhead by 60% in comparison with conventional sizing scheme. In order to deal with the sporadic nature of the resonant, we propose an adaptive sleep transistor circuit which adjusts the size of sleep transistor on the fly to remove the DC noise penalty of the fixed sizing scheme. Simulation results on 32-nm CMOS technology are used to demonstrate the functionality and effectiveness of the proposed adaptive sizing circuits.      

电路抗老化设计中基于门优先的关键门定位方法

随着CMOS工艺尺寸不断缩小,尤其在65 nm及以下的CMOS工艺中,负偏置温度不稳定性(NBTI)已经成为影响CMOS器件可靠性的关键因素。提出了一种基于门优先的关键门定位方法,它基于NBTI的静态时序分析框架,以电路中老化严重的路径集合内的逻辑门为优先,同时考虑了门与路径间的相关性,以共同定位关键门。在45 nm CMOS工艺下对ISCAS基准电路进行实验,结果表明:与同类方法比较,在相同实验环境的条件下,该方法不仅定位关键门的数量更少,而且对关键路径的时延改善率更高,有效地减少了设计开销。     

Fault Diagnosis of Analog Circuits Using Systematic Tests Based on Data Fusion

An analog fault diagnosis approach using a systematic step-by-step test is proposed for fault detection and location in analog circuits with component tolerance and limited accessible nodes. First, by considering soft faults and component tolerance, statistics-based fault detection criteria are established to determine whether a circuit is faulty by measuring accessible node voltages. For a faulty circuit, fuzzy fault verification is performed using the accessible node voltages. Furthermore, using an approximation technique, the most likely faulty elements are identified with a limited number of circuit gain measurements at selected frequencies. Finally, employing the D-S evidence theory, synthetic decision is made to locate faults according to the results of fault verification and estimation. Unlike other methods which use a single diagnosis method or a particular type of measurement information, the proposed approach makes use of the redundancy of different types of measurement information and the combined use of different diagnosis methods so as to improve diagnosis accuracy.     

Speed enhancement techniques for Clock-Delayed Dual Keeper Domino logic style

ABSTRACT

Domino circuit topology for high-speed operation, robustness and lower power consumption is quintessential in design of digital systems. In this paper, various high speed and robust mechanisms are proposed to enhance the speed of Clock-Delayed Dual Keeper Domino (CDDK) circuit. Delayed enabling of keeper circuit in CDDK domino circuit reduces contention between keeper circuit and Pull-Down network (PDN). The speed of transition at the dynamic node of the CDDK domino circuit is enhanced through imposing techniques namely (i) controlled clock delay time in enabling the keeper transistor, (ii) keeper control signal voltage swing variation, (iii) sizing of keeper transistors and (iv) deploying an additional conditional discharge path. The robustness of CDDK circuit is increased by upsizing the keeper transistor without degrading the speed by stack arrangement of dual keeper transistors. The simulation of enhancement techniques has been performed using Cadence® Virtuoso ADEL and ADEXL environments employing UMC 90nm technology library. The simulation results of wide fan-in 64-input OR gate demonstrate that CDDK technique with additional discharge path offer 38% increase in speed and CDDK technique with keeper transistor upsizing offers 52% increase in noise gain margin without speed degradation while comparing with the conventional domino logic circuit.     

Circuit-Level Design Approaches for Radiation-Hard Digital Electronics

In this paper, we present a novel circuit design approach for radiation hardened digital electronics. Our approach is based on the use of shadow gates, whose task it is to protect the primary gate in case it is struck by a heavy cosmic ion. We locally duplicate the gate to be protected, and connect a pair of diode-connected transistors (or diodes) between the outputs of the original and shadow gates. These transistors turn on when the voltages of the two gates deviate during a radiation strike. Our experiments show that at the level of a single gate, our circuit structure has a delay overhead about 1.76% on average, and an area overhead of 277%. At the circuit level, however, we do not need to protect all gates. We present a methodology to selectively protect specific gates of the circuit in a manner that guarantees radiation tolerance for the entire circuit. With this methodology, we demonstrate that at the circuit level, the average delay overhead is about 3% and the average placed-and-routed area overhead is 28%, compared to an unprotected circuit (for delay mapped designs). We also propose an improved circuit protection algorithm to reduce the area overhead associated with our approach. With this approach for circuit protection, the area and delay overheads are further lowered.      

Resynthesis of combinational logic circuits for improved path delayfault testability using comparison units

We propose a resynthesis method that modifies a given circuit to reduce the number of paths in the circuit and thus improve its path delay fault testability. The resynthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. A subcircuit can be replaced by a comparison unit if it implements a function belonging to the class of comparison functions defined here. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for resynthesis to improve the path delay fault testability of a circuit. Experimental results demonstrate considerable reductions in the number of paths and increased path delay fault testability. These are achieved without increasing the number of gates, or the number of gates along the longest path in the circuit. The random pattern testability for stuck-at faults remains unchanged     

OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

In this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen–Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.     

Generation Methodology for Good-Enough Approximate Modules of ATMR

Approximate triple modular redundancy (ATMR) is sought for logic masking of soft errors while effectuating lower area overhead than conventional TMR through the introduction of approximate modules. However, the use of approximate modules instigates reduced fault coverage in ATMR. In this work, we target better design tradeoffs in ATMR by proposing a heuristic method that effectively utilizes a threshold for unprotected input vectors to generate good enough combinations of approximate modules for ATMR, which accomplishes higher fault coverage and reduced area overhead compared with previously proposed approaches. The key concept is to employ logic optimization techniques of prime implicant (PI) expansion and reduction for successively obtaining approximate modules such that the combination of three approximate modules appropriately functions as an ATMR. For an ATMR to function appropriately, blocking is used to ensure that at each input vector, through the prime implicant (PI) expansion and reduction technique, only one approximate module differ from the original circuit. For large circuits, clustering is utilized and comparative analysis indicates that higher fault coverage is attained through the proposed ATMR scheme while preserving the characteristic feature of reduced area overhead. With a small percentage of unprotected input vectors, we achieved substantial decrease in transistor count and greater fault detection, i.e., an improvement of up to 26.1% and 42.1%, respectively.