NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits’ Life Time

Advances in CMOS technology have made possible the increase of integrated circuit’s density, which impacts directly on the circuit’s performance. However, technology scaling poses some reliability concerns that directly affect the circuit’s lifetime. One of the most important issues in nanoscale circuits is related to the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). This phenomenon increases the threshold voltage of pMOS transistors, which introduces delay along the integrated circuits’ paths, eventually causing functional failures. In this paper, a hardware-based technique able to increase the lifetime of Integrated Circuits (ICs) is proposed. In more detail, the technique is based on an on-chip sensor able to monitor IC’s aging and to adjust its power supply voltage in order to minimize NBTI effects and increase the circuit’s lifetime. Experimental results obtained throughout simulations demonstrate the technique’s efficiency, since the circuit’s lifetime has been increased by 150 %. Finally, the analysis of the main overheads introduced as well as the impact related to process variation renders the evaluation of the proposed approach possible.     

Impact of negative bias temperature instability on digital circuit reliability

We have examined the impact of NBTI degradation on digital circuits through the stressing of ring oscillator circuits. By subjecting the circuit to pMOS NBTI stress, we have unambiguously determined the circuit reliability impact of NBTI. We demonstrate that the relative frequency degradation of the NBTI stressed ring oscillator increases as the voltage at operation decreases. This behavior can be explained by reduced transistor gate overdrive and reduced voltage headroom at the circuit level. We present evidence that donor interface state generation during NBTI stress is a significant component of the transistor degradation. Further, we show that the static noise margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases.     

Impact of NBTI on the temporal performance degradation of digital circuits

Negative bias temperature instability (NBTI) has become one of the major causes for reliability degradation of nanoscale circuits. In this letter, we propose a simple analytical model to predict the delay degradation of a wide class of digital logic gate based on both worst case and activity dependent threshold voltage change under NBTI. We show that by knowing the threshold voltage degradation of a single transistor due to NBTI, one can predict the performance degradation of a circuit with a reasonable degree of accuracy. We find that digital circuits are much less sensitive (approximately 9.2% performance degradation in ten years for 70 nm technology) to NBTI degradation than previously anticipated.     

NBTI product level reliability for a low-power SRAM technology

We present a methodology to investigate product level NBTI reliability for the 90 nm technology node including the correlation between transistor, circuit, and product level NBTI reliability. NBTI reliability lifetime, dielectric breakdown, and gate leakage currents pose an important limitation to the maximum applicable supply voltage across the gate oxide. Product standby currents and regulator design are highly influenced by transistor reliability. We will present product reliability data ensuring sufficient product level reliability as well as their correlation attempts to transistor level reliability data.     

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Negative Bias Temperature Instability (NBTI) in pMOS transistors has become a major reliability concern in the state-of-the art digital circuit design. This paper discusses the effects of NBTI on 32 nm technology high fan-in dynamic OR gate, which is widely used in high-performance circuits. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG), are analyzed in the presence of NBTI degradation. We have shown the degradation in the output inverter pMOS transistor of the domino gate has a dominant impact on the delay in comparison with the keeper impact. Based on this analysis we have proposed that upsizing just the output inverter pMOS transistor can compensate for the NBTI degradation. Moreover, the impact of tuning the duty cycle of the clock has been investigated. It has been shown that although the keeper and the precharge transistors experience more NBTI degradation by increasing the low level in the clock signal, the total performance of the circuit will improve. We have also proposed an adaptive compensation technique based on Forward Body Biasing (FBB), to recover the performance of the aged circuit.     

A method of threshold voltage and current gain factor estimation for CMOS IC input transistors

A statistical technique for input transistor characteristic extraction and transistor threshold voltage and current gain factor estimation for a CMOS IC is presented. The technique is based on the sequential approach to segmented curve estimation. The method enables IC customers to make their own assessment of instability mechanisms in CMOS ICs without using special test device structures.     

Integrated modeling of Self-heating of confined geometry (FinFET,NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits

The evolution of transistor topology from planar to confined geometry transistors (i.e., FinFET, Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20 nm integrated circuits (ICs), but only at the expense of increased power density and thermal resistance. Thus, self-heating effect (SHE) has become a critical issue for performance/reliability of ICs. Indeed, temperature is one of the most important factors determining ICs reliability, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Electromigration (EM). Therefore, an accurate SHE model is essential for predictive, reliability-aware ICs design. Although SHE is collectively determined by the thermal resistances/capacitances associated with various layers of an IC, most researchers focus on isolated components within the hierarchy (i.e., a single transistor, few specific circuit configurations, or specialized package type). This fragmented approach makes it difficult to verify the implications of SHE on performance and reliability of ICs based on confined geometry transistors. In this paper, we combine theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20 nm transistors. Based on the refined Berkeley Short-channel IGFET Model Common Multi-Gate (BSIM-CMG) model, we examine SHE in typical digital circuits (e.g., ring oscillator) and analog circuits (e.g., two-stage operational amplifier) by Verilog-A based HSPICE simulation. Similarly, we develop a physics-based thermal compact model for packaged ICs using an effective media approximation for the Back End Of Line (BEOL) interconnects and ICs packaging. We integrate these components to investigate SHE behavior implication on ICs reliability and explain why one must adopt various (biomimetic) strategies to improve the lifetime of self-heated ICs.     

Negative bias temperature instability (NBTI) recovery with bake

Negative bias temperature instability (NBTI) is a major degradation mechanism of PMOSFET devices. When the p-channel field effect transistor (PFET) gate is biased negatively with respect to the channel, as in a CMOS inverter, at an elevated temperature the threshold voltage (V_t) decreases (absolute value increases for application temperatures) and the drive current (I_on) decreases. This degrades the device performance and may lead to circuit failure. NBTI has strong dependence on temperature, gate voltage, time, and gate oxide thickness. It also depends on device area and/or geometry. NBTI models used in industry are empirical. I have observed, on different (bulk and SOI) technologies, during the last several years that NBTI recovers with bake. The recovery amount and rate depend on the bake temperature. Full recovery is achieved at temperatures above 325 °C. After full recovery, the device behaves like new. Part of the NBTI recovery can be explained by piezo- and pyro-electric effect induced by the compressive nitride liner over the PFET.     

A new a-Si:H TFT pixel circuit compensating the threshold voltage shift of a-Si:H TFT and OLED for active matrix OLED

We propose a new hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel circuit for an active matrix organic light-emitting diode (AMOLED) employing a voltage programming. The proposed a-Si:H TFT pixel circuit, which consists of five switching TFTs, one driving TFT, and one capacitor, successfully minimizes a decrease of OLED current caused by threshold voltage degradation of a-Si:H TFT and OLED. Our experimental results, based on the bias-temperature stress, exhibit that the output current for OLED is decreased by 7% in the proposed pixel, while it is decreased by 28% in the conventional 2-TFT pixel.     

Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.     

一种用于AC/DC控制器中电压基准源的设计

提出了一种新颖的可用于AC/DC控制芯片中的基准电压源电路。此电路以PTAT（proportional to absolutetemperature）电流为偏置电流,利用二极管连接的MOS晶体管迁移率和阈值电压的温度系数可相互补偿的特性,产生与温度无关的栅源电压。该电路结构简单,既无启动电路也无运放,避免了运放失调对基准源的影响,设计采用CSMC0.5μm BCD工艺。仿真结果表明,该基准电压源具有较低的温度系数和高电源电压抑制比,可作为AC/DC控制芯片中迟滞比较器的参考源。     

A novel area efficient on-chip RO-Sensor for recycled IC detection

Out of different types of counterfeit integrated circuits (ICs) present in the supply chain, recycled ICs are major threat to security and reliability of electronic components. Recycled ICs possess shorter lifetime and it is extremely difficult to distinguish a recycled IC in a group of fresh IC with similar functionality. Out of several recycled IC detection methodology, Ring Oscillator (RO) sensor based detection approach is most efficient, because of its simple design and can detect ICs used only for few days. In this paper, we proposed two different types of modified RO sensor with lower area overhead. First RO sensor accelerates the aging to improve the detection of recycled ICs which are used for few days. The second architecture uses current controlled configurable RO (C-CRO) to further improve the detection of recycled IC. The RO in both the proposed sensor is designed by using modified pseudo NMOS logic based inverter. The proposed inverter accelerates the aging caused by negative bias temperature instability (NBTI) and lower the impact of process variation (PV) to improve the rate of detection. Both the proposed RO sensors are simulated in 90 nm CMOS technology. The simulation result shows both the proposed sensor improves the rate of detection as compared to the conventional sensor.     

From circuit miniaturization to the scalable IC

For more than three decades, the main driving force behind the integrated circuit (IC) revolution has been the steady scaling downwards of their lithographic design rules. It may therefore come as a surprise to those not familiar with their earlier history that the original IC did not, and actually could not, embrace the scaling concept. Instead, the early work was intended to achieve a revolution in circuit miniaturization by bringing all circuit components down to the same tiny size as the transistor. For these circuits to become truly scalable ICs, new transistor structures had to be invented and adapted to IC needs. Until this happened the cost-effectiveness of the IC was highly controversial. Five years after the IC was invented, plans were being put in place by IBM and AT&T to utilize flipchip transistor technology rather than ICs. But these, like the original ICs, were also unscalable, and consequently lost out to a new generation of ICs that were scalable. Two revolutions were driven by the subsequent evolution of design rules; first TTL/minicomputers, and then MOS/microcomputers. K. Marx proved disastrously wrong in the political arena, but his aphorism “evolution carried far enough becomes revolution” fits IC history like a glove     

一种降低电路泄漏功耗的多阈值电压方法

目前,多阈值电压方法是缓解电路泄漏功耗的有效手段之一。但是,该方法会加重负偏置温度不稳定性(NBTI)效应,导致老化效应加剧,引起时序违规。通过找到电路的潜在关键路径集合,运用协同优化算法,将关键路径集合上的门替换为低阈值电压类型,实现了一种考虑功耗约束的多阈值电压方法。基于45 nm工艺模型及ISCAS85基准电路的仿真结果表明,在一定功耗约束下,该方法的时延改善率最高可达12.97%,明显优于常规多阈值电压方法。电路的规模越大,抗泄漏功耗的效果越好。     

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The effectiveness of our method is comprehensively demonstrated with the International Symposium on Circuits and Systems (ISCAS) benchmarks and a 65-nm industrial design. Furthermore, we extract the following key design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; 2) There is an optimum supply voltage that leads to the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is highly sensitive to input vectors. The difference in delay degradation is up to 5$times $ for various static and dynamic operations. Finally, we examine the interaction between NBTI effect, and process and design uncertainty in realistic conditions.      

Local clustering 3-D stacked CMOS technology for interconnect loading reduction

A three-dimensional (3-D) stacked CMOS technology is developed to closely pack devices in a number of standard cells to form local clusters. Based on the 3-D stacked CMOS technology, an analysis to extend the technology to implement standard cell-based integrated circuits is performed. It is found that the 3-D stacked CMOS technology can reduce the size of an overall IC by 50% with significant reduction in interconnect delay. A thermal analysis is also performed. It was found that the rise in temperature in 3-D ICs could be lower than that of traditional planar ICs under the condition of same propagation delay since the required power supply voltage of 3-D ICs to achieve the same performance is lower.     

Chips go vertical [3D IC interconnection]

This article describes 3D ICs. By stacking chips and directly connecting them with vertical wires, chip makers help interconnects keep up with increasing transistor speeds. A 3D IC is a stack of multiple dies with many direct connections tunneling through them, dramatically reducing global interconnect lengths and increasing the number of transistors that are within one clock cycle of each other. The key to the advantage comes from allowing wires to be routed directly between and through the chips. With this approach, the maximum global-interconnect length and the average global-interconnect length both decrease by a factor equal to the square root of the number of dies being stacked. This decreases the bottleneck effect they have on the IC's performance by about the same factor.     

Intrinsic leakage in deep submicron CMOS ICs-measurement-based testsolutions

The high leakage current in deep submicron, short-channel transistors can increase the stand-by power dissipation of future IC products and threaten well established quiescent current (I_DDQ)-based testing techniques. This paper reviews transistor intrinsic leakage mechanisms. Then, these well-known device properties are applied to a test application that combines I_DDQ and ICs maximum operating frequency (F_max) to establish a novel two-parameter test technique for distinguishing intrinsic and extrinsic (defect) leakages in ICs with high background leakage. Results show that I_DDQ along with F_max can be effectively used to screen defects in high performance, low V_T (transistor threshold voltage) CMOS ICs     

Impact of NBTI and HCI on PMOSFET threshold voltage drift

Negative bias temperature instability (NBTI) induced PMOSFET parameter degradation is a serious reliability concern in advanced analog and mixed signal technologies. In this paper, V_t-mismatch shift due to NBTI in a cascode current mirror is examined. The impact of NBTI and hot-carrier injection (HCI) on threshold voltage degradation and subsequent damage recovery during annealing is also studied. Finally the influence of channel length, gate voltage, drain voltage and damage recovery on conventional NBTI and HCI DC lifetime extrapolation is characterized with the impact on analog applications highlighted.