Optimized 2.4 GHz voltage controlled oscillator with a high-Q MWCNT network-based pulse-shaped inductor

This paper focuses on the use of a high-Q Multi-Wall Carbon Nano-Tube (MWCNT)-based pulse-shaped inductor in the implementation of an LC differential voltage-controlled oscillator (LCVCO). The topology integrates a micro-scaled capacitor and a MWCNT network-based inductor together with the CMOS circuits. The CMOS circuits were designed to enhance the quality factor and to control the oscillation amplitude. The high quality factor of the inductor improves the overall quality factor and phase noise of the oscillator. The measurement results show that the LCVCO operates at 2.3982 GHz and achieves a phase noise of ?133.3 dBc/Hz at 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.07 GHz to 2.77 GHz (29.16%) with an ultra low power consumption of 1.7 mW from a 0.6 V supply voltage. The output power level of the VCO is ?10 dBm, with an improved quality factor of 49.     

A tunable CMOS Wilkinson power divider using active inductors

This paper presents the design and implementation of a tunable CMOS Wilkinson power divider using active inductors. Compared to a conventional active inductor topology, the proposed active inductor features higher inductance tuning range, higher self-resonant frequency, and lower power consumption by introducing two additional transistors. Benefitting from the superior inductor, the low-loss Wilkinson power divider is practical while maintaining a wide tuning range. The design consuming 10.2 mW demonstrates an insertion loss of 0.67 dB, a return loss of 27 dB, and an isolation of 22.6 dB at 8 GHz. Moreover, the tuning range of the circuit is between 5.8 GHz and 10.4 GHz, rendering a 4.6 GHz bandwidth. The active chip size of the lumped design is merely 0.25 mm × 0.15 mm.     

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

MISO current mode bi-quadratic filter employing high performance inverting second generation current conveyor circuit

This paper presents static and dynamic studies of a new CMOS realization for the inverting second generation current conveyor circuit (ICCII). The proposed design offers enhanced functionalities compared to ICCII circuits previously presented in the literature. It is characterized by a rail to rail dynamic range with high accuracy, a low parasitic resistor at terminal X (1.6 Ω) and low power consumption (0.31 mW) with wide current mode (3.32 GHz) and voltage mode (3.9 GHz) bandwidths.Furthermore, a new MISO current mode bi-quadratic filter based on using ICCII circuits as active elements is proposed. This filter can realize all standard filter responses without changing the circuit topology. It is characterized by active and passive sensitivities less than unity and an adjustment independently between pole frequency and quality factor. The operating frequency limit of this filter is about 0.8 GHz with 0.674 mW power consumption.The proposed current conveyor circuits and bi-quadratic filter are tested by TSPICE using CMOS 0.18 µm TSMC technology with ±0.8 V supply voltage to verify the theoretical results.     

Floating active inductor based Class-C VCO with 8 digitally tuned sub-bands

A fully integrated floating active inductor based voltage-controlled oscillator (VCO) is presented. The active inductor employs voltage differencing transconductance amplifier (VDTA) as a building block. The designed VCO achieves frequency tuning by varying the bias current through the VDTA and utilizes a Class-C topology for improving the phase noise performance. The inductor-less VCO is designed and implemented in a 45-nm CMOS process and its performance is estimated using Virtuoso ADE of Cadence. Operating at a supply voltage of ±1 V, the proposed VCO consumes 0.44–1.1 mW corresponding to the oscillation frequency of 1.1–1.8 GHz thereby exhibiting a tuning range of 48.27%. The phase noise of the VCO lies in the range of −94.12 to −98.37 dBc/Hz at 1 MHz offset resulting in a FOM of −172.14 to −176.69 dBc/Hz.     

A novel low power UWB cascode SiGe BiCMOS LNA with current reuse and zero-pole cancellation

A low power cascode SiGe BiCMOS low noise amplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is composed of cascode input stage and common emitter (CE) output stage with dual loop feedbacks. The novel cascode-CE current reuse topology replaces the traditional two stages topology so as to obtain low power consumption. The emitter degenerative inductor in input stage is adopted to achieve good input impedance matching and noise performance. The two poles are introduced by the emitter inductor, which will degrade the gain performance, are cancelled by the dual loop feedbacks of the resistance-inductor (RL) shunt–shunt feedback and resistance-capacitor (RC) series–series feedback in the output stage. Meanwhile, output impedance matching is also achieved. Based on TSMC 0.35 μm SiGe BiCMOS process, the topology and chip layout of the proposed LNA are designed and post-simulated. The LNA achieves the noise figure of 2.3–4.1 dB, gain of 18.9–20.2 dB, gain flatness of ±0.65 dB, input third order intercept point (IIP₃) of ?7 dBm at 6 GHz, exhibits less than 16 ps of group delay variation, good input and output impedances matching, and unconditionally stable over the whole band. The power consumption is only 18 mW.     

A resistive-feedback LNA in 65 nm CMOS with a gate inductor for bandwidth extension

In order to get a wideband and flat gain, a resistive-feedback LNA using a gate inductor to extend bandwidth is proposed in this paper. This LNA is based on an improved resistive-feedback topology with a source follower feedback to match input. A relative small inductor is connected in series to transistor׳s gate, which boosts transistor׳s effective transconductance, compensates gain loss and then leads the proposed LNA with a flat gain and wider bandwidth. Moreover, the LNA׳s noise is partially inhibited by the gate inductor, especially at high frequency. Realized in standard 65-nm CMOS process, this LNA dissipates 12 mW from a 1.5-V supply while its core area is 0.076 mm². Across 0.4–10.6 GHz band, the proposed LNA provides 9.5±0.9 dB power gain (S₂₁), better than −11-dB input matching, 3.5-dB minimum noise figure, and higher than −17.2-dBm P_1 dB.     

Low power dissipation SiGe HBT dual-band variable gain amplifier

A dual-band variable gain amplifier operating at 0.9 GHz and 2.4 GHz was designed based on high performance RF SiGe HBT for large amount of signals transmission and analysis. Current steering was adopted in gain-control circuit to get variable trans-conductance and then variable gain. Emitter degeneration and current reuse were considered in amplifying stage for low noise figure and low power dissipation respectively. A single-path circuit resonating at two frequency points simultaneously was designed for input impedance matching. PCB layout parasitic effects, especially the via parasitic inductor, were analyzed theoretically and experimentally and accounted for using electro-magnetic (EM) simulation. The measurement results show that a dynamic gain control of 26 dB/16 dB in a control voltage range of 0.0–1.4 V has been achieved at 0.9/2.4 GHz respectively. Both S₁₁ and S₂₂ are below than –10 dB in all the control voltage range. Noise figures at both 0.9 GHz and 2.4 GHz are lower than 5 dB. Total power dissipation of the dual-band VGA is about 16.5 mW at 3 V supply.     

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9 V shows a high DC gain of 63 dB with a unity gain frequency at 3.5 MHz, a wide dynamic range and a total harmonic distortion of −60 dB at 1 MHz for an input of 1 Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56 MHz and voltage mode of 16.78 MHz cut-off frequency f-3 dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24 mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18 μm TS18SL.     

A high-gain low-power 2–14 GHz ultra-wide-band CMOS LNA for wireless receivers

In this paper, a 2–14 GHz CMOS LNA for ultra-wide-band (UWB) wireless systems is presented. To achieve a good and flat high power gain along with a low noise figure and a high input return loss, the proposed LNA adopts a capacitive cross-coupling common-gate (CG) topology with extra cascaded transistors and inductance. Over the entire 2–14 GHz bandwidth, it exhibits a return loss less than ?10 dB and a small-signal gain of 9 dB. With an input intercept point of ?3 dBm at 5 GHz, it consumes only 9 mW from a 1.5 V supply voltage.     

Critical design issues for high-power GaN/AlGaN anti-serial Schottky varactor frequency triplers

In this paper the importance of a new design variable for high power anti-serial Schottky varactors, the aluminum composition of the AlGaN barrier layer, is demonstrated. AlGaN/GaN varactors containing either (1) a high-doped/low-doped GaN region or (2) just a low doped GaN region have been compared demonstrating that the selection of the device structure also depends on the amplitude of the input signal being tripled in frequency. Stronger susceptance modulation is exhibited in AlGaN/GaN ASVs made from Ga-face polar material compared to N-face polar material. Results indicate choosing the proper aluminum composition results in 27% conversion efficiency with an input signal of 5 GHz and over 7% conversion efficiency with an input signal of 60 GHz along with optimization trends. With input voltage amplitudes over 10 V an AlGaN/GaN structure with 15% Al provides greater conversion efficiency than one with 5% Al. Power absorbed in the varactor also increases as aluminum percent increases affecting reliability and power transfer. Results of a GaN ASV performing as a frequency tripler for fundamental frequencies up to 110 GHz indicate an advantage to using an AlGaN/GaN epi-structure over only a GaN epi-structure.     

High linearity,low power RF mixer design in 65 nm CMOS technology

A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB.     

A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm².     

Efficient biasing circuit strategies for inductorless wideband low noise amplifiers with feedback

This paper presents a comparative study among different biasing circuits of inductorless low-area Low Noise Amplifier (LNAs) with feedback. This study intends to determine the most suitable biasing circuit to achieve the best LNA performance for wideband applications. The main performance metrics are analyzed and a comparison is carried out based on electrical simulations. To this purpose, two different CMOS technology processes are considered: 130 nm and 90 nm. In both cases, the supply voltage is 1.2 V. The best LNA designed in 130 nm achieves a bandwidth of 2.94 GHz with a flat voltage gain (A_v) of 16.5 dB and a power consumption of 3.2 mW. The same LNA topology designed in 90 nm technology has a bandwidth of 11.2 GHz, featuring a voltage gain of 16.6 dB and consuming 1.9 mW. Both LNAs are input-impedance matched and have a noise figure below 2.4 dB measured at 2.4 GHz. As a case study, the layout of the best-performance LNA circuit has been implemented in a 130 nm technology, achieving an area of 0.012 mm², which is near the size of a pad or an inductor. It is demonstrated that the bandwidth of this circuit can be notably increased by simply adding a small inductance in the feedback path.¹     

A 1.58 nW power consumption and 34.45 ppm/°C temperature coefficient bandgap reference (BGR) for subblocks of RFID tag

In this paper a bandgap reference (BGR) circuit irrespective of the temperature and the supply voltage variation with very low power consumption is proposed. The proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) generators of the proposed BGR, which has four cores cascaded with each other, are used in order to increase not only the output voltage, but also the output control ability for the temperature and the voltage insensitivity. To combine produced voltage from PTAT and CTAT generator, a weight combination circuit, which uses internal capacitors of transistors, is applied. Due to the fact that all of the transistors in such a topology are worked in sub-threshold region, the power consumption is significantly diminished to 1.58 nW. Also the variation of the temperature from −25 °C to 150 °C, leads to the temperature coefficient about 34.45 ppm/°C. The design simulation is done at 960 MHz frequency in TSMC 0.18 µm CMOS technology with the help of Cadence software. Also the post layout simulation result and the layout of the proposed circuit are presented. The output and the chip area of this BGR are 141.5 mV and 1387 µm² respectively.     

A real-time self-calibrated current mirror for wide range current reference generation,signal reproduction and delaying

Current Mirrors are widely used in current mode circuits like A/D Converters, current conveyors, filters etc. The most important features of a current mirror are its precision, its input and output, resistance and minimum voltage and its frequency response. Although several mirrors with extremely small current transfer error have been presented, this error is usually measured in the typical case. This error may significantly differ in real-time conditions depending on mismatches, process and temperature variations. Stimulated by the current reference generation required in an A/D Converter with novel binary tree architecture that has been recently presented, an appropriate current mirror architecture supported by real time calibration logic is described in this paper. This mirror can generate a high enough output current (up to 1 mA), with relatively low transfer error (<4%), in a descent frequency range of up to 1 GHz. It requires a 1–1.2 V voltage supply and dissipates a power that can be as low as 0.3 mW. The error is measured using mismatch and process variation Monte Carlo post-layout simulations in TSMC 90 nm process.     

A 24 W Ku band GaN based power amplifier with 9.1 dB linear gain

A Ku-band power amplifier is successfully developed with a single chip 4.8 mm AlGaN/GaN high electron mobility transistors (HEMTs). The AlGaN/GaN HEMTs device, achieved by E-beam lithography г-gate process, exhibited a gate-drain reverse breakdown voltage of larger than 100 V, a cutoff frequency of f_T=30 GHz and a maximum available gain of 13 dB at 14 GHz. The pulsed condition (100 μs pulse period and 10% duty cycle) was used to test the power characteristic of the power amplifier. At the frequency of 13.9 GHz, the developed GaN HEMTs power amplifier delivers a 43.8 dBm (24 W) saturated output power with 9.1 dB linear gain and 34.6% maximum power-added efficiency (PAE) with a drain voltage of 30 V. To our best knowledge, it is the state-of-the-art result ever reported for internal-matched 4.8 mm single chip GaN HEMTs power amplifier at Ku-band.     

Miniaturized active stepped impedance planar inverted-F antenna using common ground

This paper presents a compact active integrated antenna (AIA) comprising of class-A power amplifier (PA) and stepped impedance planar inverted-F antenna (PIFA). In the proposed design, a common ground is used for both PA and PIFA, resulting a compact antenna of size 0.14λ₀ × 0.11λ₀ × 0.01λ₀ (λ₀ is free space wavelength at 0.85 GHz). Moreover, it is demonstrated that by using the stepped impedance radiator the operating frequency of the active PIFA is shifted down from its natural resonant frequency of 1.36 GHz to 0.85 GHz, offering an extensive size reduction of 80%. This active integration increases the passive antenna gain through the effective loading of the antenna to the power amplifier. The measured result indicates that the active and passive antennas achieved the gain of 15.7 dB and 3.81 dBi, respectively after the integration. In addition, the maximum SAR value of antenna is found to be 0.64 W/kg.     

Nano-gap micro-electro-mechanical bulk lateral resonators with high quality factors and low motional resistances on thin silicon-on-insulator

The design, fabrication and experimental investigation of 22–25 MHz fragmented-membrane MEM bulk lateral resonators (BLR) with 100 nm air-gaps on thin (1 and 6 μm) silicon-on-insulator (SOI) are reported. Quality factors as high as 120,000 and motional resistances of as little as 60 kΩ are measured under vacuum at room temperature, with 12 V DC bias and low AC power. The temperature influence on the resonance frequency and quality factor is studied and discussed between 80 K and 320 K. Significant quality factor increase and motional resistance reduction are reported at cryogenic temperature. The paper shows that high-quality factor MEM resonators can be integrated on partially depleted thin SOI, which can be a substrate of choice for the fabrication of future integrated hybrid MEMS–CMOS integrated circuits for communication applications.     

A tuned rectifier for RF energy harvesting from ambient radiations

A circuit topology based on accumulate-and-use philosophy has been developed to harvest RF energy from ambient radiations such as those from cellular towers. Main functional units of this system are antenna, tuned rectifier, supercapacitor, a gated boost converter and the necessary power management circuits. Various RF aspects of the design philosophy for maximizing the conversion efficiency at an input power level of 15 μW are presented here. The system is characterized in an anechoic chamber and it has been established that this topology can harvest RF power densities as low as 180 μW/m² and can adaptively operate the load depending on the incident radiation levels. The output of this system can be easily configured at a desired voltage in the range 2.2–4.5 V. A practical CMOS load – a low power wireless radio module has been demonstrated to operate intermittently by this approach. This topology can be easily modified for driving other practical loads, from harvested RF energy at different frequencies and power levels.