Efficient architecture of variable size HEVC 2D-DCT for FPGA platforms

This study presents a design of two-dimensional (2D) discrete cosine transform (DCT) hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field programmable gate array (FPGA) platforms. The proposed methodology efficiently proceeds 2D-DCT computation to fit internal components and characteristics of FPGA resources. A four-stage circuit architecture is developed to implement the proposed methodology. This architecture supports variable size of DCT computation, including 4 × 4, 8 × 8, 16 × 16, and 32 × 32. The proposed architecture has been implemented in System Verilog and synthesized in various FPGA platforms. Compared with existing related works in literature, this proposed architecture demonstrates significant advantages in hardware cost and performance improvement. The proposed architecture is able to sustain 4 K@30 fps ultra high definition (UHD) TV real-time encoding applications with a reduction of 31–64% in hardware cost.     

In situ modification of low-cost Cu electrodes for high-performance low-voltage pentacene thin film transistors (TFTs)

We demonstrate low-voltage pentacene thin film transistors (TFTs) using in situ modified low-cost Cu (M-Cu) as source–drain (S/D) electrodes and solution-processed high capacitance (200 nF/cm²) gate dielectrics. Under a gate voltage of ?3 V, the device with M-Cu electrodes shows a much higher apparent mobility (1.0 cm²/V s), a positively shifted threshold voltage (?0.62 V), a lower contact resistance (0.11 MΩ) and a larger transconductance (12 μS) as compared to the device with conventional Au electrodes (corresponding parameters are 0.71 cm²/V s, ?1.44 V, 0.41 MΩ, and 5.7 μS, respectively). The enhancement in the device performance is attributed to the optimized interface properties between S/D electrodes and pentacene. Moreover, after encapsulation the M-Cu electrodes with a thin layer of Au in the aim of suppressing unfavorable surface oxidation, the electronic characteristics of the device are further improved, and highly enhanced apparent mobility (2.3 cm²/V s) and transconductance (19 μS) can be achieved arising from the increased conductivity of the electrode itself. Our study provides a simple and feasible approach to achieve high performance low-voltage OTFTs with low-cost S/D electrodes, which is desirable for large area applications.     

DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs

Registers are one of the circuit elements that can be affected by soft errors. To ensure that soft errors do not affect the system functionality, Triple Modular Redundancy (TMR) is commonly used to protect registers. TMR can effectively protect against errors affecting a single flip-flop and has a low overhead in terms of circuit delay. The main drawback of TMR is that it requires more than three times the original circuit area as the flip-flops are triplicated and additional voting logic is inserted. Another alternative is to protect registers using Error Correction Codes (ECCs), but those typically require a large circuit delay overhead and are not suitable for high speed implementations. In this paper, DMR + an alternative to TMR to protect registers in FPGAs, is presented. The proposed scheme exploits the FPGA structure to achieve a reduction in the FPGA resources (LUTs and Flip-Flops) at the cost of a certain overhead in delay. DMR + can correct all single bit errors like TMR but is more vulnerable to multiple bit errors. To evaluate the benefits, the DMR + technique has been implemented and compared with TMR considering standalone registers and also some simple designs.     

High-speed testing of Josephson logic circuits by an on-chip signal-pattern generator

We have developed an on-chip signal-pattern generator (SPG) for high-speed testing of latching-type Josephson logic circuits. The basis of the SPG is using a feedback shift register, in which the complement output of the last-stage LATCH gate (a D flip-flop) is fed back to the first-stage LATCH gate. Since the SPG consists of only LATCH gates and requires no external input signal, the design and high-speed operation are greatly simplified. We performed a high-speed measurement of the 1-bit SPG and found that the SPG has the potential to operate at a speed of more than 4.6 GHz. We also demonstrated a high-speed testing of a 2-bit logic circuit with the 2-bit SPG up to a clock frequency of 1 GHz.     

Memristor-based combinational circuits: A design methodology for encoders/decoders

The crossbar architecture is viewed as the most likely path towards novel nanotechnologies which are expected to continue the technological revolution. Memristor-based crossbars for integrating memory units have received considerable attention, though little work has been done concerning the implementation of logic. In this work we focus on memristor-based complex combinational circuits. Particularly, we present a design methodology for encoder and decoder circuits. Digital encoders are found in a variety of electronics multi-input combinational circuits (e.g. keyboards) nowadays, converting the logic level ‘1’ data at their inputs into an equivalent binary code at the output. Their counterparts, digital decoders, constitute critical components for nanoelectronics, mainly in peripheral/interface circuitry of nanoelectronic circuits and memory structures. The proposed methodology follows a CMOS-like design scheme which can be used for the efficient design and mapping of any 2ⁿ×n (n×2ⁿ) encoder (decoder) onto the memristor-based crossbar geometry. For their implementation, a hybrid nano/CMOS crossbar type with memristive cross-point structures and available transistors is elaborated, which is a promising solution to the interference between neighboring cross-point devices during access operation. Circuit functionality of the presented encoder/decoder circuits is exhibited with simulations conducted using a simulator environment which incorporates a versatile memristor device model. The proposed design and implementation paradigm constitutes a step towards novel computational architectures exploiting memristor-based logic circuits, and facilitating the design and integration of memristor-based encoder/decoder circuits with nanoelectronics applications of the near future.     

A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter

Exploiting specific properties of the algorithm, a high-throughput pipelined architecture is introduced to implement the H.264/AVC deblocking filter. The architecture was synthesized in 0.18 μm technology and the clock frequency and area are 400 MHz and 16.8 Kgates, respectively. Also, it is able to filter 217 and 55 Frames per second (Fps) for Full- and Ultra-HD videos, respectively. The introduced architecture outperforms similar ones in terms of frequency (1.8× up to 4×), throughput, (1.5× up to 3.8×), and Fps. Moreover, extensions to support different sample bit-depths and chroma formats are included. Also, experimental results for different FPGA families are offered.     

Polymer composite of poly(vinyl phenol)-reduced graphene oxide reduced by vitamin C in low energy consuming write-once–read-many times memory devices

We report the application of reduced graphene oxide, using vitamin C as reducing agent, to make a composite with poly(vinyl phenol) as the active layer of write-once–read-many times memory devices. These devices present a high ON/OFF current ratio of 10⁵ when read at 1 V, retain the information for a long time maintaining the ON/OFF current ratio constant, and require low energy for performing at 5 V the memory write (less than 10^?8 J cm^?2 device active area) and read operations.     

High-efficiency low color temperature organic light emitting diodes with solution-processed emissive layer

Low color temperature (CT) lighting provides a warm and comfortable atmosphere and shows mild effect on melatonin suppression. A high-efficiency low CT organic light emitting diode can be easily fabricated by spin coating a single white emission layer. The resultant white device shows an external quantum efficiency (EQE) of 22.8% (34.9 lm/W) with CT 2860 K at 100 cd/m², while is shown 18.8% (24.5 lm/W) at 1000 cd/m². The high efficiency may be attributed to the use of electroluminescence efficient materials and the ambipolar-transport host. Besides, proper device architecture design enables excitons to form on the host and allows effective energy transfer from host to guest or from high triplet guest to low counterparts. By decreasing the doping concentration of blue dye in the white emission layer, the device exhibited an orange emission with a CT of 2280 K. An EQE improvement was observed for the device, whose EQE was 27.4% (38.8 lm/W) at 100 cd/m² and 20.4% (24.6 lm/W) at 1000 cd/m².     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450×380 μm².     

High-speed organic single-crystal transistors gated with short-channel air gaps: Efficient hole and electron injection in organic semiconductor crystals

Short-channel, high-mobility organic filed-effect transistors (OFETs) are developed based on single crystals gated with short-channel air gaps. The high hole mobility of 10 cm²/Vs for rubrene, and high electron mobility of 4 cm²/Vs for PDIF-CN₂ crystals are demonstrated even with a short channel length of 6 μm. Such performance is due to low contact resistance in these devices estimated to be as low as ～0.5 kΩ cm at gate voltage of ?4 V for rubrene. With the benefit of the short channel length of 4.5 μm in a new device architecture with less parasitic capacitance, the cutoff frequency of the rubrene air–gap device was estimated to be as high as 25 MHz for drain voltage of ?15 V, which is the fastest reported for p-type OFETs, operating in ambient conditions.     

New Non-Volatile Memory Structures for FPGA Architectures

A new set of programmable elements (PEs) using a new non-volatile device for use with routing switches and logical elements within a field-programmable gate array (FPGA) is described. The PEs have small area, can be combined with components that use low operational voltage on the same CMOS logic process, are non-volatile, enable the use of fast thin-oxide pass transistors, and are reprogrammable. A novel non-volatile flip-flop for use within the logical elements is presented as well. In combination, these methods enable programmable logic devices with improved area efficiency, the speed advantages of SRAM-based FPGAs, and a wide range of opportunities for power down strategies.     

A real-time self-calibrated current mirror for wide range current reference generation,signal reproduction and delaying

Current Mirrors are widely used in current mode circuits like A/D Converters, current conveyors, filters etc. The most important features of a current mirror are its precision, its input and output, resistance and minimum voltage and its frequency response. Although several mirrors with extremely small current transfer error have been presented, this error is usually measured in the typical case. This error may significantly differ in real-time conditions depending on mismatches, process and temperature variations. Stimulated by the current reference generation required in an A/D Converter with novel binary tree architecture that has been recently presented, an appropriate current mirror architecture supported by real time calibration logic is described in this paper. This mirror can generate a high enough output current (up to 1 mA), with relatively low transfer error (<4%), in a descent frequency range of up to 1 GHz. It requires a 1–1.2 V voltage supply and dissipates a power that can be as low as 0.3 mW. The error is measured using mismatch and process variation Monte Carlo post-layout simulations in TSMC 90 nm process.     

High-performance solution-processed polymer space-charge-limited transistor

We demonstrate a polymer non-field-effect transistor in a vertical architecture with an Al grid embedded in a polymer sandwiched between another two electrodes. The Al grid containing high density of self-assembled submicron openings is fabricated by a non-lithography method. This device modulates the space-charge-limited current of a unipolar polymer diode with the Al grid. The operating voltage of the device is as low as 4 V, the on/off ratio is higher than one hundred, and the current gain is 10⁴. The current density is higher than 1 mA/cm².     

A liquid cooling solution for temperature redistribution in 3D IC architectures

The advancement of contemporary three-dimensional integrated circuit (3D IC) technologies offers a promising solution for the insatiable demand of the consumer electronics market. The increased complexity of 3D IC design permits the execution of multiple applications at greater speeds whilst remaining within the design constraints of energy consumption, yield and time-to-market. However, the increased computing performance and compact size may introduce a thermal barrier inhibiting performance, particularly in the case where multiple logic die are stacked and co-aligned hotspots are induced. To mitigate this thermal barrier a novel integrated active thermal solution is investigated in this paper whose purpose is to alleviate hotspots in a contemporary two-die 3D IC architecture. The solution employs a series of integrated microchannels, which permits the transfer of heat, via a coolant, from lower to upper strata. This microfluidic system is driven by a series of integrated AC electrokinetic pumps embedded in the channel walls. Recent advancements in electrokinetic micropump technology have allowed greater increases in fluid velocity – to an order of mm/s – while operating within the voltage constraints of a 3D IC. Numerically qualitative and quantitative temperature distributions are presented for a 3D IC chip design both with and without microchannels for a constant heat flux on the active layer of each silicon chip. The implementation of a microchannel network is shown to alter the thermal distribution map within a 3D IC package creating hot and cold zones with variations on temperature of ?14.6 °C≤ΔT≤9.8 °C with a ΔT_max of ?6.5 °C in the silicon die stack (equivalent to a total maximum heat flux, q_max″, of approximately 112.5 W/cm²). Increasing bulk fluid velocity, within the range 1.3 mm/s≤u_avg≤13 mm/s, can vary the area of the cold zone enhancing heat transfer and reducing the temperature of the die stack without an overall temperature change in the package.     

Scaling down of organic complementary logic gates for compact logic on foil

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm² per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm²/V s with V_on close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at V_dd as low as 2.5 V and the inverter stage delay at V_dd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors.     

High open-circuit voltage polymer solar cells based on D–A copolymer of indacenodithiophene and fluorine-substituted benzotriazole

A medium band gap D–A copolymer of indacenodithiophene (IDT) and fluorinated dithienylbenzotriazole (FBTA), PIDT-FBTA, was synthesized for the application as donor material in polymer solar cells (PSCs). PIDT-FBTA showed deeper highest occupied molecular orbital (HOMO) energy level due to the strong electron-withdrawing difluorine substitution on benzotriazole acceptor unit in the D–A copolymer. The PSCs based on PIDT-FBTA:PC₇₀BM (1:3) exhibited a high V_oc of 0.90 V and a power conversion efficiency (PCE) of 3.62% under the illumination of AM 1.5G, 100 mW cm⁻². The device performance was further improved by methanol treatment with PCE increased to 4.90% and V_oc increased to 0.92 V.     

Efficient fluorescent white organic light-emitting diodes with blue-green host of di(4-fluorophenyl)amino-di(styryl)biphenyl

Efficient fluorescent white organic light-emitting diodes are fabricated with the use of an efficient electro-fluorescence blue-green host material di(4-fluorophenyl)amino-di(styryl)biphenyl, doped with red dye 4-(dicyano-methylene)-2-methyl-6-(julolidin-4-yl-vinyl)-4H-pyran. One resulting two-wavelength white emission device shows a maximum external quantum efficiency of 4.8% and a high power efficiency of 14.8 lm/W with 100 cd/m² at 3.8 V. The high efficiency may be attributed to the high electroluminescence character of the host, relatively high host-to-guest energy transfer efficiency, and effective device architecture.     

Efficient simplified orange and white phosphorescent organic light-emitting devices with reduced efficiency roll-off

Efficient orange phosphorescent organic light-emitting devices based on simplified structure with maximum efficiencies of 46.5 lm/W and 51.5 cd/A were reported. One device had extremely low efficiency roll-off with efficiencies of 50.6 cd/A, 45.0 cd/A and 39.2 cd/A at 1000 cd/m², 5000 cd/m² and 10,000 cd/m² respectively. The reduced efficiency roll-off was attributed to more balanced carrier injection and broader recombination zone. The designed simplified white device showed much lower efficiency roll-off than the control one based on multiple emitting layers. The efficiency of simplified white device was 40.8 cd/A at 1000 cd/m² with Commission Internationale de I’Eclairage coordinates of (0.39, 0.46).     

ESD issues in advanced CMOS bulk and FinFET technologies: Processing,protection devices and circuit strategies

The ESD performance of several CMOS bulk and SOI technologies is reviewed. The ESD area-efficiency of FinFETs is put in relation to bulk and SOI. CMOS bulk technologies have improved over the past generations owing to the possibility of reduced ESD layout dimensions. While having observed It2 values of less than 2 mA/μm² in 130 nm technology, we are able to obtain almost 4 mA/μm² in 45 nm. Downscaling will shift the challenge for a robust ESD design from the ESD protection device in the IO cell to the metal routing and voltage clamping in the supply tree. This will increase cost and effort for ESD protection of modern IC’s in spite of improvement in It2.For FinFET technologies, the influence of device layout, electrical operation modes and processing is discussed. The initially extremely low ESD values of FinFETs have been strongly improved by overall process maturity and added process features. The ESD levels of FinFET technologies are now scalable up to the levels compliant with full IC design constraints. While the area-performance is still about two times lower than in bulk CMOS, it is much better than anticipated earlier.In light of the challenges ahead for technology and circuit applications, the impact on ESD protection strategies is studied. Classical protection approaches are critically examined regarding the latest technology developments and new requirements for IO interface circuits. A switch from bulk to FinFET technology is still regarded as a major disruption for product architecture and thus ESD.