Fast thermal analysis for fixed-outline 3D floorplanning

Three dimensional integrated circuits (3D ICs) can alleviate the problem of interconnection, a critical problem in the nanoscale era, and are also promising for heterogeneous integration. However, the thermal challenge in industry is one of key obstacles to adopt the 3D ICs technology. Various thermal analysis models for 3D IC have been proposed in literature. However, the long simulation cycle makes runtime of thermal management inefficient during floorplanning phase. In this paper, we propose a fast thermal analysis method for fixed-outline 3D floorplanning. Before floorplanning, we simulate the thermal distribution of each block placed on different positions. Based on the simulated thermal profiles, bilinear interpolation is adopted to quickly estimate temperature during floorplanning. After the block planning, a heuristic method, which combines the shortest path and min-cost-max-flow, is presented for TSV allocation with minimization of chip temperature and wirelength. Compared with the superposition of thermal profiles method, the proposed thermal analysis method can reduce the peak temperature by 6.7% on average with short runtime for 3D fixed-outline floorplanning, which demonstrates the efficiency and effectiveness of the proposed thermal analysis method.     

固定边框的多电压布图规划算法

多电压设计是应对SoC功耗挑战的一种有效方法,但会带来线长、面积等的开销。为减少线长、芯片的空白面积及提高速度,提出了一种改进的固定边框多电压布图方法.对基于NPE（Normalized Polish Expression）表示的布图解,采用形状曲线相加算法来计算其最优的布图实现,并通过增量计算方法来减少计算NPE及多电压分配的时间.为使所得布图解满足给定的边框约束,提出了一个考虑固定边框约束的目标函数,并采用删除后插入（Insertion after Delete,IAD）算子对SA求得布图解进行后优化.实验结果表明,和已有方法相比,所提出方法在线长和空白面积率方面有较明显优势,且所有电路在不同高宽比、不同电压岛数下均实现了极低的空白面积率（< <1%）.     

Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine

Multi-supply voltage (MSV) technique is one of the efficient ways to reduce power consumption. However, MSV makes the physical design much more complicated. Especially, the randomized algorithm consumes much time as the size of the problem increases and the constraint of rectangular shaped voltage island limits better solutions in terms of power. In this paper, a nonrectangular shaped voltage island (NSVI) aware floorplanning is proposed with nonrandomized searching engine for efficient floorplanning. With a generalized slicing tree, a hypergraph is generated according to the cores' legal voltage levels, which is favorable to cluster cores working under the same voltage level together so that the called NSVIs can be generated easily. The proposed approach can deal with the fixed-outline floorplanning and perform well under different aspect ratios. Experimental results on GSRC benchmark suites indicate that the proposed method can obtain better solutions with less CPU time than published methods.     

Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints

3-D (stacked device layers) ICs can significantly alleviate the interconnect problem coming with the decreasing feature size and is promising for heterogeneous integration. In this paper, we concentrate on the configuration number and fixed-outline constraints in the floorplanning for 3-D ICs. Extended sequence pair, named partitioned sequence pair (in short, P-SP), is used to represent 3-D IC floorplans. We prove that the number of configuration of 3-D IC floorplans represented by P-SP is less than that of planar floorplans represented by sequence pair (SP) and decreases as the device layer number increases. Moreover, we applied the technique of block position enumeration, which have been successfully used in planar fixed-outline floorplanning, to fixed-outline multi-layer floorplanning. The experimental results demonstrate the efficiency and effectiveness of the proposed method.     

Fixed-outline floorplanning: enabling hierarchical design

Classical floorplanning minimizes a linear combination of area and wirelength. When simulated annealing is used, e.g., with the sequence pair representation, the typical choice of moves is fairly straightforward. In this paper, we study the fixed-outline floorplan formulation that is more relevant to hierarchical design style and is justified for very large ASICs and SoCs. We empirically show that instances of the fixed-outline floorplan problem are significantly harder than related instances of classical floorplan problems. We suggest new objective functions to drive simulated annealing and new types of moves that better guide local search in the new context. Wirelength improvements and optimization of aspect ratios of soft blocks are explicitly addressed by these techniques. Our proposed moves are based on the notion of floorplan slack. The proposed slack computation can be implemented with all existing algorithms to evaluate sequence pairs, of which we use the simplest, yet semantically indistinguishable from the fastest reported . A similar slack computation is possible with many other floorplan representations. In all cases the computation time approximately doubles. Our empirical evaluation is based on a new floorplanner implementation Parquet-1 that can operate in both outline-free and fixed-outline modes. We use Parquet-1 to floorplan a design, with approximately 32000 cells, in 37 min using a top-down, hierarchical paradigm.     

面向软模块的稳定固定边框布图规划算法

该文提出一种稳定的面向软模块的固定边框布图规划算法。该算法基于正则波兰表达式(Normalized Polish Expression, NPE)表示,提出一种基于形状曲线相加和插值技术的计算NPE最优布图的方法,并运用模拟退火(Simulation Annealing, SA)算法搜索最优解。为了求得满足固定边框的布图解,提出一种基于删除后插入(Insertion After Delete, IAD)算子的后布图优化方法。对8个GSRC和MCNC电路的实验结果表明,所提出算法在1%空白面积率的边框约束下的布图成功率接近100%,在总线长上较已有文献有较大改进,且在求解速度上较同类基于SA的算法有较大优势。     

Multi-scale Single Image Super-Resolution with Remote-Sensing Application Using Transferred Wide Residual Network

In the integrated circuit (IC) designing floorplanning is an important phase in the process of obtaining the layout of the circuit to be designed. The floorplanning determines the performance, size, yield, and reliability of VLSI ICs. The obtained results in this step are necessary for the other consecutive process of the chip designing. VLSI floorplanning from the computational point of view is a non-polynomial hard (NP-hard problem), and hence cannot be efficiently solved by the classical optimization techniques. In this paper, we have proposed a metaheuristic approach to address the problem by using the parallel particle swarm optimization (P-PSO) technique. The P-PSO uses a new greedy operation on the sequence pair (SP) to explore the search space to find an optimal solution. Experimental results on the Microelectronic Centre of North Carolina and Gigascale Systems Research Center benchmark shows that the applied parallel PSO (P-PSO) may be used to produce an optimal solution.

     

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization

Three-dimensional (3-D) IC physical design problems are usually of higher complexity, with a greatly enlarged solution space due to multiple device structure. In this paper, a new 3-D floorplanning algorithm is proposed for wirelength optimization. Our main contributions and results can be summarized as follows. First, a new hierarchical flow of 3-D floorplanning with a new inter-layer partitioning method. The blocks are partitioned into different layers before floorplanning. A simulated annealing (SA) engine is used to partition blocks with the objective of minimizing the statistical wirelength estimation results. The solution quality is not degraded by the hierarchical flow. Second, floorplans of all the layers are generated in a SA process. Original 3-D floorplanning problem is transformed into solving several 2-D floorplanning problems simultaneously. The solution space is scaled down to maintain a low design complexity. Finally, Experimental results show that our algorithm improves wirelength by 14%-51% compared with previous 3-D floorplanning algorithms. The hierarchical approach is proven to be very efficient and offers a potential way for high-performance 3-D design     

Bus-driven floorplanning with thermal consideration

As the increasing number of buses in multi-core SoC designs, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, these proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots, which result in high chip temperature, on the chip. In this paper, a thermal-driven bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles, which are the thermal distribution of each module, is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplanner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature.     

Thermal modeling and analysis of 3D multi-processor chips

As 3D chip multi-processors (3D-CMPs) become the main trend in processor development, various thermal management strategies have been recently proposed to optimize system performance while controlling the temperature of the system to stay below a threshold. These thermal-aware policies require the envision of high-level models that capture the complex thermal behavior of (nano)structures that build the 3D stack. Moreover, the floorplanning of the chip strongly determines the thermal profile of the system and a quick exploration of the design space is required to minimize the damage of the thermal effects.This paper proposes a complete thermal model for 3D-CMPs with building nano-structures. The proposed thermal model is then used to characterize the thermal behavior of the Niagara system and expose the strong influence of the chip floorplanning in the thermal profile.     

Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture

The increasing gap between design productivity and chip complexity and the emerging systems-on-chip (SoCs) architectural template have led to the wide utilization of reusable hard intellectual property (IP) cores. Macro block-based physical design implementation needs to find a well-balanced solution among chip area, on-chip communication energy, and critical communication path delay. We present in this paper an automated way to implement an energy optimal netlist interconnecting the hard macro blocks using a heavily segmented communication architecture. We explore the entire tradeoff curve among the network energy, chip area, and critical communication path delay at the floorplanning stage based on two real-life application drivers. Large energy gains with small area overheads are illustrated during the floorplanning stage. This tradeoff profile is a good guideline for the SOC designers to choose the optimal solution for their specific systems.     

Tomlinson-Harashima Precoding for Broadcast Channels with Uncertainty

We consider the design of Tomlinson-Harashima (TH) precoders for broadcast channels in the presence of channel uncertainty. For systems in which uplink-downlink reciprocity is used to obtain a channel estimate at the transmitter, we present a robust design based on a statistical model for the channel uncertainty. We provide a convex formulation of the design problem subject to two types of power constraints: a set of constraints on the power transmitted from each antenna and a total power constraint. For the case of the total power constraint, we present a closed-form solution for the robust TH precoder that incurs essentially the same computational cost as the corresponding designs that assume perfect channel knowledge. For systems in which the receivers feed back quantized channel state information to the transmitter, we present a robust design based on a bounded model for the channel uncertainty. We provide a convex formulation for the TH precoder that maximizes the performance under the worst-case channel uncertainty subject to both types of power constraints. We also present a conservative robust design for this type of channel uncertainty that has reduced computational complexity for the case of power constraints on individual antennas and leads to a closed-form solution for the total power constraint case. Simulation studies verify our analytical results and show that the robust TH precoders can significantly reduce the rather high sensitivity of broadcast transmissions to errors in channel state information.     

Thermal‐Aware Floorplanning with Min‐cut Die Partition for 3D ICs

Three‐dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through‐silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal‐aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal‐aware floorplanning with min‐cut die partitioning for 3D ICs. The proposed min‐cut die partition methodology minimizes the number of connections between partitions based on the min‐cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal‐aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run‐time.     

Floorplanning for low power IC design considering temperature variations

Non-uniformity in thermal profiles of integrated circuits (ICs) is an issue that threatens their performance and reliability. This paper investigates the correlation between the total power consumption and the temperature variations across a chip. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. It is demonstrated that optimizing a floorplan to minimize either the leakage or the peak temperature can lead to a significant increase in the total power consumption. In this paper, the experimental results show that lowering the temperature variations across a chip not only addresses performance degradation and reliability concerns, but also significantly contributes to chip power reduction. In addition, it is found that although uniformity in the thermal profile can be very effective in lowering the total power consumption, the most uniform temperature distribution does not necessarily correspond to the highest power savings. Consequently, for some applications, a 2% deviation from the minimum total power is traded for up to a 25% increase in thermal uniformity. The presented method is implemented for an Alpha 21264 processor running Spec 2000 benchmarks.     

A fast bit-loading algorithm for high speed power line communications

Adaptive bit-loading is a key technology in high speed power line communications with the Orthogonal Frequency Division Multiplexing (OFDM) modulation technology. According to the real situation of the transmitting power spectrum limited in high speed power line communications, this paper explored the adaptive bit loading algorithm to maximize transmission bit number when transmitting power spectral density and bit error rate are not exceed upper limit. With the characteristics of the power line channel, first of all, it obtains the optimal bit loading algorithm, and then provides the improved algorithm to reduce the computational complexity. Based on the analysis and simulation, it offers a non-iterative bit allocation algorithm, and finally the simulation shows that this new algorithm can greatly reduce the computational complexity, and the actual bit allocation results close to optimal.     

Recent advances in VLSI layout

The current status of VLSI layout and directions for future research are addressed, with emphasis on the authors' own work. Necessary terminology and definitions and, whenever possible, a precise formulation of the problems are provided. Placement and floorplanning for both the sea-of-gates and building-block designs are examined. The former emphasizes the connectivity specification, whereas the latter must also consider module shape and size. Global routing based on a method of successive cuts on a chip is discussed. This is a hierarchical top-down approach that is useful for both of the above designs. A two-dimensional detailed routing problem and the rip-up and rerouting problem are also discussed. The field of computational geometry and its application to layout-in particular, to gridless routing and compaction-are reviewed, and layout engines are considered     

Novel Low-Complexity Partial Transmit Sequences Scheme for PAPR Reduction in OFDM Systems Using Adaptive Differential Evolution Algorithm

A low-complexity partial transmit sequence (PTS) technique for reducing the peak-to-average power ratio (PAPR) of an orthogonal frequency division multiplexing signal is presented. However, the conventional PTS scheme requires an exhaustive searching over all combinations of allowed phase factors. Consequently, the computational complexity increases exponentially with the number of the subblocks. This paper presents a novel approach to the PAPR problem to reduce computational complexity based on the relationship between phase weighing factors and transmitted bit vectors. In this paper, we aim to obtain the desirable PAPR reduction with the low computational complexity. Since the process of searching the optimal phase factors can be categorized as combinatorial optimization with some variables and constraints, we propose a novel scheme, which is based on a stochastic optimization technique called modified differential evolution, to search the optimal combination of phase factors with low complexity. To validate the analytical results, extensive simulations have been conducted, showing that the proposed schemes can achieve significant reduction in computational complexity while keeping good PAPR reduction.     

PAPR Reduction of OFDM Signals Using Partial Transmit Sequences With Low Computational Complexity

Partial transmit sequences (PTS) is one of the attractive techniques to reduce the peak-to-average power ratio (PAPR) in orthogonal frequency division multiplexing (OFDM) system. As conventional PTS technique requires an exhaustive searching over all the combinations of the given phase factors, which results in the computational complexity increases exponentially with the number of the sub-blocks. In this paper, we aim to obtain the desirable PAPR reduction with the low computational complexity. Since the process of searching the optimal phase factors can be categorized as combinatorial optimization with some variables and constraints, we propose a novel scheme, which is based on a nonlinear optimization approach named as simulated annealing (SA), to search the optimal combination of phase factors with low complexity. To validate the analytical results, extensive simulations have been conducted, showing that the proposed schemes can achieve significant reduction in computational complexity while keeping good PAPR reduction.     

3D IC floorplanning: Automating optimization settings and exploring new thermal-aware management techniques

The introduction of 3D chip architectures is an increasingly attractive integration solution due to the potential performance improvement, power consumption reduction and heterogeneous integration. Nevertheless, thermal distribution, evacuation and limitation constitute some of the key issues that can hinder widespread adoption of 3D integration technology. Efficient 3D floorplan algorithms have to be developed to address such complexity. In this paper we first discuss the implementation of such an algorithm and identify parameters that play a role in the solution quality. We then propose the use of a genetic algorithm to discover sets of parameters that guarantee good ?oorplan quality. Then, we present an improved thermal-aware ?oorplanner based on a new formulation of the cost function that minimizes not only peak temperature, but also thermal gradients. The temperature minimization goal is reinforced using a smart heuristic that guides 3D moves in the direction of placing power hungry blocks next to the heat sink. Experimental results show the ability of the method to reduce the temperature peak and gradient signi?cantly, while maintaining area, wirelength and computation time.     

PAPR reduction of an OFDM signal by use of PTS with low computational complexity

One of the major drawbacks of orthogonal frequency division multiplexing (OFDM) is the high peak-to-average power ratio (PAPR) of the transmitted OFDM signal. Partial transmit sequence (PTS) technique can improve the PAPR statistics of an OFDM signal. However optimum PTS (OPTS) technique requires an exhaustive search over all combinations of allowed phase factors, the search complexity increases exponentially with the number of sub-blocks. By combining sub-optimal PTS with a preset threshold, a novel reduced complexity PTS (RC-PTS) technique is presented to decrease the computational complexity. Numerical results show that the proposed approach can achieve better performance with lower computational complexity when compared to that of other PTS approaches.