12—18GHz宽带功率低噪声固态放大器

研制开发了１２－１８ＧＨｚ宽带功率固态放大器，主要技术指标：工作频率为１２－１８ＧＨｚ，增益Ｇｐ≥２５ｄＢ，输出功率ＰＯ≥４００ｍＷ输入输出驻波比ＶＳＷＲ≤２．５：１，噪声系数Ｆａ≤６ｄＢ。     

6～18GHz宽带功率放大器模块

研究了ＧａＡｓ功率ＭＥＳＦＥＴ的小信号特性、大信号特性和其宽带匹配网络。选用ＴＷＴ－２型功率器件，设计研制出了单级宽带功率放大器。在６～１８ＧＨｚ的工作频率范围内，小信号增益等于５．０±１．０ｄＢ，１ｄＢ压缩输出功率等于２５．０±０．８ｄＢｍ，输入输出驻波比小于２．５。     

6～18GHz宽带功率放大器模块

研究了ＧａＡｓ功率ＭＥＳＦＥＴ的小信号特性，大信号特性和其宽带匹配网络。选用ＴＷＴ－２型功率器件，设计研制出了单级宽带功率放大器，在６～１８ＧＨｚ的工作频率范围内，小信号增益等于５．０±１．０ｄＢ，１ｄＢ压缩输出功率等于２５．０±０．８ｄＢｍ，输入输出驻波比小于２．５。     

2～18GHz超宽带射频放大器

采用分布电路原理、ＣＡＤ技术和微带电路技术，制作出多倍频程超宽带放大器。其主要技术参数为，ｆ＝２～１８ＧＨｚ，Ｇ＿ｐ≥３０ｄＢ，△Ｇ＿ｐ≤±３ｄＢ，Ｆ＿ｎ≤７ｄＢｍ，Ｐ＿（－１）≥＋１０ｄＢ，ＶＳＷＲ≤２．５：１。     

宽带GaAs MMIC放大器

Ｍ／Ａ-ＣＯＭ研制的ＭＡＡＭ２８０００-Ａ１型宽带ＭＭＩＣ放大器的工作频率为２～８ＧＨｚ,它采用２级放大,单电源１０Ｖ供电,具有较好的增益平坦度,输入输出阻抗均为５０Ω,增益为１７ｄＢ,增益平坦度为±０．５ｄＢ,在２～４ＧＨｚ、４～６ＧＨｚ和６～８ＧＨｚ时的最大噪声分别为８．０ｄＢ、６．５ｄＢ和６．０ｄＢ,输入和输出驻波比分别为１．６和１．５,输入ＩＰ３为+７ｄＢｍ,输出１ｄＢ压缩为+１．４ｄＢｍ,反向隔离为３５ｄＢ,最大偏压电流为１００ｍＡ。该器件采用廉价的小型８脚陶瓷封装,不需要任何外部元件,可用于卫星通…     

Ka波段功率PHEMT的设计与研制

报道了Ｋａ 波段功率ＰＨＥＭＴ的设计和研制结果。利用双平面掺杂的ＡｌＧａＡｓ／ＩｎＧａＡｓＰＨＥＭＴ材料,采用０．２ μｍ 的Ｔ型栅及槽型通孔接地技术,研制的功率ＰＨＥＭＴ的初步测试结果为：Ｉｄｓｓ：３６５ ｍ Ａ／ｍ ｍ ;ｇｍ ０：３２０ ｍ Ｓ／ｍ ｍ ;Ｖｐ：－ １．０～－ ２．０ Ｖ。总栅宽为７５０ μｍ 的功率器件在频率为３３ ＧＨｚ时,输出功率大于２８０ ｍ Ｗ,功率密度达到３８０ ｍ Ｗ／ｍ ｍ ,增益大于６ ｄＢ。     

12～18GHz宽带功率低噪声固态放大器

研制开发了１２～１８ＧＨｚ宽带功率固态放大器。主要技术指标：工作频率为１２～１８ＧＨｚ，增益ＧＰ≥２５ｄＢ，输出功率ＰＯ≥４００ｍＷ，输入输出驻波比ＶＳＷＲ≤２．５∶１，噪声系数Ｆｎ≤６ｄＢ。     

6～20GHz宽带低噪声中功率放大器

本文介绍了６￣２０ＧＨｚ微波宽带低噪声,中功率放大器的研制工作。采用微波宽带匹配和ＣＡＤ技术,研制出了符合整机要求的放大器。主要性能指标：工作频率６￣２０ＧＨｚ,１ｄＢ压缩输出功率≥１８ｄＢｍ,增益≥２８ｄＢ,输入输出驻波比≤２．０：１,噪声系数≤４．０ｄＢ,增益平坦度≤±２．０ｄＢ。     

8—12GHz低噪声PHEMT单片集成电路

描述了以ＰＨＥＭＴ为有源器件的８￣１２ＧＨｚ宽带低噪声单片电路的设计及制造，获得了满意的结果。其性能为ｆ＝８￣１２ＧＨｚ，Ｇａ＝１７．４￣１９．５ｄＢ，Ｆｎ＝１．８４￣２．２０ｄＢ；ｆ＝８￣１４ＧＨｚ，Ｇａ＝１７．４￣１９．９ｄＢ，Ｆｎ＝１．８４￣１．５ｄＢ。     

8～16GHzGaAs单片宽带分布放大器

报道了８～１６ＧＨｚＧａＡｓ单片宽带分布放大器的设计与制作。单级ＭＭＩＣ电路采用三个栅宽为２８０μｍ的ＧａＡｓＭＥＳＦＥＴ作为有源器件，芯片尺寸为１．１ｍｍ×１．６ｍｍ。在８～１６ＧＨｚ频率范围，用管壳封装的两级级联放大器增益Ｇ＿ａ，为１１．３±１ｄＢ，噪声系数Ｆ＿ｎ＜６ｄＢ，输出功率Ｐ＿（１ｄＢ）＞１６ｄＢｍ。     

A robust, load-insensitive pad driver

A new approach to implement load-insensitive integrated pad drivers in monolithic integrated circuits is presented. The design utilizes a source follower topology along with a simple negative feedback approach to fix and control both rise and fall times independent of loading capacitance. This novel technique was used to implement a differential output pad driver for Universal Serial Bus design in a standard 0.35-μm/3-V CMOS technology. The two drivers occupy less than 0.15 mm² of die area and can handle a capacitive load of 0-100 pF and 0-800 pF for 1.2- and 1.5-Mbps data rates, respectively. Measured transition times for 1.2 Mbps (with 50 pF) and 1.5 Mbps (with 350 pF) data rates were 17 and 250 ns, respectively     

A new compensation technique for resistive level shifters

A compensation technique is introduced for resistive level-shifting stages that reduces the size of the compensating capacitor from 20-30 pF in conventional compensation to about 2-3 pF, making the stage more attractive for use in many analog ICs such as op amps, comparators, and wideband amplifiers     

An advanced PNP bipolar transistor design for a low-power and very-high-performance quarter-micron CBiCMOS process

This paper describes an advanced PNP bipolar transistor which has been designed by using the mixed two-dimensional device/circuit simulation (CODECS) [1] for a low-power and very-high-performance 0.25 μm complementary BiCMOS (CBiCMOS) device. The optimized PNP structure has a 30-nm-wide emitter, a 39-nm-wide intrinsic base region, a maximum cut-off frequency of 14 GHz and a current gain of 16 (without poly-Si emitter effect). A high performance and limits in terms of delay for pull-down of 0.25 μm CBiCMOS were obtained and compared to those offered by BiCMOS and complementary metal-oxide semiconductor circuits at different power supplies and charge capacitance. An improvement of 1.5 × at 1 pF, 1.6 × at 0.6 pF and 2 × at 0.2 pF over BiCMOS has been achieved.     

Compact current-mode loop filter for PLL applications

A novel capacitance scaling technique is proposed to reduce on-chip capacitor area using a dual-path self-biased current-mode filter. The capacitor multiplier is obtained by the relative ratio of charge-pump currents I/sub cp2//(I/sub cp2/-I/sub cp1/), rather than the scaling ratio I/sub cp2//I/sub cp1/. Compared with the original current-mode filter, the demonstrated loop filter of 250 pF capacitance is achieved with only 25 pF (90% die area saving), and the resistor area is reduced by 50% owing to reuse of the degenerated resistor R/sub G/.     

Storage array and sense/refresh circuit for single-transistor memory cells

For the cell layout in silicon-gate technology a storage capacitor is proposed that uses a field-induced nonequilibrium inversion layer as an electrode. As a sensitive refresh amplifier a gated flip-flop that can be used for one digit line at each of its two input nodes is presented. Different cells and refresh circuits have been realized in silicon-gate technologies. Cells with an area of 1600 /spl mu/m/SUP 2/(2.6 mil/SUP 2/) have been successfully operated with a READ/WRITE cycle time of 350 ns (storage capacitance 0.134 pF, digit line capacitance 0.32 pF for 64 cells per line or 128 cells per amplifier).     

Interdigitated pn junction device with novel capacitance/voltage characteristic, ultralow capacitance and low punch-through voltage

The first demonstration of the recently disclosed channelling diode is reported. The structure combines important and unique features which can be used for a large variety of applications. The diode exhibits a novel capacitance/voltage characteristic; large capacitance variations (1 pF) have been achieved over a small voltage range. Operated as a PIN diode the device has an ultralow capacitance (0.05 pF) and a low punch-through voltage (2?3 V). This small capacitance is largely independent of the detector area and of the doping of the layers. These features are important for ultralow noise PINFET receiver applications.     

Low-Power High-Drive CMOS Operational Amplifiers

Low-power CMOS op amps with high-drive capability and good settling characteristics are described. One circuit, occupying 150 mils/sup 2/ of active area and consuming 1 mW of power drives a capacitive load of up to 150 pF with greater than +-2.5 V/µs slew rates and less than 3.5 µs settling time to 0.1 percent. A somewhat larger circuit drives low-resistance (e.g., 600 Omega) and high-capacitance (1000 pF) loads with better slew rates and settling time. These circuits are suitable for applications in such systems as charge-redistribution codecs and switched-capacitor filters.     

激光锁定Fabry-Perot干涉仪精密测量电容

为了实现pF量级小电容的精密测量,建立了基于激光锁定Fabry-Perot干涉仪的精密电容测量系统。对该系统所采用的计算电容原理、激光锁定干涉仪方法及其整数级次确定方法进行了研究。首先,根据Lampard和Thompson电学基本原理介绍了Fabry-Perot干涉仪的结构与工作方式,采用一种锁定干涉仪测量位移的方法。其次,介绍了Fabry-Perot干涉仪的光路设计,详细分析了干涉仪锁定控制系统的工作状态以及锁定状态下干涉仪腔长的抖动情况。通过分析利用电容值确定干涉仪整数级次变化的可行性,提出了基于1 pF标准电容器确定Fabry-Perot干涉仪整数级次的实验过程。最后,介绍了Fabry-Perot锁定干涉仪的台阶式位移过程以及利用该套系统测量电容的重复性。实验结果表明:Fabry-Perot干涉仪在锁定状态下,腔长抖动峰峰值为0.4 nm,测量1 pF标准电容器重复性达到5.010-9。     

硅衬底上射频无源低通滤波器的设计及版图实现

文章系统地研究了微波无源低通滤波器的设计原理及其设计方法。根据网络综合法，设计出了一个—3dB截止频率为1．2GHz的2阶低通无源滤波器，其器件参数C1、L1、C2分别为2．56pF、13．252nH和2．56pF。采用自行设计的算法，编制了相应的Matlab程序，计算出滤波嚣的版图结构参数。最后，用ADS软件对该滤波器进行了版图级的模拟验证。结果表明，该微波无源滤波器的散射参数曲线与理想元件所组成的滤波器的散射曲线相吻合，且性能好，能够满足实际应用的需要。     

多晶硅衬底上的RF MEMS开关

在微机械开关与硅IC工艺设计和兼容方面进行了改进,获得了一种可与IC工艺兼容的RF MEMS微机械开关.采用介质隔离工艺技术把这种RF MEMS微机械开关制作在绝缘的多晶硅衬底上,实现了与IC工艺兼容;采用在金属膜桥的端点附近刻蚀一些孔的优化方法,降低了RF MEMS微机械开关的下拉电压.用TE2819电容测试设备测试开关的电容,测得开关的开态电容、关态电容和致动电压分别为0.32pF、6pF和25V.用HP8753C网络分析仪对RF MEMS微机械开关进行了RF特性测试,得出RF MEMS微机械开关在频率1.5GHz下关态的隔离度为35dB,开态的插入损耗为2dB,用示波器测得该开关的开关速度为3μs.