Design of a single-chip digital lattice equalizer filter

One lattice equalizer stage is designed on a single chip using 4-/spl mu/m NMOS technology. All the arithmetic operations of the chip are performed bit-serially under the control of a global two-phase clock, and they are totally pipelined. The data are represented as 16-bit two's complement fixed-point numbers. A built-in test scheme allows the offline testing of the chip with high fault coverage at a minimal hardware overhead. Direct coupling between chips permits the realization of filters of higher order. In addition, the structure of the lattice equalizer permits the use of the same chip in linear prediction problems. SPICE simulation results and fabrication of the major blocks in the design demonstrated that operating clock frequencies of up to 8 MHz are possible. At the maximum estimated operating clock frequency, the chip can accommodate applications with data rates of up to 500 kHz.     

Sensitivity formulas for digital lattice filters

Formulas are given for the sensitivities of the transfer function with respect to the k-parameters in a digital lattice structure.     

Design of optimal digital lattice filter structures based on genetic algorithm

In this paper, a new class of lattice-based digital filter structures is derived. The optimum structure problem is formulated in terms of minimizing the signal power ratio with respect to the two sets of free parameters in the proposed structures. An efficient genetic algorithm is proposed to solve the optimum structure problem with the constraint on the structure parameters to be represented in signed power-of-two format. Two design examples are given, in which the optimized structures show excellent finite wordlength properties such as very low parameter sensitivity and very uniform signal powers across signal nodes and outperform the classical lattice structures.     

数字视频降分辨率算法的滤波器设计

数字视频在不通终端上应用时往往需要将分辨率降低到原始分辨率的1/2或1/4。因而需要有合适的算法改善降分辨率后图像的清晰度,满足用户对显示图像质量的要求。基于视频转码的需要,针对分辨率转换算法中最常用的滤波与子采样法,设计了一种用于滤波与子采样法的5阶数字滤波器,并在编译器上进行仿真验证与评估。仿真结果显示,新滤波器表现出优异的峰值信噪比,并且在分块算法中依然优异。总之,这里提出的方法不但复杂度适中,适应性强,而且能够高效、高质量地完成数字视频降分辨率。     

Synthesis of a periodically time-varying digital filter

The paper presents an approximate method of periodically linear time-varying (PLTV) digital filter (DF) synthesis through mean values of their coefficients in time. The recursive and nonrecursive PLTV DFs of the first, second and arbitrary orders are considered. It is shown that PLTV DFs have distinguishing features which give them advantages in some applications in comparison with linear time-invariant (LTI) DFs     

State-space description of a multirate digital filter

The concept of multirate sampling in a digital filter is discussed, and a generalised method using the state-space technique of describing and analysing a 2nd-order multirate digitalfilter is presented.     

Method of data reduction of sampled speech signals by using nonuniform sampling and a time-variable digital filter

A method of data reduction applicable to sampled continuous signals, for example, sampled speech signals, is described and tested by computer simulation, Nonuniform sampling obtained through skipping of samples is used. The reconstruction network is a time-variable digital filter. A minimisation procedure for coefficient derivation is described.     

Linear-phase digital anti-aliasing filter

A simple digital technique is described for prefiltering a signal to reduce aliasing errors in a subsequent main digital filtering operation. Unlike analogue prefilters, this new filter has a linear phase characteristic.     

数字滤波器在数字信号处理中的应用设计

在信号处理中,滤波占有十分重要的地位.数字滤波是数字信号处理的基本方法,以FIR滤波器为基础,利用MATLB程序设计语言对低通FIR数字滤波器进行了有效的设计,应用DSP 汇编语言编程实现了该滤波器.     

Sampling rate selection for a digital matched filter

The problem of selecting the sampling rate for the digital implementation of a matched filter for noncoherent digital communications is considered. The effects of bandwidth reduction and sampling are evaluated. A Nyquist rate of 8 samples per bit is found to be the critical value even with respect to the dependence on the carrier phase.     

Top-down design of a VLSI digital filter bank

This paper relates theoretical investigations in digital signal processing (DSP) to the design of a VLSI digital filter bank (DFB). Emphasis is on a top-down approach to identify multilevel parallelisms inherent in a generic DSP algorithm and a new VLSI architecture. System level control and communication requirements are examined. Finite word length effects on filter accuracy are identified. The complexity of filter modules is reduced by partitioning large filter functions into a sum of smaller subfunctions. A memory intensive architecture minimizes design time. Up to 100 DRF modules are configured in parallel to perform signal processing up to 20 MHz. This VLSI DFB out performs sequential von Neumann architectures by several orders of magnitude using the same level of VLSI technology.     

Adaptive LMS filter with lattice prefilter

A filter structure consisting of a lattice predictor to function as a prefilter and a bank of subfilters using backward predictor errors is presented. It can realise a general transversal transfer function, has a good convergence rate, and is insensitive to the eigenvalue spread, even when a low order lattice predictor is used     

一种Farrow结构数字延时滤波器的设计

普通数字延时滤波器虽然结构简单,但系数计算过程复杂,在延时参数快速变化时,系数更新速度无法满足实时性要求,在工程应用上受限制。采用Farrow结构数字延时滤波器能够更加灵活高效地进行分数延时滤波,延时参数改变时,无需重新计算滤波器系数,更容易在现场可编程门阵列(FPGA)上实现。介绍了一种Farrow结构数字延时滤波器,提出采用基于对称结构的滤波器系数求解方法,并经过加权优化,获得最终Farrow滤波器的系数。系数计算过程中,通过对设计所得Farrow滤波器延时精度和误差的分析,调整加权因子的取值和滤波器阶数,进而提高延时精度。计算机仿真结果证明了加权对称系数求解Farrow滤波器系数方法的有效性和实用性。     

A pipelined adaptive lattice filter architecture

The stochastic gradient adaptive lattice filter is pipelined by the application of relaxed look-ahead. This form of look-ahead maintains the functional behavior of the algorithm instead of the input-output mapping and is suitable for pipelining adaptive filters. The sum and product relaxations are employed to pipeline the filter. The hardware complexity of the pipelined filters is the same as for the sequential filter and is independent of the level of pipelining or speedup. Two pipelined architectures along with their convergence analyses are presented to illustrate the tradeoff offered by relaxed look-ahead. Simulation results supporting the conclusions of the convergence analysis are provided. The proposed architectures are then employed to develop a pipelined adaptive differential pulse-code modulation (DPCM) codec for video compression applications. Speedup factors up to 20 are demonstrated via simulations with image data     

新型文字电话中数字滤波器的设计

文中介绍了应用在新型文字电话中的数字滤波器设计技术,这种电话使用了dsPIC33F系列微处理器。采用dsPIC单片机专用数字滤波器辅助设计软件包进行设计,把最佳CSD编码技术与Horner算法相结合对该滤波器进行优化。实验结果表明优化之后的滤波器大大缩短了滤波计算所需要的时间,更能满足系统实时通信的要求。     

Minimizing quantization effects in a practical second-order digital filter bank

The paper describes the solution to coefficient and product-quantization effects in a practical, real-time digital filter bank. The solution to the coefficient-quantization effects involves simple manipulation of the floating-point filter coefficients. A computer simulation of product-quantization errors enables the appropriate number of bits for the truncated products to be determined.     

State-space approach to the multiplication error in a digital filter

The state-space method has been used to evaluate the statistical error due to the finite-precision arithmetic in a digital filter. The actual error of a 2nd-order filter obtained from computer simulation has also been plotted against the expected error     

Jitter reduction of a digital phase-locked loop

This letter presents a jitter reduction technique for the digital phase-locked loop proposed by G. Pasternack and R. L. Whalin. In this technique, the lower N bits of load data from the first register are cut down and loaded into the final register as the round-off data. According to the experimental results, rounding off 5 bits in the second-order loop causes jitter to be reduced by 19.5 dB; therefore, this technique is useful for carrier tracking applications.     

Implementation of a tracking Kalman filter on a digital signalprocessor

A Kalman filter for tracking moving objects has been implemented on a TMS32010 digital signal processor. Tracking accuracy and quantization effects of the implementation have been measured by comparing the filter to one implemented on a general-purpose computer with a 32 bit word length. The filter design has been optimized to minimize the program memory requirements and execution speed. Although the filter has been implemented on a specific signal processing chip, the design is general enough to be applicable to any other digital signal processor. The filter can be used for tracking objects for industrial or other applications where range and bearing measurements are available. For motion on a plane, the filter can be used to track objects where the maximum system bandwidth is 1680 Hz; for three-dimensional motion the system bandwidth is 1120 Hz. Using the approach presented, higher system bandwidth can be accommodated through higher-speed digital signal processors