Analytical calculation for DC inductances of rectangular spiral inductors with finite metal thickness in the PEEC formulation

Inductances of rectangular spiral inductors with finite metal thickness are evaluated by the partial element equivalent circuit (PEEC) technique. The six-fold partial self and mutual inductance integrals resulting from the PEEC partitions are found to have analytical expressions, so that the singularities of the integrands can be overcome and the theoretical or "exact" results can be obtained very efficiently. Via and underpath required for input/output connection can also be included in the calculation. Calculated inductance values for 20 square spiral inductors are checked against measured data published in open literature. Dependence of inductance values on metal thickness is investigated for two specific spiral structures.     

An efficient DC fault simulation algorithm for nonlinear circuits

An efficient DC fault simulation algorithm for nonlinear circuits is proposed in which Householder’s transform and the method of partitioned matrices are used to minimize the number of operations for fault simulation. The algorithm is also applicable to DC analysis for nonlinear circuits.     

An explicit knowledge-embedded space mapping technique and its application to optimization of LTCC RF passive circuits

A novel explicit knowledge embedded space mapping (SM) optimization technique is presented in this paper. It generalizes the implementation procedure of the efficient SM technique by introducing a buffer space called embedded knowledge space between the original coarse model space and the fine model space, where the ingredients of the coarse model space can be completely different from those of the fine model space. Therefore, this generic scheme can be used to map the coarse model space of arbitrary physical content to the fine model space of different physical content through the embedded knowledge space that is built up with the available radio frequency (RF) circuit CAD formula. The emphasis of the application of the proposed scheme is put on the design of low temperature cofired ceramic (LTCC) RF passive circuits in this paper, along with the required CAD formulas (knowledge) for typical embedded multilayer passives. The effectiveness of the proposed new scheme is demonstrated through two design examples of LTCC lumped element band pass filters for wireless applications. The detailed procedure and flowchart of the proposed implementation scheme are also given in the paper.     

Simple and accurate formulas for a microstrip with finite strip thickness

Simple and accurate dosed form expressions for variation of characteristic impedance and effective dielectric constant of microstrip with finite strip thickness are reported. The results are in good agreement with the numerical values. These expressions are useful for microstrips used in microwave integrated circuits and computers.     

An efficient algorithm for the global modeling of RF and microwave circuits using a reduced nonlinear lumped network (RNL/sup 2/N)-FDTD approach

In this letter, we present an efficient and simple reduced nonlinear lumped network (RNL/sup 2/N)-FDTD method for the global modeling of RF and microwave circuits. This method is a simplified version of the original nonlinear lumped network (NL/sup 2/N)-FDTD approach, which does not require a complicated precalculation and a huge back-storage compared to the former version.     

Fast location of high-order modes for boxed microstrip with finite strip thickness

Many analyses of boxed microstrip discontinuities require the location of large numbers of high-order modes. Using Sturm-Liouville theory, this letter derives a relationship between microstrip modes and slab-loaded guide modes, leading to an efficient mode location algorithm for microstrip, including microstrip with finite strip thickness.<>     

On the modeling of metal strip antennas contiguous with the edge ofelectrically thick finite size dielectric substrates

A solution to the problem of radiation by a narrow metal strip antenna contiguous with the edge of a dielectric substrate is presented where the substrate has parameters such that its electrical thickness is appreciable. Such an antenna may be useful at millimeter wavelengths as an integrated phased array element forming a part of a monolithic microwave integrated circuit (MMIC). A suitable geometry for this application is illustrated and an efficient computational procedure developed. Comparisons with experimental results for the input impedance and far-field radiation patterns show excellent agreement. The influence of the dielectric substrate on the performance of an antenna designed to operate at approximately 60 GHz is discussed. Two examples, the first involving the analysis of a coplanar strip transmission line fed antenna and the second involving impedance matching and control of cross-polarized radiation using a folded strip dipole, are given to illustrate practical applications of the analytical method to design problems     

State reduction for efficient digital calibration of analog/RF integrated circuits

Calibration of analog/radio-frequency (RF) integrated circuits addresses the problem of yield loss that is a result of the increased variability commonly observed in nanoscale processes. In order to compensate for increased yield loss, calibration techniques have been developed that are applied to fabricated chips, aiming at the restoration of a circuit’s performance to its acceptable range of values that are defined by the specifications. To allow calibration, adjustable elements are introduced that provide multiple states of a circuit’s operation through built-in tuning knobs. Digital calibration—that refers to the case of discrete tuning knob settings—is performed by switching to a circuit’s state at which all performance characteristics are restored to their specified ranges. Due to the large number of performance characteristics of interest a large space of tuning knob settings should be explored, that leads to a series of practical considerations that need to be addressed, such as increased times required for calibration preparation and conduction, or chip area overhead if built-in tuning knobs are used. In this paper we present a method to maintain a desired level of yield recovery through the exploitation of only a minimum number of calibration states, also ensuring low cost by shortening calibration times and reducing chip area overhead. The proposed method is assessed through case studies conducted on a typical RF mixer designed in a 180 nm CMOS technology.     

AN EFFICIENT CIRCUIT VECTOR SPACE ALGORITHM FOR GENERATING ALL DIRECTED CIRCUITS OF A DIGRAPH

An efficient circuit vector space algorithm is presented for enumerating directed circuits ofa directed graph,by which every directed circuit is generated by the ring sum of a fundamental circuit anda subset of the obtained directed circuits,and can be expressed as a linear combination of a basic set of thedirected circuits.     

An efficient on-the-fly encoding algorithm for binary and finite field LDPC codes

We present a general framework on prototype structures for efficiently encoding low density parity check codes onthe- fly. The encoding algorithm is applicable to finite field based codes and can handle a wide range of high code rates and large block lengths. This structure can be used particularly in data storage and multimedia applications with increased code rate and throughput requirements. We also establish the necessary and sufficient conditions for the existence of such encoders.     

Tracking sensitivity: an efficient algorithm for linear nonreciprocal circuits

For the frequency-domain response of linear nonreciprocal circuits, an algorithm for computing component tracking-sensitivity has been devised. Rapid exploration of the effect is permitted by the very limited calculation associated with each value of the global variable. e.g. temperature, following an initial calculation common to all values of the global variable.     

An algorithm for designing multiplexer logic circuits

Several algorithms arc now available for designing combinational logic circuits using multiplexers. In the present paper, the authors propose an algorithm which loads to a design, in a simple way, to meet one of two objectives discussed in the paper. The authors feel that the algorithm is simpler than some of the existing methods involving similar objectives.     

有限厚度平面周期结构的快速算法研究

给出一种能够快速有效计算有限厚度平面周期结构电磁特性的积分方程矩量法,并对有限厚度的四腿加载单元频率选择表面的电磁特性做了详细的分析和研究。给出了不同金属屏厚度下频率选择表面的反射、传输特性,远场散射特性及表面电场分布。通过分析可知：在高频谐振情况下,金属屏厚度对其电磁特性具有较明显的影响。文中方法与高频结构仿真器（HFSS）计算所得结果取得了很好的一致性,同时,在计算时效上也得到了提高。     

An efficient algorithm for the three-dimensional analysis ofpassive microstrip components and discontinuities for microwave andmillimeter-wave integrated circuits

A numerical technique for the full-wave analysis of shielded, passive microstrip components on a two-layer substrate is presented. The distinct feature of the technique is an efficient formulation for establishing the system matrix in the moment method procedure which allows the derivation of the elements of any large matrix by a linear combination of elements in a precomputed index table. The table is obtained from a two-dimensional discrete fast Fourier transform. In the moment method procedure, the two-dimensional surface current is represented by locally defined rooftop functions. The effect of the resonant modes associated with the metallic enclosure on the numerical procedure is examined. In order to demonstrate the features and the accuracy of the technique, numerical results for a microstrip open end and for a right-angle bend with and without the compensated corner are computed by using the resonant technique and are compared with other published computational and experimental data     

An efficient reliability estimation method for CNTFET-based logic circuits

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.     

An efficient method for finding DC solutions for Josephson circuits

The formulation of Josephson circuit equations in the DC state is discussed and a mixed-mode approach that combines the nonlinear solution method of source-stepping and time-domain method of numerical integration is proposed. Since Josephson circuit equations are often multivalued, the mixed-mode algorithm follows the paths of the independent sources, detects ill-conditioned points, and converges to stable points on the characteristic curves of the simulated circuit. The algorithm uses a combination of source stepping and transient calculation with resistive damping. An adaption of method to superconducting quantum interference device (SQUID) threshold curve calculation is also discussed. The techniques are suitable and presented in sufficient detail, so that a reader may implement them as part of a general simulation program such as JSIM or SPICE     

CAD tools for efficient RF/microwave transistor modeling and circuit design

In today’s radiofrequency and microwave communication circuits, there is an ever-increasing demand for higher integration and miniaturization. This trend leads to massive computational tasks during simulation, optimization and statistical analyses, requiring robust modeling tools so that the whole process can be achieved reliably. In this paper, the authors proposed frequency- and time-domain computer-aided design tools that can characterize RF/microwave field effect and heterojunction bipolar transistors and efficiently predict a circuit performance. The proposed tools are demonstrated through examples.     

An efficient numerical approach for modeling microstrip-typeantennas

An efficient numerical approach to model antennas that include a microstrip element radiating in the presence of material layers is developed. The class of antennas considered is fed through the ground plane by a coaxial transmission line. The reaction integral equation is formulated by treating the coaxial aperture as part of the antenna. The substrate thickness can be arbitrary, making this numerical technique suitable for high-frequency applications. The effects of the substrate are also included in the analysis. Numerical results are obtained for the current distribution and input impedance. The algorithm is validated with experimental results     

An efficient systematic approach to model extraction for passivemicrowave circuits

This paper introduces a new systematic approach to equivalent circuit model extraction for linear microwave passive circuits directly from full-wave frequency domain simulation. The devices being modeled may be either lossless or lossy. Adaptive frequency sampling is used to minimize the computational effort of EM simulation while critically assisting in determining the pole locations of an RF circuit. A simple circuit model for lossy RF circuits along with a determined starting point of optimization of lumped element component values is also presented in detail. The overall result is an efficient and accurate means to produce a complete equivalent lumped element model for RF circuits that is suitable for use in conventional SPICE-like simulation software     

A fast 3D modeling approach to electrical parameters extraction ofbonding wires for RF circuits

Bonding wires are extensively used in integrated circuit (IC) packaging and circuit design in RF applications. An approach to fast three-dimensional (3D) modeling of the geometry for bonding wires in RF circuits and packages is demonstrated. The geometry can readily be used to extract electrical parameters such as inductance and capacitance. An equivalent circuit is presented to model the frequency response of bonding wires. To verify simulation accuracy, test structures have been made and measured. Excellent agreement between simulated and measured data is achieved for frequencies up to 10 GHz. The model is well suited for the design and analysis of circuits for cellular phone communication (i.e., order 2 GHz) and future wireless communication (i.e., order 5 GHz)