A fully planarized 4H-SiC trench MOS barrier Schottky (TMBS)rectifier

A fully planarized 4H-SiC trench MOS barrier Schottky (TMBS) rectifier has been designed, fabricated and characterized for the first time. The use of a TMBS structure helps improve the reverse leakage current by more than three orders of magnitude compared to that of a planar Schottky rectifier. We have achieved a low reverse leakage current density of 6×10^-6 A/cm² and a low forward voltage drop of 1.75 V at 60 A/cm² for the TMBS rectifier. The static current-voltage (I-V) and switching characteristics of the TMBS rectifier have been measured at various temperatures. A barrier height of 1.0 eV and an ideality factor of 1.8 were extracted from the forward characteristics. The switching characteristics do not change with temperature indicating the essential absence of stored charge     

Influence of the trench corner design on edge termination of UMOS power devices

In this article, the voltage blocking capability of UMOS power devices is experimentally demonstrated to be limited by the onset of a premature breakdown at the corners of the trench located at the device periphery. With the aid of numerical simulations performed in cylindrical co-ordinates, it is shown for the first time that a race-track shape of the trench gate fingers alleviates the electric fields at the trench corners and maximizes the UMOS voltage blocking capability. In addition, it is also shown that the breakdown voltage at the trench corners can be made to exceed the UMOS unit cell breakdown voltage by using a deep p diffusion around the trenches located at the device periphery.     

高压槽型SOI LDMOS槽区设计的普适方法

论文介绍了高压SOI槽型LDMOS不同槽介质,槽宽和槽深设计的普适方法。该方法考虑了击穿电压和导通电阻的折中关系。浅而宽的槽适合用高介电常数材料填充,深而窄的槽适合用低介电常数材料填充。论文还讨论了真空槽的情况。仿真结果表明由于器件总宽度的降低,采用低介电常数材料填充槽区可以获得更高的设计优值。     

A simpler 100-V polysilicon TFT with improved turn-oncharacteristics

An improved polysilicon high-voltage thin-film transistor (HVTFT) structure for eliminating the current-pinching phenomenon often observed in the conventional offset-gate polysilicon HVTFTs is discussed. The device employs, in lieu of implantation, a metal field plate overlapping the entire offset region to control the conductivity of the offset region. By properly biasing the field plate to distribute the drain electric field at both ends, high-voltage operation of up to 100 V, suitable for many large-area applications, is achieved. Good turn-on characteristics without current pinching effects are consistently obtained. The structure also eliminates the lightly doped drain implant required in conventional offset-gate HVTFTs, resulting in a simpler and more reproducible process     

100-V high-performance amplifiers in BCD technology for SLICapplications

The circuits described by the authors are a line driver and a sensing amplifier. They are part of a subscriber line interface circuits (SLIC) fabricated in BCD technology that operates up to 100 V. The driver requires about 500 μA of quiescent current, can sink and source up to 100 mA, and remains stable for all possible line lengths. The sensing amplifier senses the line current to synthesize both the AC and DC line terminations. It achieves a 2-mV offset and a gain-bandwidth product of 2.5 MHz. The adopted mixed technology allows the realization of a compact single-chip SLIC     

A high-linearity 100-element diode grid mixer

Grid-mixer arrays can achieve high linearity and dynamic range through quasi-optical power combining. We present a 100-element single-ended diode grid mixer operating at 2.45 GHz. Each element incorporates two diodes in series. We measure an input third-order intercept of 11 W (40.5 dBm), and output third-order intercept of 3.4 W (35.4 dBm), and an associated conversion loss of 5.1 dB. The power-handling capability of the array is 100 times larger than that of a microstrip mixer using a single element. The local oscillator (LO) drive requirement for the entire array is 1.4 W (31.6 dBm). The angular dependence of the array's IF power is also presented and is in agreement with theory     

一种用于sub-1V流水线ADC的新型低失调动态比较器

本文提出了一种适用于高速低电压流水线ADC的新型低失调动态比较器。在该比较器中,采用CMOS开关取代了差分对型比较器的两个动态尾电流源。这一改进保持了输入差分对管在比较时刻仍然像差分对型比较器一样工作在饱和区,从而确保该新型比较器拥有像差分对型比较器一样的低失调电压,并能进一步在sub-1V的苛刻条件下也正常工作。而且,它还具有大输入摆幅、低共模敏感度、以及线性的输入输出关系等优点。这种新结构的比较器与两种传统结构的比较器一起在中芯国际0.13微米CMOS工艺下流片验证。对比实测结果验证了此种比较器相对于传统结构的优势。该型比较器也已应用于一款12-bit 100MS/s 的流水线ADC中。     

A novel low-offset dynamic comparator for sub-1-V pipeline ADCs

A novel low-offset dynamic comparator for high-speed low-voltage analog-to-digital converters (ADCs) has been proposed.In the proposed comparator,a CMOS switch takes the place of the dynamic current sources in the differential comparator,which allows the differential input transistors still to operate in the saturation region at the comparing time.This gives the proposed comparator a low offset as the differential comparator while tolerating a sub-1-V supply voltage.Additionally,it also features a larger input swing,less sensitivity to common mode voltage,and a simple relationship between the input and reference voltage.This proposed comparator with two traditional comparators has been realized by SMIC 0.13μm CMOS technology.The contrast experimental results verify these advantages over conventional comparators.It has been used in a 12-bit 100-MS/s pipeline ADC.     

A novel temperature-stable light-emitting diode

A new type of light-emitting diode (LED) has been developed, the light intensity of which is stable during temperature change. This device consists of a multilayer dielectric optical filter on the surface of a conventional LED. The transmissivity of the optical filter is low for the short wavelength region of the LED's light spectrum and high for the long wavelength region. When the LED's temperature increases, the spectrum of LED light shifts toward the long wavelength side because of the shrinkage of the energy gap of the compound semiconductor. The shift increases the total transmission of the light because the transmissivity is high for the long wavelength region. This increase compensates for the decrease of the LED light intensity, which is caused by the decrease of the internal quantum efficiency. The effect of this filter is confirmed by both calculation and experiment     

A novel silicon Schottky diode for NLTL applications

The design and simulation of a novel silicon Schottky diode for nonlinear transmission line (NLTL) applications is discussed in this paper. The Schottky diode was fabricated on a novel silicon-on-silicide-on-insulator (SSOI) substrate for minimized series resistance. Ion implantation technology was used as a low-cost alternative to molecular beam epitaxy to approximate the delta (/spl delta/) doping profile, which results in strong nonlinear CV characteristics. The equivalent circuit model of the Schottky diode under reverse bias conditions was extracted from the S-parameter measurement performed on the diode. The measured CV characteristics show strong nonlinearity, the junction capacitance varies from 182 to 47.5 fF as the reverse bias voltage is varied from 0 to -5 V. A parasitic inductance of 40 pH was measured for the silicon Schottky diode, which is much smaller than a comparable sized GaAs Schottky diode. This small inductance is an advantage for the silicon Schottky diode offering improvement in the silicon NLTL performance.     

A novel planar diode mixer for submillimeter-wave applications

A mixer employing a planar GaAs Schottky diode has been designed and tested over a 300-365 GHz bandwidth. Using a planar diode eliminates the disadvantages of mechanical instability and labor-intensive assembly associated with conventional whisker-contacted diodes. The mixer design process uses scale model impedance measurements for both the design of individual components and the measurement of impedances presented to the diode terminals by the mixer mount at fundamental and harmonic frequencies. Results from these impedance measurements are used in linear and nonlinear numerical mixer analyses to predict the mixer performance     

Trench SJ IGBT 的仿真研究

本文对沟槽型超结绝缘栅双极晶体管(trench SJ IGBT)进行了全面的分析,并通过Sentaurus TCAD仿真软件将其与沟槽型场截止绝缘栅双极晶体管(trench FS IGBT)进行了详尽的对比,仿真结果显示,在相同的条件下与trench FS IGBT 相比,trench SJ IGBT 的击穿电压提高了100 V,饱和导通压降降低了0.2 V,关断损耗减少了50%。最后,文章研究了电荷不平衡对trench SJ IGBT 的动静态参数的影响。对各参数和它们对电荷不平衡的灵敏度之间的折中进行了讨论。     

A 55-V, 0.2-mΩ-cm2 vertical trench power MOSFET

Experimental results that demonstrate trench power MOSFETs with a specific on-state resistance of 0.2 mΩ-cm² and capable of sustaining 55 V across drain-source terminals in the off state are discussed. This performance was achieved by using an improved silicon trench processing technology. The forward conductivity reported is the highest ever obtained for a silicon power device     

A 1.5-V 14-bit 100-MS/s self-calibrated DAC

Large-area current source arrays are widely used in current-steering digital-to-analog converters (DACs) to statistically maintain a required level of matching accuracy between the current sources. This not only results in large die size but also in significant degradation of dynamic range for high-frequency signals. To overcome technology barriers, relax requirements on the layout, and reduce DAC sensitivities to process, temperature, and aging, calibration is emerging as a viable solution for the next-generation high-performance DACs. In this paper, a new foreground calibration technique suitable for very-low-voltage environments is presented which effectively compensates for current source mismatch, and achieves high linearity with small die size and low power consumption. Settling and dynamic performance are also improved due to a dramatic reduction of parasitic effects. To demonstrate this technique, a 14-bit DAC prototype was implemented in a 0.13-/spl mu/m digital CMOS process. This is the first CMOS DAC reported that operates with a single 1.5-V power supply and achieves 14-bit linearity with less than 0.1 mm/sup 2/ of active area. At 100 MS/s, the spurious free dynamic range is 82 dB (62 dB) for signals of 0.9 MHz (42 MHz) and the power consumption is only 16.7 mW.     

A 100-element planar Schottky diode grid mixer

The authors present a Schottky diode grid mixer suitable for mixing or detecting quasi-optical signals. The mixer is a planar bow-tie grid structure periodically loaded with diodes. A simple transmission line model is used to predict the reflection coefficient of the grid to a normally incident plane wave. The grid mixer power handling and dynamic range scales as the number of devices in the grid. A 10-GHz 100-element grid mixer has shown an improvement in dynamic range of 16.3 to 19.8 dB over an equivalent single-diode mixer. The conversion loss and noise figure of the grid are equal to those of a conventional mixer. The quasi-optical coupling of the input signals makes the grid mixer suitable for millimeter-wave and submillimeter-wave applications by eliminating waveguide sidewall losses and machining difficulties. The planar property of the grid potentially allows thousands of devices to be integrated monolithically     

一种新颖双馈电型PIN开关

微波光电二极管（PIN）开关速度和功率容量是相互矛盾的2个指标,为同时兼顾改善2个指标,结合半导体器件特性,采取PIN管芯两极同时馈电的设计形式（即双馈电型开关）,经过优化设计,研制出2 GHz～6 GHz单刀双掷PIN开关。与传统型开关电路相比,开关速度和功率容量都得到较好提升,为后续的工程应用奠定了基础。     

A novel trench capacitor enhancement approach by selective liquid-phase deposition

For the first time, a novel and simple trench bottle integrated process is demonstrated on dynamic random access memory (DRAM) manufacturing by selective liquid phase deposition (S-LPD) oxide. After photoresist (PR) filled into a deep trench (DT) and was recess etched at around 1.3 /spl mu/m depth, LPD oxide can be selected as a deposit onto the DT sidewall but not as a deposit on the PR surface. This S-LPD oxide is formed by using hexa-fluosilic acid (H/sub 2/SiF/sub 6/) and water without H/sub 3/BO/sub 3/. After the PR is removed, the LPD oxide becomes a protective layer on DT upper portion. Thus, the DT bottom area can be enlarged to form a trench bottle by NH/sub 4/OH wet etching. Compared to conventional DT trench, 20% of capacitance was enhanced by this S-LPD process. This novel and low-cost method is for the first time demonstrated on 200-mm wafer 110-nm trench DRAM technology.     

0.5-V analog circuit techniques and their application in OTA and filter design

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.     

A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder

This paper describes a 4-state rate-1/2 analog convolutional decoder fabricated in 0.8-μm CMOS technology. Although analog implementations have been described in the literature, this decoder is the first to be reported realizing the add-compare-select section entirely with current-mode analog circuits. It operates at data rates up to 115 Mb/s (channel rate 230 Mb/s) and consumes 39 mW at that rate from a single 2.8-V power supply. At a rate of 100 Mb/s, the power consumption per trellis state is about 1/3 that of a comparable digital system. In addition, at 50 Mb/s (the only rate at which comparative data were available), the power consumption per trellis state is similarly about 1/3 that of the best competing analog realization (i.e., excluding, for example, PR4 detectors which use a simplified form of the Viterbi algorithm). The chip contains 3.7 K transistors of which less than 1 K are used in the analog part of the decoder. The die has a core area of 1 mm², of which about 1/3 contains the analog section. The measured performance is close to that of an ideal Viterbi decoder with infinite quantization. In addition, a technique is described which extends the application of the circuits to decoders with a larger number of states. A typical example is a 64-state decoder for use in high-speed satellite communications     

A 0.25-μm CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-μm CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-μm CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs